JPH06224426A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06224426A JPH06224426A JP50A JP1055693A JPH06224426A JP H06224426 A JPH06224426 A JP H06224426A JP 50 A JP50 A JP 50A JP 1055693 A JP1055693 A JP 1055693A JP H06224426 A JPH06224426 A JP H06224426A
- Authority
- JP
- Japan
- Prior art keywords
- region
- drain
- drain region
- concentration
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 230000015556 catabolic process Effects 0.000 abstract description 19
- 230000007423 decrease Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は高耐圧横型絶縁ゲート型
バイポーラトランジスタ等の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a high voltage lateral insulated gate bipolar transistor.
【０００２】[0002]
【従来の技術】以下、従来の半導体装置としての高耐圧
横型絶縁ゲート型バイポーラトランジスタ（以降Ｌ−Ｉ
ＧＢＴと称する）を図面に基づいて説明する。2. Description of the Related Art A high breakdown voltage lateral insulated gate bipolar transistor (hereinafter referred to as LI) as a conventional semiconductor device will be described below.
(Referred to as GBT) will be described with reference to the drawings.
【０００３】図３は上記従来の半導体装置としてのＬ−
ＩＧＢＴ５０を示す断面図である。図３において、第１
導電型の半導体基板５１の表面部には第２導電型の延長
ドレイン領域５２が形成され、該延長ドレイン領域５２
の表面部には、第２導電型の高濃度ドレイン領域５３が
形成され、該高濃度ドレイン領域５３を取り囲むように
第１導電型の高濃度のドレイン隣接領域５４が形成され
ており、該ドレイン隣接領域５４は高濃度ドレイン領域
５３と電気的に接続されている。さらに、延長ドレイン
領域５２の表面部には高濃度ドレイン領域５３及びドレ
イン隣接領域５４を取り囲むように第１導電型の頂上領
域５５が形成されており、該頂上領域５５は半導体基板
５１と電気的に接続されている。また、半導体基板５１
の表面部には、第２導電型の高濃度ソース領域５６が形
成され、該高濃度ソース領域５６の中央部に第１導電型
の高濃度のソース隣接領域５７が形成され、高濃度ソー
ス領域５６を取り囲むように第１導電型の高濃度のチャ
ンネルストッパ５８が形成されている。そして、半導体
基板５１の表面上には、ドレイン隣接領域５４から高濃
度ソース領域５６に亙るゲート酸化膜６０と、高濃度ド
レイン領域５３及びドレイン隣接領域５４と電気的に接
続された断面Ｔ字形のドレイン電極６１と、高濃度ソー
ス領域５６及びソース隣接領域５７と電気的に接続され
た断面Ｔ字形のソース電極６２とが形成されており、ゲ
ート酸化膜６０の内部には延長ドレイン領域５２の端部
から高濃度ソース領域５６の端部に亙って多結晶シリコ
ン膜からなるゲート電極６３が形成されており、半導体
基板５１の表面部のゲート電極６３下にチャンネルが形
成される。FIG. 3 shows an L-type semiconductor device as the conventional semiconductor device.
It is sectional drawing which shows IGBT50. In FIG. 3, the first
A second conductivity type extended drain region 52 is formed on the surface of the conductivity type semiconductor substrate 51.
A second-conductivity-type high-concentration drain region 53 is formed on the surface of the first conductive-type drain region 53, and a first-conductivity-type high-concentration drain adjoining region 54 is formed so as to surround the high-concentration drain region 53. The adjacent region 54 is electrically connected to the high concentration drain region 53. Further, a first conductivity type top region 55 is formed on the surface of the extended drain region 52 so as to surround the high-concentration drain region 53 and the drain adjacent region 54, and the top region 55 is electrically connected to the semiconductor substrate 51. It is connected to the. In addition, the semiconductor substrate 51
A second-conductivity-type high-concentration source region 56 is formed on the surface portion of the first conductive-type high-concentration source region 56, and a first-conductivity-type high-concentration source adjacent region 57 is formed at the center of the high-concentration source region 56. A first conductive type high-concentration channel stopper 58 is formed so as to surround 56. Then, on the surface of the semiconductor substrate 51, the gate oxide film 60 extending from the drain adjacent region 54 to the high-concentration source region 56 and the T-shaped cross section electrically connected to the high-concentration drain region 53 and the drain adjacent region 54 are formed. A drain electrode 61 and a source electrode 62 having a T-shaped cross section that is electrically connected to the high-concentration source region 56 and the source adjacent region 57 are formed, and the end of the extended drain region 52 is formed inside the gate oxide film 60. A gate electrode 63 made of a polycrystalline silicon film is formed from the portion to the end of the high concentration source region 56, and a channel is formed below the gate electrode 63 on the surface of the semiconductor substrate 51.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記従
来の半導体装置としてのＬ−ＩＧＢＴにおいては、図３
に示すような頂上領域とドレイン隣接領域との間隔Ｘ２
が小さ過ぎると、ドレイン−ソース間の降伏電圧が低下
するという欠点がある。However, in the above-mentioned conventional L-IGBT as a semiconductor device, as shown in FIG.
X2 between the top region and the drain adjacent region as shown in
If is too small, there is a drawback that the breakdown voltage between the drain and the source decreases.
【０００５】そこで、考慮した結果、頂上領域とドレイ
ン隣接領域との間隔Ｘ２を４μｍに設定するとドレイン
−ソース間の降伏電圧が低下しないことが判明した。Therefore, as a result of consideration, it has been found that the breakdown voltage between the drain and the source does not decrease when the distance X2 between the top region and the drain adjacent region is set to 4 μm.
【０００６】ところが、インダクタンス負荷の回路に用
いた場合に、ゲートオフ時にインダクタンスの逆起電力
により、ドレイン−ソース間に内蔵されるダイオードが
降伏し過大な降伏電流がドレイン−ソース間に流れるこ
とによって、高濃度ソース領域下の電圧降下が約０．７
Ｖに達すると、第２導電型の高濃度ソース領域と第１導
電型の半導体基板と第２導電型の延長ドレイン領域とか
らなるバイポーラトランジスタが動作し、温度上昇を引
き起こし熱破壊に至るという課題に直面した。このとき
のＬ−ＩＧＢＴの消費エネルギー量を当該Ｌ−ＩＧＢＴ
のＡＤ耐量と称する。However, when it is used in an inductance load circuit, the counter electromotive force of the inductance when the gate is off causes the diode built in between the drain and the source to break down, and an excessive breakdown current flows between the drain and the source. Voltage drop under high concentration source region is about 0.7
When the voltage reaches V, the bipolar transistor including the second-conductivity-type high-concentration source region, the first-conductivity-type semiconductor substrate, and the second-conductivity-type extended drain region operates to cause a temperature rise and thermal destruction. Faced with. The energy consumption of the L-IGBT at this time is calculated as the L-IGBT.
Is called AD tolerance.
【０００７】本発明は上記に鑑みなされたものであっ
て、ドレイン−ソース間の降伏電圧を維持しＡＤ耐量を
増大させることができる半導体装置を提供することを目
的とする。The present invention has been made in view of the above, and an object thereof is to provide a semiconductor device capable of maintaining the breakdown voltage between the drain and the source and increasing the AD withstand voltage.
【０００８】[0008]
【課題を解決するための手段】上記の目的を達成するた
め、本発明は、延長ドレイン領域における頂上領域とド
レイン隣接領域との間の部位の抵抗値を所定値よりも増
大させることにより、第２導電型の高濃度ソース領域と
第１導電型の半導体基板と第２導電型の延長ドレイン領
域とからなるバイポーラトランジスタの動作を抑制する
ことによってＡＤ耐量を増大させるものである。In order to achieve the above-mentioned object, the present invention is to increase the resistance value of the portion between the summit region and the drain adjacent region in the extended drain region above a predetermined value. The AD withstand amount is increased by suppressing the operation of the bipolar transistor including the high-concentration source region of the second conductivity type, the semiconductor substrate of the first conductivity type, and the extended drain region of the second conductivity type.
【０００９】具体的に本発明が講じた解決手段は、Ｌ−
ＩＧＢＴ等の半導体装置を対象とし、、第１導電型の半
導体基板と、該半導体基板の表面部に形成された第２導
電型の延長ドレイン領域と、該延長ドレイン領域の表面
部に形成された第２導電型の高濃度ドレイン領域と、上
記半導体基板の表面部における上記延長ドレイン領域の
外部に形成された第２導電型の高濃度ソース領域と、上
記延長ドレイン領域の表面部における上記高濃度ドレイ
ン領域と高濃度ソース領域との間の部位に形成され且つ
上記半導体基板と電気的に接続された第１導電型の頂上
領域と、上記延長ドレイン領域の表面部における上記高
濃度ドレイン領域と頂上領域との間で該高濃度ドレイン
領域と隣接する部位に形成され且つ上記高濃度ドレイン
領域と電気的に接続された第１導電型の高濃度のドレイ
ン隣接領域とを備えており、上記頂上領域とドレイン隣
接領域との間隔は、上記延長ドレイン領域における上記
頂上領域とドレイン隣接領域との間の部位の抵抗値を所
定値よりも増大させる４μｍ以上の所定距離に設定され
ている構成とするものである。[0009] Specifically, the solving means taken by the present invention is L-
For a semiconductor device such as an IGBT, a semiconductor substrate of a first conductivity type, a second conductivity type extended drain region formed on a surface portion of the semiconductor substrate, and a surface portion of the extension drain region are formed. A second conductivity type high-concentration drain region, a second conductivity type high-concentration source region formed outside the extended drain region on the surface of the semiconductor substrate, and the high-concentration drain region on the surface of the extended drain region. A top region of the first conductivity type formed at a portion between the drain region and the high-concentration source region and electrically connected to the semiconductor substrate; and the high-concentration drain region and the top on the surface portion of the extended drain region. A high-concentration drain adjoining region of the first conductivity type that is formed between the high-concentration drain region and a region adjacent to the high-concentration drain region and is electrically connected to the high-concentration drain region. The distance between the top region and the drain-adjacent region is set to a predetermined distance of 4 μm or more that increases the resistance value of the portion between the top region and the drain-adjacent region in the extended drain region above a predetermined value. The configuration is as follows.
【００１０】[0010]
【作用】上記の構成により、頂上領域とドレイン隣接領
域との間隔は４μｍ以上の距離に設定されている。この
ため、ドレイン−ソース間の降伏電圧を低下させること
なく維持することができる。With the above structure, the distance between the top region and the drain adjacent region is set to 4 μm or more. Therefore, the breakdown voltage between the drain and the source can be maintained without lowering.
【００１１】さらに、頂上領域とドレイン隣接領域との
間隔は、延長ドレイン領域における頂上領域とドレイン
隣接領域との間の部位の抵抗値を所定値よりも増大させ
る所定距離に設定されている。ここで、上記所定値と
は、頂上領域とドレイン隣接領域との間隔が４μｍであ
る場合の、延長ドレイン領域における頂上領域とドレイ
ン隣接領域との間の部位の抵抗値を意味する。Further, the interval between the top region and the drain adjacent region is set to a predetermined distance that increases the resistance value of the portion between the top region and the drain adjacent region in the extended drain region above a predetermined value. Here, the predetermined value means a resistance value of a portion between the top region and the drain adjacent region in the extended drain region when the distance between the top region and the drain adjacent region is 4 μm.
【００１２】これにより、例えば、本発明に係る半導体
装置をインダクタンス負荷の回路に用いた場合にゲート
オフ時のインダクタンスの逆起電力によりドレイン−ソ
ース間に内蔵されるダイオードが降伏したとしても、延
長ドレイン領域における頂上領域とドレイン隣接領域と
の間の部位の抵抗が大きいため、高濃度ソース領域下を
流れる降伏電流は減少し、該降伏電流の減少分は半導体
基板の表面部から裏面部に流れる。Thus, for example, when the semiconductor device according to the present invention is used in an inductance load circuit, even if the diode built in between the drain and the source breaks down due to the counter electromotive force of the inductance when the gate is off, the extended drain Since the resistance of the region between the top region and the drain adjacent region is large, the breakdown current flowing under the high-concentration source region is reduced, and the reduced breakdown current flows from the front surface portion to the back surface portion of the semiconductor substrate.
【００１３】このように、高濃度ソース領域下を流れる
降伏電流を低減することができるため、高濃度ソース領
域下の電圧降下を低く抑えることができる。Since the breakdown current flowing under the high-concentration source region can be reduced as described above, the voltage drop under the high-concentration source region can be suppressed low.
【００１４】従って、第２導電型の高濃度ソース領域と
第１導電型の半導体基板と第２導電型の延長ドレイン領
域とからなるバイポーラトランジスタの動作を抑制する
ことができるのでＡＤ耐量を増大させることが可能であ
る。Therefore, it is possible to suppress the operation of the bipolar transistor including the high-concentration source region of the second conductivity type, the semiconductor substrate of the first conductivity type, and the extended drain region of the second conductivity type, so that the AD withstand capability is increased. It is possible.
【００１５】[0015]
【実施例】以下、本発明の一実施例を図面に基づいて説
明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
【００１６】図１は上記実施例に係る半導体装置として
のＬ−ＩＧＢＴ１０を示す断面図である。図１におい
て、第１導電型の半導体基板１１の表面部には第２導電
型の延長ドレイン領域１２が島状に形成され、該延長ド
レイン領域１２の表面部には第２導電型の高濃度ドレイ
ン領域１３が形成され、延長ドレイン領域１２の表面部
における高濃度ドレイン領域１３と隣接する部位に該高
濃度ドレイン領域１３を取り囲むように第１導電型の高
濃度のドレイン隣接領域１４が形成されており、該ドレ
イン隣接領域１４は高濃度ドレイン領域１３と電気的に
接続されている。さらに、延長ドレイン領域１２の表面
部には高濃度ドレイン領域１３及びドレイン隣接領域１
４を取り囲むように第１導電型の頂上領域１５が形成さ
れており、該頂上領域１５は半導体基板１１と電気的に
接続されており、頂上領域１５とドレイン隣接領域１４
との間隔Ｘ１は延長ドレイン領域１２における頂上領域
１５とドレイン隣接領域１４との間の部位の抵抗値を所
定値よりも増大させる４μｍ以上の所定距離である例え
ば１０μｍに設定されている。FIG. 1 is a sectional view showing an L-IGBT 10 as a semiconductor device according to the above embodiment. In FIG. 1, a second conductivity type extended drain region 12 is formed in an island shape on the surface part of the first conductivity type semiconductor substrate 11, and a high concentration of the second conductivity type is formed on the surface part of the extension drain region 12. The drain region 13 is formed, and the first-conductivity-type high-concentration drain adjoining region 14 is formed so as to surround the high-concentration drain region 13 in a portion of the surface of the extended drain region 12 adjacent to the high-concentration drain region 13. The drain adjacent region 14 is electrically connected to the high concentration drain region 13. Further, the high-concentration drain region 13 and the drain-adjacent region 1 are formed on the surface of the extended drain region 12.
4, a top region 15 of the first conductivity type is formed so as to surround 4, and the top region 15 is electrically connected to the semiconductor substrate 11, and the top region 15 and the drain adjacent region 14 are formed.
The distance X1 between and is set to, for example, 10 μm, which is a predetermined distance of 4 μm or more that increases the resistance value of the portion between the top region 15 and the drain adjacent region 14 in the extended drain region 12 above a predetermined value.
【００１７】また、半導体基板１１の表面部における延
長ドレイン領域１２の外部には第２導電型の高濃度ソー
ス領域１６が形成され、該高濃度ソース領域１６の中央
部には第１導電型の高濃度のソース隣接領域１７が形成
され、半導体基板１１の表面部における延長ドレイン領
域１２の外部において高濃度ソース領域１６を取り囲む
ように第１導電型の高濃度のチャンネルストッパ１８が
形成されている。A second conductivity type high-concentration source region 16 is formed outside the extended drain region 12 on the surface of the semiconductor substrate 11, and a first conductivity type high-concentration source region 16 is formed in the center of the high-concentration source region 16. A high-concentration source adjacent region 17 is formed, and a first-conductivity-type high-concentration channel stopper 18 is formed outside the extended drain region 12 on the surface portion of the semiconductor substrate 11 so as to surround the high-concentration source region 16. .
【００１８】そして、半導体基板１１の表面上には、ド
レイン隣接領域１４から高濃度ソース領域１６に亙るゲ
ート酸化膜２０と、高濃度ドレイン領域１３及びドレイ
ン隣接領域１４と電気的に接続された断面Ｔ字形のドレ
イン電極２１と、高濃度ソース領域１６及びソース隣接
領域１７と電気的に接続された断面Ｔ字形のソース電極
２２とが形成されており、ゲート酸化膜２０の内部には
延長ドレイン領域１２の端部から高濃度ソース領域１６
の端部に亙って多結晶シリコン膜からなるゲート電極２
３が形成されており、半導体基板１１の表面部のゲート
電極２３下にチャンネルが形成される。ここで、ソース
隣接領域１７は当該チャンネルの基板バイアス効果を抑
制するために形成されている。On the surface of the semiconductor substrate 11, the gate oxide film 20 extending from the drain adjacent region 14 to the high concentration source region 16 and the cross section electrically connected to the high concentration drain region 13 and the drain adjacent region 14 are formed. A T-shaped drain electrode 21 and a source electrode 22 having a T-shaped cross section electrically connected to the high-concentration source region 16 and the source adjoining region 17 are formed, and an extended drain region is formed inside the gate oxide film 20. High concentration source region 16 from the end of 12
Gate electrode 2 made of a polycrystalline silicon film over the edge of
3 is formed, and a channel is formed below the gate electrode 23 on the surface portion of the semiconductor substrate 11. Here, the source adjacent region 17 is formed in order to suppress the substrate bias effect of the channel.
【００１９】以上のように、本実施例に係る半導体装置
としてのＬ−ＩＧＢＴ１０においては、頂上領域１５と
ドレイン隣接領域１４との間隔Ｘ１は１０μｍに設定さ
れているため、ドレイン−ソース間の降伏電圧を低下さ
せることなく維持することができる。As described above, in the L-IGBT 10 as the semiconductor device according to the present embodiment, since the distance X1 between the top region 15 and the drain adjacent region 14 is set to 10 μm, the breakdown between the drain and the source is caused. The voltage can be maintained without being reduced.
【００２０】さらに、頂上領域１５とドレイン隣接領域
１４との間隔Ｘ１が１０μｍに設定されていることによ
り、延長ドレイン領域１２における頂上領域１５とドレ
イン隣接領域１４との間の部位の抵抗値が所定値よりも
増大する。ここで、上記所定値とは、頂上領域１５とド
レイン隣接領域１４との間隔Ｘ１が４μｍである場合
の、延長ドレイン領域１２における頂上領域１５とドレ
イン隣接領域１４との間の部位の抵抗値を意味する。Further, since the interval X1 between the top region 15 and the drain adjacent region 14 is set to 10 μm, the resistance value of the portion of the extended drain region 12 between the top region 15 and the drain adjacent region 14 is predetermined. Greater than the value. Here, the predetermined value is a resistance value of a portion between the top region 15 and the drain adjacent region 14 in the extended drain region 12 when the distance X1 between the top region 15 and the drain adjacent region 14 is 4 μm. means.
【００２１】これにより、例えば、Ｌ−ＩＧＢＴ１０を
インダクタンス負荷の回路に用いた場合にゲートオフ時
のインダクタンスの逆起電力によりドレイン−ソース間
に内蔵されるダイオードが降伏したとしても、延長ドレ
イン領域１２における頂上領域１５とドレイン隣接領域
１４との間の部位の抵抗が大きいため、高濃度ソース領
域１６下を流れる降伏電流は減少し、該降伏電流の減少
分は半導体基板１１の表面部から裏面部に流れる。Thus, for example, when the L-IGBT 10 is used in an inductance load circuit, even if the diode built in between the drain and the source breaks down due to the counter electromotive force of the inductance when the gate is off, in the extended drain region 12. Since the resistance between the top region 15 and the drain-adjacent region 14 is large, the breakdown current flowing under the high-concentration source region 16 is reduced, and the reduction amount of the breakdown current is from the front surface portion to the back surface portion of the semiconductor substrate 11. Flowing.
【００２２】このように、高濃度ソース領域１６下を流
れる降伏電流を低減することができるため、高濃度ソー
ス領域１６下の電圧降下を低く抑えることができる。As described above, since the breakdown current flowing under the high concentration source region 16 can be reduced, the voltage drop under the high concentration source region 16 can be suppressed low.
【００２３】従って、第２導電型の高濃度ソース領域１
６と第１導電型の半導体基板１１と第２導電型の延長ド
レイン領域１２とからなるバイポーラトランジスタの動
作を抑制することができるのでＡＤ耐量を増大させるこ
とが可能である。Therefore, the high-concentration source region 1 of the second conductivity type
6 and the semiconductor substrate 11 of the first conductivity type and the extended drain region 12 of the second conductivity type can suppress the operation of the bipolar transistor, so that the AD withstand capability can be increased.
【００２４】図２は、半導体装置のＡＤ耐量と、頂上領
域１５とドレイン隣接領域１４との間隔Ｘ１との関係を
示しており、ここでは、Ｘ１＝４μｍの場合の半導体装
置の単位面積当たりのＡＤ耐量の値を１としている。図
２に示すように、本実施例に係る半導体装置（Ｘ１＝１
０μｍ）によるとＸ１＝４μｍの場合に比較して単位面
積当たりのＡＤ耐量の値を１．７倍にすることが可能で
ある。FIG. 2 shows the relationship between the AD withstand capability of the semiconductor device and the distance X1 between the top region 15 and the drain adjoining region 14, where the unit area per unit area of the semiconductor device is X1 = 4 μm. The value of AD tolerance is 1. As shown in FIG. 2, the semiconductor device according to the present embodiment (X1 = 1
0 μm), it is possible to increase the value of the AD withstand amount per unit area by 1.7 times as compared with the case of X1 = 4 μm.
【００２５】[0025]
【発明の効果】以上説明したように、本発明に係る半導
体装置によると、頂上領域とドレイン隣接領域との間隔
が４μｍ以上の距離に設定されているため、ドレイン−
ソース間の降伏電圧を低下させることなく維持すること
ができる。さらに、頂上領域とドレイン隣接領域との間
隔が延長ドレイン領域における頂上領域とドレイン隣接
領域との間の部位の抵抗値を所定値よりも増大させる所
定距離に設定されているため、ドレイン−ソース間に内
蔵されるダイオードが降伏したとしても高濃度ソース領
域下を流れる降伏電流が低減され高濃度ソース領域下の
電圧降下を低く抑えることができる。このため、第２導
電型の高濃度ソース領域と第１導電型の半導体基板と第
２導電型の延長ドレイン領域とからなるバイポーラトラ
ンジスタの動作を抑制することができるのでＡＤ耐量を
増大させることができる。As described above, according to the semiconductor device of the present invention, the distance between the top region and the drain adjacent region is set to 4 μm or more.
The breakdown voltage between the sources can be maintained without lowering. Furthermore, since the distance between the top region and the drain-adjacent region is set to a predetermined distance that increases the resistance value of the portion between the top region and the drain-adjacent region in the extended drain region above a predetermined value, the drain-source Even if the diode built in the diode breaks down, the breakdown current flowing under the high-concentration source region is reduced, and the voltage drop under the high-concentration source region can be suppressed low. Therefore, the operation of the bipolar transistor including the second-conductivity-type high-concentration source region, the first-conductivity-type semiconductor substrate, and the second-conductivity-type extended drain region can be suppressed, so that the AD withstand capability can be increased. it can.
【００２６】従って、本発明によるとドレイン−ソース
間の降伏電圧を維持しＡＤ耐量を増大させることがで
き、半導体装置の過熱を防止し熱破壊から半導体装置を
保護することが可能である。Therefore, according to the present invention, it is possible to maintain the breakdown voltage between the drain and the source, increase the AD withstand voltage, prevent overheating of the semiconductor device, and protect the semiconductor device from thermal breakdown.
【図１】本発明の一実施例に係る半導体装置を示す断面
図である。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.
【図２】半導体装置のＡＤ耐量と、頂上領域とドレイン
隣接領域との間隔との関係を示す図である。FIG. 2 is a diagram showing a relationship between AD tolerance of a semiconductor device and a distance between a top region and a drain adjacent region.
【図３】従来の半導体装置を示す断面図である。FIG. 3 is a cross-sectional view showing a conventional semiconductor device.
１０ Ｌ−ＩＧＢＴ（半導体装置） １１ 半導体基板 １２ 延長ドレイン領域 １３ 高濃度ドレイン領域 １４ ドレイン隣接領域 １５ 頂上領域 １６ 高濃度ソース領域 10 L-IGBT (semiconductor device) 11 semiconductor substrate 12 extended drain region 13 high-concentration drain region 14 drain adjacent region 15 top region 16 high-concentration source region
Claims (1)
板の表面部に形成された第２導電型の延長ドレイン領域
と、該延長ドレイン領域の表面部に形成された第２導電
型の高濃度ドレイン領域と、上記半導体基板の表面部に
おける上記延長ドレイン領域の外部に形成された第２導
電型の高濃度ソース領域と、上記延長ドレイン領域の表
面部における上記高濃度ドレイン領域と高濃度ソース領
域との間の部位に形成され且つ上記半導体基板と電気的
に接続された第１導電型の頂上領域と、上記延長ドレイ
ン領域の表面部における上記高濃度ドレイン領域と頂上
領域との間で該高濃度ドレイン領域と隣接する部位に形
成され且つ上記高濃度ドレイン領域と電気的に接続され
た第１導電型の高濃度のドレイン隣接領域とを備えてお
り、 上記頂上領域とドレイン隣接領域との間隔は、上記延長
ドレイン領域における上記頂上領域とドレイン隣接領域
との間の部位の抵抗値を所定値よりも増大させる４μｍ
以上の所定距離に設定されていることを特徴とする半導
体装置。1. A semiconductor substrate of a first conductivity type, a second conductivity type extended drain region formed on a surface portion of the semiconductor substrate, and a second conductivity type extended drain region formed on a surface portion of the extension drain region. A high-concentration drain region, a second-conductivity-type high-concentration source region formed outside the extended drain region on the surface of the semiconductor substrate, and a high-concentration drain region and a high concentration on the surface of the extended drain region. Between the top region of the first conductivity type formed in a portion between the source region and electrically connected to the semiconductor substrate, and between the high-concentration drain region and the top region in the surface portion of the extended drain region. A first-conductivity-type high-concentration drain adjoining region formed adjacent to the high-concentration drain region and electrically connected to the high-concentration drain region; Distance between the drain flanking regions, 4 [mu] m to increase than the predetermined value the resistance value of the site between the top region and the drain flanking region of the extended drain region
A semiconductor device having the above predetermined distance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05010556A JP3076468B2 (en) | 1993-01-26 | 1993-01-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05010556A JP3076468B2 (en) | 1993-01-26 | 1993-01-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06224426A true JPH06224426A (en) | 1994-08-12 |
| JP3076468B2 JP3076468B2 (en) | 2000-08-14 |
Family
ID=11753532
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05010556A Expired - Fee Related JP3076468B2 (en) | 1993-01-26 | 1993-01-26 | Semiconductor device |
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| Country | Link |
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- 1993-01-26 JP JP05010556A patent/JP3076468B2/en not_active Expired - Fee Related
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