JPH06224425A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a high breakdown strength horizontal insulating gate type bipolar transistor capable of increasing an AD resistance. CONSTITUTION:A second conductive type extension drain region 12 is formed on the surface of a semiconductor substrate 11 of a first conductivity type. A high concentration drain region 13 of a second conductivity type is formed on the surface of the extension drain region 12, and high concentration drain adjacent regions 14 of the first conductivity type are electrically connected to the high concentration drain region 13 and are formed so as to surround the high concentration drain region 13, and a top region 15 of the first conductivity type is electrically connected to the semiconductor substrate 11 and is formed so as to surround the high concentration drain region 13 and the drain adjacent regions 14. High concentration source regions 16 of the second conductivity type are formed on the surface of the semiconductor substrate 11, and a source lower region 19 of the first conductivity type is formed below the high concentration source regions 16. A resistance value below the high concentration source regions 16 is reduced by the source lower region 19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a high voltage lateral insulated gate bipolar transistor.

[0002]

2. Description of the Related Art A high breakdown voltage lateral insulated gate bipolar transistor (hereinafter referred to as LI) as a conventional semiconductor device will be described below.
(Referred to as GBT) will be described with reference to the drawings.

FIG. 3 shows an L-type semiconductor device as the conventional semiconductor device.
It is sectional drawing which shows IGBT50. In FIG. 3, the first
A second conductivity type extended drain region 52 is formed on the surface of the conductivity type semiconductor substrate 51.
A second-conductivity-type high-concentration drain region 53 is formed on the surface of the first conductive-type drain region 53, and a first-conductivity-type high-concentration drain adjoining region 54 is formed so as to surround the high-concentration drain region 53. The adjacent region 54 is electrically connected to the high concentration drain region 53. Further, a first conductivity type top region 55 is formed on the surface of the extended drain region 52 so as to surround the high-concentration drain region 53 and the drain adjacent region 54, and the top region 55 is electrically connected to the semiconductor substrate 51. It is connected to the. In addition, the semiconductor substrate 51
A second-conductivity-type high-concentration source region 56 is formed on the surface portion of the first conductive-type high-concentration source region 56, and a first-conductivity-type high-concentration source adjacent region 57 is formed at the center of the high-concentration source region 56. A first conductive type high-concentration channel stopper 58 is formed so as to surround 56. Then, on the surface of the semiconductor substrate 51, the gate oxide film 60 extending from the drain adjacent region 54 to the high-concentration source region 56 and the T-shaped cross section electrically connected to the high-concentration drain region 53 and the drain adjacent region 54 are formed. A drain electrode 61 and a source electrode 62 having a T-shaped cross section that is electrically connected to the high-concentration source region 56 and the source adjacent region 57 are formed, and the end of the extended drain region 52 is formed inside the gate oxide film 60. A gate electrode 63 made of a polycrystalline silicon film is formed from the portion to the end of the high concentration source region 56, and a channel is formed below the gate electrode 63 on the surface of the semiconductor substrate 51.

[0004]

However, in the above-mentioned conventional L-IGBT as a semiconductor device, when it is used in a circuit of an inductance load, it is built in between the drain and the source due to the counter electromotive force of the inductance when the gate is off. When the voltage drop under the high-concentration source region reaches about 0.7 V due to the diode breakdown and an excessive breakdown current flowing between the drain and the source, the high-concentration source region of the second conductivity type and the first conductivity type The bipolar transistor including the semiconductor substrate and the second-conductivity-type extended drain region operates, causing a temperature rise and causing thermal destruction. The amount of energy consumed by the L-IGBT at this time is referred to as the AD tolerance of the L-IGBT.

The present invention has been made in view of the above, and an object thereof is to provide a semiconductor device capable of increasing the AD withstand capability.

[0006]

In order to achieve the above-mentioned object, the present invention reduces the resistance value under the high-concentration source region to reduce the resistance value of the second-conductivity-type high-concentration source region and the first-conductivity-type. The AD withstand capability is increased by suppressing the operation of the bipolar transistor including the semiconductor substrate and the second conductivity type extended drain region.

[0007] Specifically, the solution means taken by the present invention is L-
For a semiconductor device such as an IGBT, a semiconductor substrate of a first conductivity type, a second conductivity type extended drain region formed on a surface portion of the semiconductor substrate, and a surface portion of the extension drain region are formed. A second conductivity type high-concentration drain region, a second conductivity type high-concentration source region formed outside the extended drain region on the surface of the semiconductor substrate, and the high-concentration drain region on the surface of the extended drain region. A top region of the first conductivity type formed at a portion between the drain region and the high-concentration source region and electrically connected to the semiconductor substrate; and the high-concentration drain region and the top on the surface portion of the extended drain region. A first-conductivity-type high-concentration drain adjoining region which is formed between the high-concentration drain region and a region adjacent to the high-concentration drain region and is electrically connected to the high-concentration drain region; It is an arrangement and a source under region of the first conductivity type to reduce the resistance value under the high-concentration source region is formed on the lower side of the high concentration source region in the surface portion of the semiconductor substrate.

[0008]

With the above structure, the first-conductivity-type source lower region is formed below the second-conductivity-type high-concentration source region, and the resistance value under the high-concentration source region is reduced by the source-lower region. It can be reduced. Therefore, for example, when the semiconductor device according to the present invention is used in a circuit of an inductance load, even if an excessive breakdown current flows between the drain and the source due to the counter electromotive force of the inductance when the gate is off, Since it is possible to suppress the voltage drop of the low voltage, it is possible to suppress the operation of the bipolar transistor including the high-concentration source region of the second conductivity type, the semiconductor substrate of the first conductivity type, and the extended drain region of the second conductivity type. Therefore, it is possible to increase the AD tolerance.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing an L-IGBT 10 as a semiconductor device according to the above embodiment. In FIG. 1, a second conductivity type extended drain region 12 is formed in an island shape on the surface part of the first conductivity type semiconductor substrate 11, and a high concentration of the second conductivity type is formed on the surface part of the extension drain region 12. The drain region 13 is formed, and the first-conductivity-type high-concentration drain adjoining region 14 is formed so as to surround the high-concentration drain region 13 in a portion of the surface of the extended drain region 12 adjacent to the high-concentration drain region 13. The drain adjacent region 14 is electrically connected to the high concentration drain region 13. Further, the high-concentration drain region 13 and the drain-adjacent region 1 are formed on the surface of the extended drain region 12.
A top region 15 of the first conductivity type is formed so as to surround 4 and the top region 15 is electrically connected to the semiconductor substrate 11.

A second conductivity type high-concentration source region 16 is formed outside the extended drain region 12 on the surface of the semiconductor substrate 11, and a first conductivity type high-concentration source region 16 is formed in the center of the high-concentration source region 16. A high-concentration source adjacent region 17 is formed, and a first-conductivity-type high-concentration channel stopper 18 is formed outside the extended drain region 12 on the surface portion of the semiconductor substrate 11 so as to surround the high-concentration source region 16. High concentration source region 1 on substrate 11
A source lower region 19 of the first conductivity type is formed under 6 and the source adjacent region 17, and the source lower region 19 is formed at the same time as the top region 15.

On the surface of the semiconductor substrate 11, a cross section electrically connected to the gate oxide film 20 extending from the drain adjacent region 14 to the high concentration source region 16 and the high concentration drain region 13 and the drain adjacent region 14 is formed. A T-shaped drain electrode 21 and a source electrode 22 having a T-shaped cross section electrically connected to the high-concentration source region 16 and the source adjoining region 17 are formed, and an extended drain region is formed inside the gate oxide film 20. High concentration source region 16 from the end of 12
Gate electrode 2 made of a polycrystalline silicon film over the edge of
3 is formed, and a channel is formed below the gate electrode 23 on the surface portion of the semiconductor substrate 11. Here, the source adjacent region 17 is formed in order to suppress the substrate bias effect of the channel.

As described above, in the L-IGBT 10 as the semiconductor device according to the present embodiment, the first conductivity type is formed below the second conductivity type high concentration source region 16 at the same time as the top region 15. The source lower region 19 is formed, and the resistance value under the high concentration source region 16 can be reduced by the source lower region 19. So, for example,
When the L-IGBT 10 is used in an inductance load circuit, even if an excessive breakdown current flows between the drain and the source due to the counter electromotive force of the inductance when the gate is off, the voltage drop under the high-concentration source region 16 is kept low. Therefore, the operation of the bipolar transistor including the second-conductivity-type high-concentration source region 16, the first-conductivity-type semiconductor substrate 11, and the second-conductivity-type extended drain region 12 can be suppressed, so that the AD withstand capability is improved. It can be increased.

FIG. 2 shows the AD tolerance of the semiconductor device according to this embodiment and the AD tolerance of the conventional semiconductor device. Here, the value of the AD tolerance per unit area of the conventional semiconductor device is 1. . As shown in FIG. 2, the semiconductor device according to the present embodiment can increase the value of the AD withstand amount per unit area by 1.6 times as compared with the conventional semiconductor device.

[0015]

As described above, according to the semiconductor device of the present invention, the high-concentration source region is formed under the first-conductivity-type source region formed below the second-conductivity-type high-concentration source region. The resistance value of can be reduced. With this, even if an excessive breakdown current flows between the drain and the source, the voltage drop under the high-concentration source region can be suppressed to a low level. Therefore, the high-concentration source region of the second conductivity type and the semiconductor substrate of the first conductivity type are suppressed. Since it is possible to suppress the operation of the bipolar transistor including the second conductive type extended drain region, it is possible to increase the AD tolerance.

Therefore, according to the present invention, it is possible to prevent the semiconductor device from overheating and protect the semiconductor device from thermal destruction.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing the AD tolerance of the semiconductor device according to the above embodiment and the AD tolerance of the conventional semiconductor device.

FIG. 3 is a cross-sectional view showing a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 L-IGBT (semiconductor device) 11 Semiconductor substrate 12 Extended drain region 13 High concentration drain region 14 Drain adjacent region 15 Top region 16 High concentration source region 19 Source lower region

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, a second conductivity type extended drain region formed on a surface portion of the semiconductor substrate, and a second conductivity type extended drain region formed on a surface portion of the extension drain region. A high-concentration drain region, a second-conductivity-type high-concentration source region formed outside the extended drain region on the surface of the semiconductor substrate, and a high-concentration drain region and a high concentration on the surface of the extended drain region. Between the top region of the first conductivity type formed in a portion between the source region and electrically connected to the semiconductor substrate, and between the high-concentration drain region and the top region in the surface portion of the extended drain region. A high-concentration drain adjacent region of the first conductivity type formed in a portion adjacent to the high-concentration drain region and electrically connected to the high-concentration drain region, and a surface portion of the semiconductor substrate. And a source lower region of the first conductivity type that is formed below the high-concentration source region and reduces the resistance value under the high-concentration source region.