JPH05335584A - Vertical mos field effect transistor - Google Patents
Vertical mos field effect transistorInfo
- Publication number
- JPH05335584A JPH05335584A JP4140507A JP14050792A JPH05335584A JP H05335584 A JPH05335584 A JP H05335584A JP 4140507 A JP4140507 A JP 4140507A JP 14050792 A JP14050792 A JP 14050792A JP H05335584 A JPH05335584 A JP H05335584A
- Authority
- JP
- Japan
- Prior art keywords
- region
- source
- well region
- gate electrode
- well
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 14
- 230000003071 parasitic effect Effects 0.000 description 5
- 230000006378 damage Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、縦型ＭＯＳ構造をし
た電界効果トランジスタに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor having a vertical MOS structure.
【０００２】[0002]
【従来の技術】以下、従来の大出力用縦型ＭＯＳ電界効
果トランジスタ（以下パワーＭＯＳＦＥＴという）につ
いて説明する。図２は従来のパワーＭＯＳＦＥＴのセル
構造を示す図で、同図（ａ）はそのパターンが正方形の
もの、（ｂ）はそのパターンがストライプのものを示
し、（ｃ）はセルの断面構造を示している。図２におい
て、１はドレイン領域、２はゲート酸化膜、３は多結晶
シリコンからなるゲート電極、４はウェル領域、５はソ
ース領域、６は層間絶縁膜、７はソース電極、８はドレ
イン電極を示している。2. Description of the Related Art A conventional large output vertical MOS field effect transistor (hereinafter referred to as power MOSFET) will be described below. 2A and 2B are views showing a cell structure of a conventional power MOSFET. FIG. 2A shows a square pattern, FIG. 2B shows a stripe pattern, and FIG. 2C shows a cross-sectional structure of the cell. Shows. In FIG. 2, 1 is a drain region, 2 is a gate oxide film, 3 is a gate electrode made of polycrystalline silicon, 4 is a well region, 5 is a source region, 6 is an interlayer insulating film, 7 is a source electrode, and 8 is a drain electrode. Is shown.
【０００３】図２に示すように、縦型構造のＭＯＳＦＥ
Ｔは一般的に拡散自己整合、いわゆるＤ−ＭＯＳ( Ｄｉ
ｆｆｕｓｅｄ ｓｅｌｆ ａｌｉｇｎｅｄ) 構造をして
いる。すなわち、ドレイン領域１となるシリコン基板表
面上にゲート酸化膜２および多結晶シリコンからなるゲ
ート電極３を並設してリソグラフィ工程によりゲート電
極３を格子状あるいはストライプ状に形成し、ゲート電
極３をマスクとして自己整合拡散によりドレイン領域１
とは逆導電型のウェル領域４とソース領域５を形成し、
ゲート電極３に対して層間絶縁膜６を形成してリソグラ
フィ工程を経た後にソ−ス電極７およびドレイン電極８
を形成したものである。図中二点鎖線はソース領域５の
中心を示す。As shown in FIG. 2, a vertical structure MOSFE is provided.
T is generally diffusion self-alignment, so-called D-MOS (Di
It has a fused self aligned structure. That is, the gate oxide film 2 and the gate electrode 3 made of polycrystalline silicon are juxtaposed on the surface of the silicon substrate to be the drain region 1, and the gate electrode 3 is formed in a lattice shape or a stripe shape by a lithography process. Drain region 1 by self-aligned diffusion as a mask
And a well region 4 and a source region 5 of opposite conductivity type are formed,
After the interlayer insulating film 6 is formed on the gate electrode 3 and a lithography process is performed, the source electrode 7 and the drain electrode 8 are formed.
Is formed. In the figure, the alternate long and two short dashes line indicates the center of the source region 5.
【０００４】なお、ウェル領域４はゲート電極３を除い
た領域全面に形成され、一方ソース領域５はゲート電極
３を除いた領域の中心部を除いて形成されるので、チャ
ネルの形成される領域はゲート電極３に沿った領域に形
成されることになる。Since the well region 4 is formed on the entire surface of the region excluding the gate electrode 3, the source region 5 is formed excluding the central portion of the region excluding the gate electrode 3, so that the region where the channel is formed. Will be formed in a region along the gate electrode 3.
【０００５】[0005]
【発明が解決しようとする課題】従来のパワーＭＯＳＦ
ＥＴにおいては、図２に示すように、ソース領域５はゲ
ート電極と隣接して存在し、チャネル領域であるウェル
領域４とソース電極７との接続部はソース領域５とソー
ス電極７の接続部よりもゲート電極３から離れた位置に
あるので、図３に示すように、ＭＯＳＦＥＴがブレーク
ダウンするとブレークダウン電流１１はソース領域５下
のウェル領域４を通ることになる。このため、この部分
の抵抗成分１２による電圧降下が大きくなると、ソース
領域５、ウェル領域４、ドレイン領域１で形成される寄
生のバイポーラトランジスタ１３が動作し、パワーＭＯ
ＳＦＥＴは発熱により破壊される。このように従来のパ
ワーＭＯＳＦＥＴの構造では、逆方向の安全動作領域
（以下Ｒ−ＡＳＯという）が狭いという問題点があっ
た。Conventional power MOSF
In ET, as shown in FIG. 2, the source region 5 exists adjacent to the gate electrode, and the connection between the well region 4 which is the channel region and the source electrode 7 is the connection between the source region 5 and the source electrode 7. As shown in FIG. 3, when the MOSFET breaks down, the breakdown current 11 passes through the well region 4 below the source region 5 because it is located farther from the gate electrode 3. Therefore, when the voltage drop due to the resistance component 12 in this portion becomes large, the parasitic bipolar transistor 13 formed by the source region 5, the well region 4 and the drain region 1 operates and the power MO
The SFET is destroyed by heat generation. As described above, the structure of the conventional power MOSFET has a problem that the reverse safe operation area (hereinafter referred to as R-ASO) is narrow.
【０００６】したがって、この発明の目的は、逆方向安
全動作領域の向上を図ることができる縦型ＭＯＳ電界効
果トランジスタを提供することである。Therefore, an object of the present invention is to provide a vertical MOS field effect transistor capable of improving the backward safe operation area.
【０００７】[0007]
【課題を解決するための手段】この発明の縦型ＭＯＳ電
界効果トランジスタは、ドレイン領域となる一導電型の
半導体基板内に形成された他導電型のウェル領域内に一
導電型のソース領域を形成し、チャネル領域となる前記
ウェル領域上にゲート酸化膜を介してゲート電極を形成
するとともに、コンタクト窓部でウェル領域およびソー
ス領域をソース電極に電気的に接続した縦型ＭＯＳ電界
効果トランジスタであって、ウェル領域内のソース領域
をゲート電極に隣接した側で広くコンタクト窓部側で狭
く形成し、ソース領域が形成されないウェル領域の部位
をウェル領域からソース電極へ向かうブレーク電流用バ
イパス領域としている。In the vertical MOS field effect transistor of the present invention, a source region of one conductivity type is formed in a well region of another conductivity type formed in a semiconductor substrate of one conductivity type to be a drain region. A vertical MOS field effect transistor in which a gate electrode is formed on the well region to be a channel region via a gate oxide film, and the well region and the source region are electrically connected to the source electrode at the contact window portion. The source region in the well region is formed wide on the side adjacent to the gate electrode and narrow on the contact window side, and the portion of the well region where the source region is not formed is used as a break current bypass region from the well region to the source electrode. There is.
【０００８】[0008]
【作用】この発明の構成によれば、ウェル領域内のソー
ス領域をゲート電極に隣接した側で広く、コンタクト窓
部側で狭く形成し、ソース領域が形成されないウェル領
域の部位をウェル領域からソース電極へ向かうブレーク
電流用バイパス領域としているので、ＭＯＳＦＥＴのブ
レークダウン時に流れるブレークダウン電流は、このバ
イパス領域を流れる。このため、ソース領域、ウェル領
域、ドレイン領域で形成される寄生のバイポーラトラン
ジスタは動作しにくくなり、パワーＭＯＳＦＥＴの破壊
が抑制される。また、ゲート電極に接したソース領域を
広くすることで、ゲート幅が広くなり、飽和電流を減少
させずに降伏時の耐性が向上する。According to the structure of the present invention, the source region in the well region is formed wide on the side adjacent to the gate electrode and narrow on the contact window side, and the portion of the well region where the source region is not formed is sourced from the well region. Since the bypass region for the break current toward the electrode is used, the breakdown current flowing at the breakdown of the MOSFET flows through this bypass region. For this reason, the parasitic bipolar transistor formed in the source region, the well region, and the drain region becomes difficult to operate, and the destruction of the power MOSFET is suppressed. Further, by widening the source region in contact with the gate electrode, the gate width becomes wider, and the resistance against breakdown is improved without reducing the saturation current.
【０００９】[0009]
【実施例】以下、この発明の実施例について図面を参照
しながら説明する。図１は、この発明の実施例であるパ
ワーＭＯＳＦＥＴのセル構造を示す図で、同図（ａ）は
正方形パターンのもの、（ｂ）はストライプパターンの
もの、（ｃ）（ｄ）はそれぞれ（ａ）および（ｂ）にお
けるＡ−Ａ’、Ｂ−Ｂ’間で切断したセルの断面構造を
示している。図１において従来例を示す図２と同一符号
を付したものは同じものを示す。Embodiments of the present invention will be described below with reference to the drawings. 1A and 1B are views showing a cell structure of a power MOSFET according to an embodiment of the present invention. FIG. 1A is a square pattern, FIG. 1B is a stripe pattern, and FIGS. The sectional structure of the cell cut | disconnected between AA 'and BB' in (a) and (b) is shown. In FIG. 1, the same reference numerals as those in FIG. 2 showing the conventional example indicate the same parts.
【００１０】実施例にかかるパワーＭＯＳＦＥＴは、従
来と同様の製造工程により製造されるが、図１（ａ）
（ｂ）に示すように、ウェル領域４内にソース領域５が
形成される部位でのソース領域５の形成を、ゲート電極
３に隣接した側のゲート電極３の形成方向に平行な幅を
広くし、コンタクト窓部１０側に向かう程狭くなるよう
にして形成している。また、ソース領域５が形成されな
いウェル領域４の部位は、ウェル領域４からソース電極
７へ向かうブレーク電流用バイパス領域９とし、その形
成されない領域を上記とは逆にコンタクト窓部１０側で
広く、ゲート電極側で狭く形成している。図中二点鎖線
はソース領域５の中心を示す。The power MOSFET according to the embodiment is manufactured by the same manufacturing process as the conventional one, but FIG.
As shown in (b), the source region 5 is formed in a region where the source region 5 is formed in the well region 4 by increasing the width parallel to the formation direction of the gate electrode 3 on the side adjacent to the gate electrode 3. However, it is formed so as to become narrower toward the contact window portion 10 side. Further, the portion of the well region 4 where the source region 5 is not formed is a break current bypass region 9 extending from the well region 4 to the source electrode 7, and the region where the source region 5 is not formed is wide on the contact window portion 10 side, contrary to the above. It is formed narrow on the gate electrode side. In the figure, the alternate long and two short dashes line indicates the center of the source region 5.
【００１１】このように、ソース領域５は、セル構造が
正方形パターンでもストライプパターンであっても、上
記したようにゲート電極３側において広く、ソース電極
７のコンタクト窓部１０側で狭くなるように形成され、
ソース領域５が形成されないウェル領域４の部位には、
ウェル領域４からソース電極７へ向かうブレーク電流用
バイパス領域９として作用するので、ＭＯＳＦＥＴのブ
レークダウン時に流れるブレークダウン電流は、このブ
レーク電流用バイパス領域９（ソース領域のない部分）
を流れる。このため、ソース領域５、ウェル領域４、ド
レイン領域１で形成される寄生のバイポーラトランジス
タは動作しにくくなり、パワーＭＯＳＦＥＴの破壊が抑
制される。In this way, the source region 5 is wide on the gate electrode 3 side and narrow on the contact window 10 side of the source electrode 7, as described above, regardless of whether the cell structure is a square pattern or a stripe pattern. Formed,
In the well region 4 where the source region 5 is not formed,
Since it acts as a break current bypass region 9 extending from the well region 4 to the source electrode 7, the breakdown current flowing at the time of breakdown of the MOSFET is the break current bypass region 9 (a part without the source region).
Flowing through. Therefore, the parasitic bipolar transistor formed by the source region 5, the well region 4, and the drain region 1 becomes difficult to operate, and the destruction of the power MOSFET is suppressed.
【００１２】また、ゲート電極３に接したソース領域５
を広くすることで、ゲート幅が広くなり、ＭＯＳＦＥＴ
の飽和電流をあまり減らさずに上記の効果を引き出すこ
とができ、基板バイアス降下を低減することもできる。The source region 5 in contact with the gate electrode 3
The gate width becomes wider by increasing the
The above effect can be brought out without significantly reducing the saturation current of (3), and the substrate bias drop can also be reduced.
【００１３】[0013]
【発明の効果】この発明の縦型ＭＯＳ電界効果トランジ
スタは、ブレークダウンが生じても、ウェル領域内のソ
ース領域をゲート電極に隣接した側で広く、ウェル領域
とソース領域とをソース電極に接続するコンタクト窓部
側で狭く形成し、ソース領域が形成されないウェル領域
の部位をウェル領域からソース電極へ向かうブレーク電
流用バイパス領域としているので、ＭＯＳＦＥＴのブレ
ークダウン時に流れるブレークダウン電流がブレーク電
流用バイパス領域を流れ、ソース領域、ウェル領域、ド
レイン領域で形成される寄生のバイポーラトランジスタ
が動作しにくくなる。このため、パワーＭＯＳＦＥＴの
破壊が抑制され、逆方向安全動作領域の向上を図ること
ができる。また、ゲート電極に接したソース領域を広く
することで、ゲート幅が広くなり、飽和電流を減少させ
ずに逆方向安全動作領域の向上を図ることができる。According to the vertical MOS field effect transistor of the present invention, even if a breakdown occurs, the source region in the well region is wide on the side adjacent to the gate electrode, and the well region and the source region are connected to the source electrode. Since the region of the well region where the source region is not formed is the bypass region for the break current from the well region to the source electrode, the breakdown current flowing during the MOSFET breakdown is bypassed for the break current. The parasitic bipolar transistor that flows through the region and is formed of the source region, the well region, and the drain region becomes difficult to operate. Therefore, destruction of the power MOSFET is suppressed, and the reverse safe operation area can be improved. In addition, by widening the source region in contact with the gate electrode, the gate width becomes wider, and the reverse safe operation region can be improved without reducing the saturation current.
【図１】（ａ）（ｂ）はこの発明の実施例であるパワー
ＭＯＳＦＥＴのセルのパターンを示す図であり、（ｃ）
（ｄ）はそれぞれ（ａ）および（ｂ）におけるＡ−
Ａ’、Ｂ−Ｂ’間で切断したセルの断面構造を示す図で
ある。1A and 1B are views showing a cell pattern of a power MOSFET according to an embodiment of the present invention, and FIG.
(D) is A- in (a) and (b), respectively.
It is a figure which shows the cross-section of the cell cut | disconnected between A'and BB '.
【図２】（ａ）（ｂ）は従来例のパワーＭＯＳＦＥＴの
セルのパターンを示す図であり、（ｃ）は（ａ）（ｂ）
に示すセルの断面構造を示す図である。2A and 2B are diagrams showing a cell pattern of a power MOSFET of a conventional example, and FIG. 2C is a diagram of FIGS.
It is a figure which shows the cross-section of the cell shown in FIG.
【図３】パワーＭＯＳＦＥＴのブレークダウン電流の流
れ方と寄生バイポーラトランジスタを示す図である。FIG. 3 is a diagram showing a breakdown current flow of a power MOSFET and a parasitic bipolar transistor.
１ ドレイン領域 ２ ゲート酸化膜 ３ ゲート電極 ４ ウェル領域 ５ ソース領域 ６ 層間絶縁膜 ７ ソース電極 ８ ドレイン電極 ９ ブレーク電流用バイパス領域 10 コンタクト窓部 1 Drain Region 2 Gate Oxide Film 3 Gate Electrode 4 Well Region 5 Source Region 6 Interlayer Insulation Film 7 Source Electrode 8 Drain Electrode 9 Break Current Bypass Region 10 Contact Window
Claims (1)
板内に形成された他導電型のウェル領域内に一導電型の
ソース領域を形成し、チャネル領域となる前記ウェル領
域上にゲート酸化膜を介してゲート電極を形成するとと
もに、コンタクト窓部で前記ウェル領域およびソース領
域をソース電極に電気的に接続した縦型ＭＯＳ電界効果
トランジスタであって、 前記ウェル領域内のソース領域を、前記ゲート電極に隣
接した側で広くコンタクト窓部側で狭く形成し、前記ソ
ース領域が形成されないウェル領域の部位を前記ウェル
領域から前記ソース電極へ向かうブレーク電流用バイパ
ス領域としたことを特徴とする縦型ＭＯＳ電界効果トラ
ンジスタ。1. A source region of one conductivity type is formed in a well region of another conductivity type formed in a semiconductor substrate of one conductivity type to be a drain region, and a gate oxide film is formed on the well region to be a channel region. A vertical MOS field-effect transistor in which a gate electrode is formed via the well and the well region and the source region are electrically connected to a source electrode at a contact window portion, and the source region in the well region is connected to the gate. The vertical type is characterized in that it is formed wide on the side adjacent to the electrode and narrow on the side of the contact window, and the portion of the well region where the source region is not formed is a bypass region for break current from the well region to the source electrode. MOS field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4140507A JPH05335584A (en) | 1992-06-01 | 1992-06-01 | Vertical mos field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4140507A JPH05335584A (en) | 1992-06-01 | 1992-06-01 | Vertical mos field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05335584A true JPH05335584A (en) | 1993-12-17 |
Family
ID=15270260
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4140507A Pending JPH05335584A (en) | 1992-06-01 | 1992-06-01 | Vertical mos field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05335584A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004022693A (en) * | 2002-06-14 | 2004-01-22 | Toshiba Corp | Semiconductor device |
| US8129758B2 (en) | 2008-07-09 | 2012-03-06 | Panasonic Corporation | Semiconductor element and manufacturing method therefor |
-
1992
- 1992-06-01 JP JP4140507A patent/JPH05335584A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004022693A (en) * | 2002-06-14 | 2004-01-22 | Toshiba Corp | Semiconductor device |
| JP4537646B2 (en) * | 2002-06-14 | 2010-09-01 | 株式会社東芝 | Semiconductor device |
| US8129758B2 (en) | 2008-07-09 | 2012-03-06 | Panasonic Corporation | Semiconductor element and manufacturing method therefor |
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