JP3100755B2 - Vertical MOS field-effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor having a vertical MOS structure.

[0002]

2. Description of the Related Art FIG. 3 is a view showing the structure of a conventional high power vertical MOS field effect transistor (hereinafter referred to as a power MOSFET). FIG.
FIG. 2B is a plan view showing a mask of T, and FIG.
It is a figure which shows the cross-section of the cell cut | disconnected between -B '. In FIG. 3, 1 is a drain region, 2 is a gate oxide film, 3
Is polycrystalline silicon, 4 is a high concentration region, 5 is a well region,
6 is a source region, 7 is an interlayer insulating film, 8 is a source electrode, 9
Indicates a drain electrode.

[0003] As shown in FIG.
T is generally a diffusion self-alignment, so-called D-MOS (Di
(fused self aligned) structure. That is, a gate oxide film 2 is formed on the surface of a silicon substrate to be a drain region 1, and a polycrystalline silicon film 3 is formed on the gate oxide film 2 by a lithography process in a lattice shape. A high-concentration region 4 having a conductivity type opposite to that of the drain region 1 is formed in a rectangular shape without contacting the polycrystalline silicon film 3 from above, and the polycrystalline silicon film 3 is used as a mask to form a high concentration region 4 opposite to the drain region 1 by self-aligned diffusion. A source region 6 of the same conductivity type as that of the well region 5 and the drain region 1 is formed, an interlayer insulating film 7 is formed on the polycrystalline silicon film 3, and a lithography process is performed. 8 and a drain electrode 9 are formed.

[0004]

However, in the conventional structure described above, when the power load of the power MOSFET is an inductive load such as a motor or a solenoid, the power MOSFET is connected to the junction between the drain region 1 and the well region 5. When the breakdown occurs, a parasitic bipolar transistor formed by the source region 6, the well region 5, and the drain region 1 operates, and the power MOSFET is destroyed by heat generation. In the case of breakdown, the depletion layer extends from the adjacent well region inside the chip, so that the curvature is relaxed and an apparently stair-junction state is obtained. Is not relaxed, resulting in a spherical joint. For this reason, the breakdown current concentrates on the periphery of the chip and mainly destroys the periphery of the chip. Thus, in the structure of the conventional power MOSFET,
There is a problem that the safe operation area in the reverse direction (hereinafter referred to as R-ASO) is narrow.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a field effect transistor having a vertical MOS structure capable of improving a safe reverse operation area.

[0006]

A vertical MOS field-effect transistor according to the present invention is formed around a chip of a plurality of well regions of another conductivity type formed in a semiconductor substrate of one conductivity type serving as a drain region. A gate electrode in the well region and a gate pad, which is a wire bonding part for the gate electrode, are electrically connected via a resistor having a high sheet resistance.

[0007]

According to the structure of the present invention, even if a breakdown occurs, since the sheet resistance of the gate of the power MOSFET formed around the chip is high, it takes a long time to close the channel, and during that time, the peripheral portion of the chip A concentrated breakdown current flows from the drain electrode to the source electrode through the channel of the MOSFET. Therefore, the operation of the parasitic bipolar transistor at the periphery of the chip is suppressed, and the power MOSFET can be prevented from being broken.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A power MOSFET according to an embodiment of the present invention will be described below with reference to the drawings. FIG.
FIG. 2A is a plan view showing a mask of a power MOSFET integrated on a single silicon chip according to an embodiment of the present invention, and FIG. 2B is a sectional view taken along the line AA ′ in FIG. It is a figure showing a section structure. In FIG. 1A, the same components as those in FIG. 3 showing the conventional example are denoted by the same reference numerals, and the description thereof is omitted.

A power MOSFE according to an embodiment of the present invention.
As shown in FIG. 1, T is formed so that polycrystalline silicon 21 serving as a gate electrode at the periphery of the chip surrounds the periphery of the chip in a stripe shape. The polycrystalline silicon 22, which is another gate electrode, is formed in a lattice shape. The lattice-shaped polycrystalline silicon 22 is directly connected to a gate pad 24 serving as a gate electrode wire bonding portion, and the striped polycrystalline silicon 21 is made of polycrystalline silicon or amorphous silicon having a high sheet resistance. It is connected to a gate pad 24 via a resistor 23.

Therefore, the power MOSF of the embodiment is
ET is, as shown in FIG. 2, a power MOSFET (hereinafter referred to as a MOS) existing in a peripheral portion of a chip having a high resistance gate.
-A) and other power MOSFETs (hereinafter M
OS-B) is connected in parallel.
The operation of the embodiment device configured as described above will be described. In the circuit shown in FIG. 2, when the gate is turned off, the channel of the MOS-B is closed. However, MOS-A
Takes a long time to close the channel because the gate resistance 23 is large. If a breakdown occurs, a breakdown current concentrated in the peripheral portion while the channel closes will flow from the drain electrode 1 to the source electrode 8 through the MOS-A channel. For this reason, the operation of the parasitic bipolar transistor generated in the peripheral portion of the chip is suppressed, so that the power MOSFET can be prevented from being destroyed and the reverse safe operation area can be expanded.

FIG. 4 is a characteristic diagram showing the R-ASO level, and shows that the R-ASO level of the above-described embodiment device is about twice as large as that of the conventional device.

[0012]

According to the vertical MOS field effect transistor of the present invention, even if a breakdown occurs, it takes a long time to close the channel because the sheet resistance of the gate of the power MOSFET formed around the chip is high. In the meantime, the breakdown current concentrated on the peripheral portion of the chip passes through the channel of this MOSFET and escapes from the drain electrode to the source electrode, so that the operation of the parasitic bipolar transistor on the peripheral portion of the chip is suppressed, and the power M
It is possible to prevent the OSFET from being destroyed and to extend the reverse safe operation area.

[Brief description of the drawings]

FIG. 1A is a plan view showing a power MOSFET mask integrated on a single silicon chip according to an embodiment of the present invention, and FIG. 1B is an AA ′ portion in FIG. FIG. 3 is a diagram illustrating a cross-sectional structure of a cut cell.

FIG. 2 is a circuit diagram showing an equivalent circuit of a power MOSFET in the embodiment.

FIG. 3A is a plan view showing a mask of a power MOSFET integrated on a single silicon chip as a conventional example, and FIG. 3B is a cell cut along a line BB ′ in FIG. FIG. 3 is a view showing a sectional structural view of FIG.

FIG. 4 is a comparison diagram of R-ASO levels.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Drain region 2 Gate oxide film 3 Polycrystalline silicon 4 High concentration region 5 Well region 6 Source region 7 Interlayer insulating film 8 Source electrode 9 Drain electrode 21 Striped polycrystalline silicon 22 Lattice polycrystalline silicon 23 High resistance 24 Gate pad

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (1)

(57) [Claims] A gate electrode of a well region formed around a chip among a plurality of well regions of another conductivity type formed in a semiconductor substrate of one conductivity type serving as a drain region, and a wire bonding part for a gate electrode. A vertical MOS field-effect transistor wherein a certain gate pad is electrically connected via a high-resistance body having a high sheet resistance.