CN107564815A - A kind of method for making power semiconductor - Google Patents
A kind of method for making power semiconductor Download PDFInfo
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- CN107564815A CN107564815A CN201610507639.8A CN201610507639A CN107564815A CN 107564815 A CN107564815 A CN 107564815A CN 201610507639 A CN201610507639 A CN 201610507639A CN 107564815 A CN107564815 A CN 107564815A
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Abstract
A kind of method for making power semiconductor, this method include：Step 1: the gate oxide of preset thickness is formed on substrate；Step 2: the gate oxide of preset thickness being performed etching so that gate oxide has multi-thickness, wherein, the trend gradually increased is presented from first end to the second end for the thickness of gate oxide；Step 3: form polysilicon layer on gate oxide after etching.Compared to existing power semiconductor preparation method, the power semiconductor that this method makes to obtain is more smooth, its technique (such as mark alignment, photoetching and etching etc.) difficulty is effectively reduced, and so also helps to improve the performance of power semiconductor and the reliability of chip package function.
Description
Technical field
The present invention relates to electric and electronic technical field, specifically, is related to a kind of side for making power semiconductor
Method.
Background technology
Power semiconductor is the basis of Power Electronic Technique and its application apparatus, is to promote converters hair
The main source of exhibition.Power semiconductor is in the heart status of modern power electronic converter, and it can to device
Played a very important role by property, cost and performance.Wherein, triode thyristor, gate turn off thyristor and
Insulated gate bipolar transistor (IGBT) is successively referred to as the development platform of power semiconductor.
The thickness of the gate oxide of (plane) grid-controlled type power semiconductor (such as IGBT) for
The size of gate capacitance has direct influence, and this also and then have impact on the threshold voltage of whole power semiconductor
And switching characteristic.In order to reduce gate capacitance, prior art be typically by the way of gate oxide thickness is increased come
Realize.And if considering threshold voltage simultaneously, then requiring the thickness of gate oxide needs optimal compromise.
However, the optimal compromise mode of gate oxide thickness causes gate oxidation used by existing power semiconductor
The surface irregularity of layer and to easily cause gate oxide surface topography discontinuous.
The content of the invention
To solve the above problems, the invention provides a kind of method for making power semiconductor, methods described includes：
Step 1: the gate oxide of preset thickness is formed over the substrate；
Step 2: the gate oxide of the preset thickness is performed etching so that the gate oxide has a variety of
Thickness, wherein, the trend gradually increased is presented from first end to the second end for the thickness of the gate oxide；
Step 3: form polysilicon layer on gate oxide after etching.
According to one embodiment of present invention, the thickness of the most thick opening position of the gate oxide after etching is its most thin position
Put more than 8 times of the thickness at place.
According to one embodiment of present invention, in the step 2, the gate oxidation to the preset thickness is passed through
Layer performs etching so that the thickness of the gate oxide is along first end to the second linear increase.
According to one embodiment of present invention, in the step 2, the gate oxidation to the preset thickness is passed through
Layer carries out multiple etching, forms the multiple intervals being sequentially connected,
Each odd number interval is flat bed section in the multiple interval, and each even number interval is oblique interval；Or,
Each odd number interval is oblique interval in the multiple interval, and each even number interval is flat bed section；
Wherein, the flat bed section keeps constant interval for the thickness of each opening position, and the tiltedly interval is thickness
The interval linearly increased.
According to one embodiment of present invention, in the step 2, the gate oxidation to the preset thickness is passed through
Layer carries out multiple etching, forms the multiple intervals being sequentially connected, and the multiple interval forms step structure, its
In, the thickness of the interval more remote apart from the first end is bigger.
According to one embodiment of present invention, in the multiple interval the farthest interval of first end described in distance length
Half of the degree less than half cellular thickness of power semiconductor.
According to one embodiment of present invention, the thickness of the polysilicon layer position is equal.
According to one embodiment of present invention, before the gate oxide of the preset thickness is formed, methods described is also
First window is formed over the substrate, and is formed in the substrate using the first window and led with first
The enhanced carrier layer of electric type, P- bases are formed in the enhanced carrier layer.
According to one embodiment of present invention, after the polysilicon layer is formed, methods described is also in the polycrystalline
Form the second window in silicon layer and gate oxide, and is formed in the substrate using second window and to have the
The enhanced carrier layer of one conduction type, P- bases are formed in the enhanced carrier layer.
According to one embodiment of present invention, after the P- bases are formed, the also described P- bases of methods described
Middle source area of the formation with the first conduction type and the ohmic contact regions with the second conduction type, wherein, institute
State the centre position that ohmic contact regions are located at the P- bases.
According to one embodiment of present invention, the thickness of the ohmic contact regions is more than the thickness of the source area.
According to one embodiment of present invention, methods described also includes：
Cushion is formed on another surface of the substrate；
Collector area is formed on the cushion.
According to one embodiment of present invention, according to one embodiment of present invention, methods described also includes：
Short dot is formed on the collector area.
Power semiconductor method for semiconductor manufacturing provided by the present invention enables to gate oxidation in power semiconductor
The linear change of layer, therefore it can effectively avoid the device surface present in existing power semiconductor high convex and not
The defects of continuous.Compared to existing power semiconductor, power semiconductor provided by the present invention is more smooth,
Its technique (such as mark alignment, photoetching and etching etc.) difficulty is effectively reduced, so also helps to carry
The performance of high power semiconductor device and the reliability of chip package function.
The gate oxide of power semiconductor provided by the present invention can using photoetching and the etching technics of standard come
Made, without additionally developing specific photoetching and etching technics for step gates structure, therefore can be saved
Process exploitation cost.Meanwhile gate oxide is using the multiple substep photoetching knot shallower with the ratio of etching formation
Structure, therefore can avoid carrying out single deep etching, this also just reduces technology difficulty.
Other features and advantages of the present invention will be illustrated in the following description, also, partly from specification
In become apparent, or by implement the present invention and understand.The purpose of the present invention and other advantages can pass through
Specifically noted structure is realized and obtained in specification, claims and accompanying drawing.
Brief description of the drawings
Accompanying drawing shows the various embodiments of each aspect of the present invention, and they are used to explain together with specification
The principle of the present invention.Those skilled in the art will appreciate that specific embodiment shown in the drawings is only example
Property, and they are not intended to limit the scope of the present invention.It should be appreciated that in some examples, it is illustrated
One element can also be designed to multiple element, or multiple element can also be designed to an element.
In some examples, another element can also be implemented as by being shown as the element of the internal part of another element
External component, vice versa.In order to which clearer, of the invention in detail exemplary embodiment is so that this area
Technical staff can understand more thorough to the advantages of each aspect of the present invention and its feature, and now accompanying drawing is carried out
Introduce, in the accompanying drawings：
Fig. 1 is the structural representation of existing power semiconductor；
Fig. 2 is the structural representation of the cellular of power semiconductor half according to an embodiment of the invention；
Fig. 3 is the structural representation of the cellular of power semiconductor half according to an embodiment of the invention；
Fig. 4 is the structural representation of the cellular of power semiconductor half according to an embodiment of the invention；
Fig. 5 is the structural representation of the cellular of power semiconductor half according to an embodiment of the invention；
Fig. 6 is the structural representation of the cellular of power semiconductor half according to an embodiment of the invention；
Fig. 7 is the structural representation of the cellular of power semiconductor half according to an embodiment of the invention；
Fig. 8 and Fig. 9 is the flow according to an embodiment of the invention for making power semiconductor as shown in Figure 7
Figure.
Embodiment
Embodiments of the present invention are described in detail below with reference to drawings and Examples, whereby to the present invention such as
What application technology means solves technical problem, and the implementation process for reaching technique effect can be fully understood and evidence
To implement.As long as it should be noted that do not form conflict, each embodiment in the present invention and each implement
Example in each feature can be combined with each other, the technical scheme formed protection scope of the present invention it
It is interior.
Meanwhile in the following description, many details are elaborated for illustrative purposes, to provide to this
The thorough understanding of inventive embodiments.It will be apparent, however, to one skilled in the art, that this hair
It is bright to implement without detail here or described ad hoc fashion.
In addition, can be in the meter of such as one group computer executable instructions the flow of accompanying drawing illustrates the step of
Performed in calculation machine system, although also, show logical order in flow charts, in some situations
Under, can be with the step shown or described by being performed different from order herein.
As shown in figure 1, for existing plane grid-controlled type power semiconductor, its gate oxide uses
One trapezoidal design, by setting one layer of thin gate oxide, remote in the opening position close to raceway groove
The opening position of raceway groove sets a thickness gate oxide, to realize that reduction gate capacitance, optimization power semiconductor are opened
The effect of characteristic is closed, while can also adjusting threshold voltage characteristic.However, how design of thin, thick grating oxide layer
Ratio (packet length, the ratio of thickness), the size of gate capacitance can be directly affected, and then influence switching characteristic
With the optimal compromise of threshold voltage characteristic.Also, most importantly, the design of existing gate oxide,
The pattern of device surface is influenceed very big, it is easy to the high convex and discontinuous of device surface is caused, so as to influence
The planarization of device surface.This not only cause the technique of device realize difficulty increase, can also influence device performance with
And the reliability of chip package.
For the above-mentioned problems in the prior art, the invention provides a kind of new power semiconductor, the work(
The thickness smooth variation of the gate oxide of rate semiconductor, it can so improve the planarization on power semiconductor surface,
The technology difficulty of gate oxide is reduced, while chip performance and package reliability can also be improved.
In order to more clearly illustrate the structure of power semiconductor provided by the present invention and advantage, individually below
Power semiconductor provided by the present invention is further detailed with reference to different embodiments, meanwhile, by
In the structure of power semiconductor provided by the present invention be symmetrical, therefore in order to aspect describe, following examples
In illustrated with half structure cell.
Embodiment one：
Fig. 2 shows the structural representation of half cellular of the power semiconductor that the present embodiment is provided.
As shown in Fig. 2 the power semiconductor that the present embodiment is provided preferably includes：Substrate 201, first are led
Electric region, gate oxide 202 and polysilicon layer 203.Wherein, in the present embodiment, the first conductive region shape
Into in substrate 201, it includes：Enhanced carrier layer 204 with the first conduction type, with second
The P- basic units 205 of conduction type, the source area 206 with the first conduction type and with the second conduction type
Ohmic contact regions 207.In the present embodiment, the conduction type of substrate 201 is the first conduction type.
In the present embodiment, enhanced carrier layer 204 is formed in substrate 201.Making enhanced carrier
During layer 204, layer of oxide layer is deposited on the substrate 201 first, the thickness of the oxide layer is preferably not
More than 0.5 μm, then the oxide layer formed is performed etching, so as to produce enhanced carrier layer 204
Injection/doping window.After injection/doping window of enhanced carrier layer 204 is obtained, using the injection/
Doping window carries out injection/doping of enhanced carrier layer into substrate 201, then carries out high temperature propulsion/expansion
Dissipate, so as to form a doping concentration enhanced carrier layer 204 higher than substrate 201.In the present embodiment,
The doping concentration of enhanced carrier layer 204 is preferably more than 1e15/cm3。
, it is necessary to further be formed in enhanced carrier layer 204 after enhanced carrier layer 204 is obtained
P- basic units 205.In the present embodiment, increase because the injection using enhanced carrier layer 204/doping window is formed
During strong type carrier layer 204, high temperature promotes technique that the thickness of oxide layer is added, therefore now
Need first to perform etching the increased oxide layer of thickness, to form the injection of P- bases/doping window.
After injection/doping window of P- bases is formed, you can using the window to enhanced carrier layer 204
Injection/doping of P- bases is carried out, then carries out high temperature propulsion/DIFFUSION TREATMENT, so as in enhanced carrier layer
P- bases 205 are formed in 204.In the present embodiment, the doping concentration of P- bases 205 is preferably e17/cm3
Magnitude.
It is pointed out that in other embodiments of the invention, according to being actually needed, enhanced carrier layer
The doping concentration of 204 and/or P- bases 205 can also be other reasonable values, and the invention is not restricted to this.
Similarly, source area 206 and Europe can be formed respectively in P- bases 205 using same method
Nurse contact zone 207, its specific forming process will not be repeated here.In the present embodiment, ohmic contact regions 207
Thickness is preferably more than the thickness of source area 206.
As shown in Fig. 2 in the present embodiment, gate oxide 202 is formed on the substrate 201, and gate oxide
202 contact close to one end of source area 206 with source area 206.Polysilicon layer 207 is formed in gate oxide 202
On, the thickness of its position preferably keeps constant.
In order to avoid existing power semiconductor because thin, thickness portion the thickness difference of gate oxide is excessive and caused by
The problem of technology difficulty is big, process uniformity control is poor, and thus caused power semiconductor surface is high
Convex and discontinuous problem, the gate oxide for the power semiconductor that the present embodiment is provided employ new table top
Grid structure.Specifically, as shown in Fig. 2 gate oxide 202 has multi-thickness, and led with first
The increase of the distance between electric region center line, the thickness of gate oxide linearly increase.
In the structure cell of power semiconductor half as shown in Figure 2, the first end of gate oxide 202 is (i.e. in figure
Left end point) positioned at the top of source area 206, the second end (right endpoint i.e. in figure) aligns with cellular edge.
Wherein, the first end of gate oxide 202 can be to be regarded as the starting point of gate oxide, and the second end can be regarded as grid oxygen
Change the terminal of layer.In the present embodiment, the thickness of gate oxide 202 is, grid linearly increasing by origin-to-destination
Thickness D of the oxide layer at start position1Preferably general thickness (such as 0.1 μm), gate oxide is at end
The thickness D of point opening position2Preferably more than 10 times (such as 1 μm) of starting point thickness.
It is pointed out that in other embodiments of the invention, according to being actually needed, gate oxide 202
Thickness at start position can also be for his Rational Thickness, while the thickness at final position can also be
Other are more than the value of the thickness at start position, and (such as thickness of the gate oxide at final position is start position
8 times of place's thickness are with first-class), the invention is not restricted to this.
, can be to enter after obtaining completing the making of source area 206 and ohmic contact regions 207 in the present embodiment
The making of row gate oxide 202 and polysilicon layer 203.Specifically, in the present embodiment, first in substrate 201
And first to form a thickness on conductive region be D2SiO2Layer, then using multiple photoetching and the side of etching
Method, so that SiO2The thickness of layer linearly changes.
Obtaining the SiO of the thickness linear change2After layer, in the SiO2The polycrystalline of a specific thicknesses is formed on layer
Silicon layer, and carry out N-type polycrystalline silicon doping.In the present embodiment, the thickness of polysilicon layer is preferably less than 0.5 μm,
Its doping concentration is preferably in 1e19/cm3More than.Certainly, in other embodiments of the invention, according to reality
Need, the thickness and doping concentration of polysilicon layer can also be other reasonable values, and the invention is not restricted to this.
After completing said process, in the present embodiment, also to being covered in ohmic contact regions 207 and source area 206
On part SiO2Layer and polysilicon layer carry out photoetching or etching, so as to ultimately form power as shown in Figure 2
Semiconductor structure.
It is pointed out that in other embodiments of the invention, the material of gate oxide can also select other
Reasonable material, the invention is not restricted to this.It is also desirable to, it is noted that in other embodiments of the invention,
Source area 206 and ohmic contact regions 207 in gate oxide 202 and polysilicon layer 203 also to complete
After made, due to its specific manufacturing process those skilled in the art by foregoing description it is known that
Therefore it will not be repeated here.
In the present embodiment, power semiconductor is also including the cushion 208 with the first conduction type and with second
The collector area 209 of conduction type.Wherein, for cushion shape 208 on another surface of substrate 201, its is excellent
Selection of land includes first buffer layer 208a and second buffer layer 208b.It is to be noted that in other realities of the present invention
Apply in example, cushion 208 both can only include a Rotating fields, can also include more than three layers structures, the present invention
Not limited to this.
Collector area 209 is formed on cushion 208, as shown in Fig. 2 in the present embodiment, collector area
Formed with some short dots 210 with the first conduction type in 209.
In the present embodiment, during cushion 208, collector area 209 and short dot 210 is made,
Moved back first with high temperature (being greater than 1000 DEG C) diffusion or ion implanting+low temperature (such as less than 500 DEG C)
The mode of fire forms one or more N buffer layer structures on the surface of substrate 201, so as to obtaining cushion 208.
Come to form P+ current collections on the surface of cushion 208 followed by the mode of High temperature diffusion or ion implanting+laser annealing
Polar region 209.Finally, come also with the mode of High temperature diffusion or ion implanting+laser annealing in P+ colelctor electrodes
Some N+ short dots 210 are formed in area 209.
It is pointed out that in different embodiments of the invention, for the thicker power semiconductor of thickness, its
The order of positive technique and back process (technical process for making cushion, collector area and short dot) can
To be adjusted, i.e., it both can first carry out back process and carry out positive technique again, and can also first carry out positive technique
Back process is carried out again.And for needing to carry out thinned power semiconductor again to enter, it is necessary to first carry out positive technique
Row back process, and can not overleaf have pyroprocess in technique.
As can be seen that gate oxide linearly becomes in the power semiconductor that the present embodiment is provided from foregoing description
Change, therefore it can effectively avoid the device surface height present in existing power semiconductor convex and discontinuous scarce
Fall into.Compared to existing power semiconductor, the power semiconductor that the present embodiment is provided is more smooth, its technique
(such as mark alignment, photoetching and etching etc.) difficulty is effectively reduced, and so also helps to improve power
The performance of semiconductor devices and the reliability of chip package function.
The gate oxide for the power semiconductor that the present embodiment is provided can use photoetching and the etching technics of standard
To be made, without additionally developing specific photoetching and etching technics for step gates structure, therefore can save
About process exploitation cost.Meanwhile gate oxide is shallower using the ratio of multiple substep photoetching and etching formation
Structure, therefore can avoid carrying out single deep etching, this also just reduces technology difficulty.
Embodiment two：
Fig. 3 shows the structural representation for the cellular of power semiconductor half that the present embodiment is provided.
Comparison diagram 2 and Fig. 3 can be seen that the power semiconductor that the present embodiment is provided and provided with embodiment one
Power semiconductor only exist in gate oxide and polysilicon layer it is different, therefore, for convenience of description, together
When protrude above-mentioned difference, the gate oxide only to power semiconductor in the present embodiment and polysilicon layer are carried out below
Further illustrate.
As shown in figure 3, in the present embodiment, gate oxide includes two intervals, i.e. the 1st interval and the 2nd interval.
Wherein, the projected length of the 1st interval and the 2nd interval on substrate is respectively L1And L2.Come for the 1st interval
Say, with the increase with ohmic contact regions center line distance, its thickness keeps constant, i.e., thickness is D always1；And
For the 2nd interval, with the increase with ohmic contact regions center line distance, its thickness is by D1Linearly increase to
D2。
Certainly, in other embodiments of the invention, with the increase with ohmic contact regions center line distance, power
The thickness of gate oxide first can also linearly increase in semiconductor keeps constant again, that is, forms knot as shown in Figure 4
Structure.
It is pointed out that for the power semiconductor shown in Fig. 4, in order to avoid the gate oxide institute of big thickness
Accounting example is excessive, the length L of its 2nd interval2The preferably less than half of the cellular length of power semiconductor half, with
By the threshold voltage control of power semiconductor in the reasonable scope.
Embodiment three：
Fig. 5 shows the structural representation for the cellular of power semiconductor half that the present embodiment is provided.
Comparison diagram 2 and Fig. 5 can be seen that the power semiconductor that the present embodiment is provided and provided with embodiment one
Power semiconductor only exist in gate oxide and polysilicon layer it is different, therefore, for convenience of description, together
When protrude above-mentioned difference, the gate oxide only to power semiconductor in the present embodiment and polysilicon layer are carried out below
Further illustrate.
As shown in figure 5, in the present embodiment, gate oxide includes three intervals, i.e. the 1st interval, the 2nd interval
With the 3rd interval.Wherein, projected length of these three intervals on substrate is respectively L1、L2And L3.For
For 1 interval, with the increase with ohmic contact regions center line distance, its thickness keeps constant, i.e., thickness is kept
In D1；For the 2nd interval, with the increase with ohmic contact regions center line distance, its thickness is by D1Line
Property increases to D2；For the 3rd interval, with the increase with ohmic contact regions center line distance, its thickness is protected
Hold constant, i.e., thickness is maintained at D2。
It is pointed out that in other embodiments of the invention, the interval number n that gate oxide is included may be used also
Think other reasonable values, the invention is not restricted to this.For example, when gate oxide includes 7 intervals, power half
The structure of conductor will be as shown in Figure 6.
Simultaneously, it is necessary to which explanation, excessive in order to avoid the gate oxide proportion of big thickness, its is last
The length L of one interval (i.e. n-th layer section)nThe preferably less than cellular length L of power semiconductor half half, with
By the threshold voltage control of power semiconductor in the reasonable scope.Exist：
L1+L2+...+Ln-1＞ L/2
It is pointed out that when gate oxide includes multiple intervals, it both can be in this multiple interval
Odd number interval is flat bed section (i.e. as the increase with ohmic contact regions center line distance, thickness keep constant layer
Section), even number interval is oblique interval (i.e. as the increase with ohmic contact regions center line distance, thickness linearly increase
Interval) or this multiple interval in odd number interval be oblique interval and even number interval is basic unit's section, this
Invention not limited to this.
In addition, for each interval in multiple intervals, its projected length on substrate is advantageously equal,
L be present1=L2=...=Ln, and the slope of each tiltedly interval is also preferably equal.
Example IV：
Fig. 7 shows the structural representation for the cellular of power semiconductor half that the present embodiment is provided.
Comparison diagram 2 and Fig. 7 can be seen that the power semiconductor that the present embodiment is provided and provided with embodiment one
Power semiconductor only exist in gate oxide and polysilicon layer it is different, therefore, for convenience of description, together
When protrude above-mentioned difference, the gate oxide only to power semiconductor in the present embodiment and polysilicon layer are carried out below
Further illustrate.
As shown in fig. 7, in the present embodiment, gate oxide includes four intervals, i.e. the 1st interval, the 2nd interval,
3rd interval and the 4th interval.Wherein, this four intervals are flat bed section, the projection length on its each comfortable substrate
Degree is respectively L1、L2、L3And L4, so just form stair-stepping gate oxide structure.
In the present embodiment, the length for multiple intervals that gate oxide is included preferably is equal to each other, that is, exists
L1=L2=L3=L4.Meanwhile, its last layer excessive in order to avoid the gate oxide proportion of big thickness
The length of section is preferably less than the cellular length L of power semiconductor half half, by the threshold value electricity of power semiconductor
Voltage-controlled system is in the reasonable scope.
It is pointed out that in other embodiments of the invention, the quantity for the interval that gate oxide is included is also
Can be other fair amounts, meanwhile, the length of different intervals can also be unequal, and the invention is not restricted to this.
In order to more easily understand the characteristic of power semiconductor that the present embodiment provided, below to the present embodiment
The manufacturing process of the power semiconductor provided is described further.
Fig. 8 and Fig. 9 shows the flow chart that power semiconductor as shown in Figure 7 is manufactured in the present embodiment.
As shown in figure 8, in the present embodiment, layer of oxide layer is deposited on the substrate 201 first, the oxide layer
Thickness is preferably no more than 0.5 μm, and then the oxide layer formed is performed etching, enhanced so as to produce
The injection of carrier layer 204/doping window.After injection/doping window of enhanced carrier layer 204 is obtained,
Injection/doping of enhanced carrier layer is carried out into substrate 201 using the injection/doping window, is then carried out
High temperature propulsion/diffusion, so as to form a doping concentration enhanced carrier layer 204 higher than substrate 201.This
In embodiment, the doping concentration of enhanced carrier layer 204 is preferably more than 1e15/cm3。
, it is necessary to further be formed in enhanced carrier layer 204 after enhanced carrier layer 204 is obtained
P- basic units 205.As shown in figure 8, in the present embodiment, due to the injection using enhanced carrier layer 204/mix
During miscellaneous window forms enhanced carrier layer 204, high temperature propulsion technique causes the thickness of oxide layer 211
Add, the injection/doping window so made to form enhanced carrier layer 204 is covered oxidized layer
Lid, therefore now need first to perform etching the increased oxide layer of thickness, to form injection/doping of P- bases
Window.
After injection/doping window of P- bases is formed, you can using the window to enhanced carrier layer 204
Injection/doping of P- bases is carried out, then carries out high temperature propulsion/DIFFUSION TREATMENT, so as in enhanced carrier layer
P- bases 205 are formed in 204.In the present embodiment, the doping concentration of P- bases 205 is preferably e17/cm3
Magnitude.
It is pointed out that in other embodiments of the invention, according to being actually needed, enhanced carrier layer
The doping concentration of 204 and/or P- bases 205 can also be other reasonable values, and the invention is not restricted to this.
After P- bases 205 are formed, it is D to form a thickness on the substrate 2012SiO2Layer 211, and lead to
The method for crossing multiple photoetching and etching, produce stepped SiO as shown in Figure 82Table top, wherein, the SiO2
The thickness of the thinnest part of table top is D1.In the present embodiment, D2Value be preferably D1More than 10 times of value,
D1Value be preferably 0.1 μm.
Obtaining the SiO2After table top, in the SiO2The polysilicon layer of a specific thicknesses is formed on table top, is gone forward side by side
Row N-type polycrystalline silicon is adulterated.In the present embodiment, the thickness of polysilicon layer is preferably less than 0.5 μm, and its doping is dense
Degree is preferably in 1e19/cm3More than.Certainly, in other embodiments of the invention, it is more according to being actually needed
The thickness and doping concentration of crystal silicon layer can also be other reasonable values, and the invention is not restricted to this.
According to Fig. 9 as can be seen that after polysilicon layer is formed, by be covered in ohmic contact regions 207 and
Part SiO on source area 2062Layer and polysilicon layer carry out photoetching or etching, so as to the grid of final needs
Oxide layer 202 and polysilicon layer 203, meanwhile, pass through the photoetching or etching process, additionally it is possible to formed and be used for
Make injection/doping window of ohmic contact layer and source area.
After injection/doping window of ohmic contact layer and source area is obtained, in the present embodiment, successively in P- bases
Source area 206 and ohmic contact regions 207 are formed in area 205, due to source area 206 and ohmic contact regions
207 specific forming process is similar with the forming process of P- bases, therefore will not be repeated here.In the present embodiment,
The thickness of ohmic contact regions 207 is preferably more than the thickness of source area 206.
So far the positive technique of power semiconductor is just completed.After positive technique is completed, the present embodiment is provided
Method will carry out power semiconductor back process making.Specifically, as shown in figure 9, first with height
The mode of warm (being greater than 1000 DEG C) diffusion or ion implanting+low temperature (such as less than 500 DEG C) annealing is come
One or more N buffer layer structures are formed on another surface of substrate 201, so as to obtain cushion 208.This
In embodiment, cushion 208 includes first buffer layer 208a and second buffer layer 208b.Followed by high temperature
The mode of diffusion or ion implanting+laser annealing to form P+ collector areas 209 on the surface of cushion 208.Most
Afterwards, formed also with High temperature diffusion or the mode of ion implanting+laser annealing in P+ collector areas 209
Some N+ short dots 210.
It is pointed out that in different embodiments of the invention, for the thicker power semiconductor of thickness, its
The order of positive technique and back process (technical process for making cushion, collector area and short dot) can
To be adjusted, i.e., it both can first carry out back process and carry out positive technique again, and can also first carry out positive technique
Back process is carried out again.And for needing to carry out thinned power semiconductor again to enter, it is necessary to first carry out positive technique
Row back process, and can not overleaf have pyroprocess in technique.
In addition it is also necessary to, it is noted that in other embodiments of the invention, according to being actually needed, source area
206 and the manufacturing process of ohmic contact regions 207 can also be advanced to before manufacturing gate oxide layers, the present invention is not
It is limited to this.
It should be understood that disclosed embodiment of this invention is not limited to specific structure disclosed herein, processing
Step or material, and being equal for these features that those of ordinary skill in the related art are understood should be extended to and replaced
Generation.It is to be further understood that term as used herein is only used for describing the purpose of specific embodiment, and simultaneously unexpectedly
Taste limitation.
Special characteristic that " one embodiment " or " embodiment " mentioned in specification means to describe in conjunction with the embodiments,
During structure or characteristic are included at least one embodiment of the present invention.Therefore, specification various places throughout occurs
Phrase " one embodiment " or " embodiment " same embodiment might not be referred both to.
Although above-mentioned example is used to illustrate principle of the present invention in one or more apply, for this area
For technical staff, without departing substantially from the present invention principle and thought in the case of, hence it is evident that can in form, use
Various modifications may be made in method and the details of implementation and does not have to pay creative work.Therefore, the present invention is by appended power
Sharp claim limits.
Claims (13)
- A kind of 1. method for making power semiconductor, it is characterised in that methods described includes：Step 1: the gate oxide of preset thickness is formed over the substrate；Step 2: the gate oxide of the preset thickness is performed etching so that the gate oxide has a variety of Thickness, wherein, the trend gradually increased is presented from first end to the second end for the thickness of the gate oxide；Step 3: form polysilicon layer on gate oxide after etching.
- 2. the method as described in claim 1, it is characterised in that the most thick opening position of gate oxide after etching Thickness be more than 8 times of thickness of its most thin opening position.
- 3. method as claimed in claim 1 or 2, it is characterised in that in the step 2, by right The gate oxide of the preset thickness performs etching so that the thickness of the gate oxide is along first end to the second end Linear increase.
- 4. method as claimed in claim 1 or 2, it is characterised in that in the step 2, by right The gate oxide of the preset thickness carries out multiple etching, forms the multiple intervals being sequentially connected,Each odd number interval is flat bed section in the multiple interval, and each even number interval is oblique interval；Or,Each odd number interval is oblique interval in the multiple interval, and each even number interval is flat bed section；Wherein, the flat bed section keeps constant interval for the thickness of each opening position, and the tiltedly interval is thickness The interval linearly increased.
- 5. method as claimed in claim 1 or 2, it is characterised in that in the step 2, by right The gate oxide of the preset thickness carries out multiple etching, forms the multiple intervals being sequentially connected, the multiple layer Section forms step structure, wherein, the thickness of the interval more remote apart from the first end is bigger.
- 6. the method as described in claim 4 or 5, it is characterised in that in the multiple interval described in distance The length of the farthest interval of first end is less than the half of half cellular thickness of power semiconductor.
- 7. such as method according to any one of claims 1 to 6, it is characterised in that the polysilicon layer everybody The thickness for putting place is equal.
- 8. such as method according to any one of claims 1 to 7, it is characterised in that forming the default thickness Before the gate oxide of degree, methods described also forms first window over the substrate, and utilizes the first window The enhanced carrier layer with the first conduction type is formed in the substrate, in the enhanced carrier layer Middle formation P- bases.
- 9. such as method according to any one of claims 1 to 7, it is characterised in that forming the polysilicon After layer, methods described also forms the second window in the polysilicon layer and gate oxide, and utilizes described second Window forms the enhanced carrier layer with the first conduction type in the substrate, in the enhanced current-carrying P- bases are formed in sublayer.
- 10. method as claimed in claim 8 or 9, it is characterised in that after the P- bases are formed, Source area with the first conduction type is formed in the also described P- bases of methods described and with the second conduction type Ohmic contact regions, wherein, the ohmic contact regions are located at the centre position of the P- bases.
- 11. method as claimed in claim 10, it is characterised in that the thickness of the ohmic contact regions is more than The thickness of the source area.
- 12. the method as any one of claim 1~11, methods described also include：Cushion is formed on another surface of the substrate；Collector area is formed on the cushion.
- 13. method as claimed in claim 12, methods described also include：Short dot is formed on the collector area.
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| CN116230753A (en) * | 2023-04-21 | 2023-06-06 | 南京第三代半导体技术创新中心有限公司 | Gate thickening dielectric layer for silicon carbide field effect transistor and manufacturing method thereof |
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| US20090108347A1 (en) * | 2007-10-26 | 2009-04-30 | Adkisson James W | Lateral diffusion field effect transistor with asymmetric gate dielectric profile |
| CN102194861A (en) * | 2009-12-28 | 2011-09-21 | 富士电机控股株式会社 | Semiconductor device |
| US9166039B2 (en) * | 2011-12-06 | 2015-10-20 | Infineon Technologies Ag | Lateral transistor component and method for producing same |
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