CN205959988U - Take shielding electrode's power MOSFET cellular - Google Patents
Take shielding electrode's power MOSFET cellular Download PDFInfo
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- CN205959988U CN205959988U CN201621005083.4U CN201621005083U CN205959988U CN 205959988 U CN205959988 U CN 205959988U CN 201621005083 U CN201621005083 U CN 201621005083U CN 205959988 U CN205959988 U CN 205959988U
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- layer
- epitaxial layer
- power mosfet
- silicon oxide
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Abstract
Take shielding electrode's power MOSFET cellular. Relate to semiconductor device and make the field, especially relate to a power MOSFET cellular and processing technology. The utility model provides a simple process, with low costs, the control degree of difficulty is little, compares the take shielding electrode's power MOSFET cellular of the lower and stable performance of energy consumption with current MOSFET cellular structure. Be equipped with the regional and N type region of P type on the first interarea of epitaxial layer, the second interarea of epitaxial layer is equipped with the substrate, be equipped with the drain electrode metal level on the substrate, the first interarea of epitaxial layer is equipped with grid polycrystalline silicon layer, grid polycrystalline silicon layer with be equipped with gate oxide between the epitaxial layer, source electrode polycrystalline silicon with be equipped with oxygen ambient silica layer between the lateral wall of slot. The utility model provides rise anti excessive pressure of chip and the anti ability that overflows to promote the life of chip.
Description
Technical field
This utility model chip is related to field of manufacturing semiconductor devices, more particularly, to a kind of power MOSFET cellular.
Background technology
Currently, conventional power MOSFET（Mos field effect transistor）Manufacture method be to make
Grid polycrystalline silicon, source region (N-type region domain) and P-Body（P type island region domain）Directly carry out hole (contact) etching and front gold afterwards
Belong to and making, this process structure mainly is tied by P/N pressure, and this triangle electric field has conducting resistance and breakdown voltage
Contradictory problems, conducting resistance exponentially rises with breakdown voltage, and the conducting resistance of unit area is very high.
In order to obtain relatively low on-resistance per unit, occur in that different superjunction (CoolMOS) structure at present, comprise with
Company of Infineon is the multilayer epitaxial super-junction structure of representative, the deep trench super-junction structure with Toshiba as representative, multilayer epitaxial
To have multiple epitaxial growth and injection repeatedly, this easily affected by epitaxial growth quality and alignment precision, deep trench is logical
Cross formation deep trench on N-type extension and be subsequently filled p-type extension, because zanjon groove depth is very deep, filling quality is difficult to protect
Card, these structures can make epi region N-type and p-type electric charge reach balance, and triangle electric field is changed into trapezoidal electric field, fall
The conducting resistance of low unit area, but to be technique extremely complex for the shortcoming of these structures, process costs and control difficulty big, work
Skill concordance is excessively poor.
An application for a patent for invention disclosed in State Intellectual Property Office 2011-07-20（Application number：2010100273142,
Title：There is power MOS device construction of shield grid and preparation method thereof）Specifically disclose in groove type grid polysilicon bottom
Lower section has made lower floor's polysilicon gate, and this structural manufacturing process controls difficulty larger, and to two-layer grid between
The quality of oxide layer and be formed with higher requirement.
Utility model content
This utility model is directed to problem above, there is provided a kind of process is simple, low cost, control difficulty little, and existing
MOSFET structure cell is compared, and energy consumption is lower and the power MOSFET cellular with bucking electrode of stable performance.
The technical solution of the utility model is：With the power MOSFET cellular of bucking electrode, including epitaxial layer, described extension
First interarea of layer is provided with p type island region domain and N-type region domain, and the second interarea of described epitaxial layer is provided with substrate, described substrate sets
There is drain metal layer；
First interarea of described epitaxial layer is provided with gate polysilicon layer, between described gate polysilicon layer and described epitaxial layer
It is provided with grid oxic horizon；
The top of described gate polycrystalline body silicon layer covers source metal, described source metal and described grid polycrystalline silicon
It is sequentially provided with silicon oxide layer and insulating medium layer between layer；
The side of described epitaxial layer is provided with groove, filling source polysilicon, described source polysilicon upper table in described groove
Face is less than N polar region domain, higher than P pole sections bottom；
It is provided with silicon oxide layer between the side wall of described source polysilicon and described groove.
Described epitaxial layer is provided with gate trench, and in described gate trench, filling grid polycrystalline silicon forms grid polycrystalline silicon
Layer, is provided with grid oxic horizon between described gate polysilicon layer and described gate trench.
What described gate polysilicon layer projected sets on said epitaxial layer there, described gate polysilicon layer and described epitaxial layer it
Between be provided with grid oxic horizon.
Described gate polysilicon layer is concordant with above described epitaxial layer, described gate polysilicon layer and described epitaxial layer it
Between be provided with grid oxic horizon.
The silicon oxide layer thickness of the side wall of described groove is identical with the thickness of the silicon oxide layer of the bottom surface of described groove.
The thickness of the silicon oxide layer of the side of the inwall of described groove is less than the silicon oxide of the bottom surface of inwall of described groove
The thickness of layer.
In this utility model, the both sides in body are provided with groove, fill polysilicon, polysilicon and described groove in groove
It is provided with silicon oxide layer between outer wall.Make source region（The region of filling polysilicon in groove）Can be in the oxide layer side wall sensing of groove
Electric charge, the electric charge of balance external Yanzhong, reach charge balance so that peak value electric field internally moves from device surface, reduce unit
The conducting resistance of area and switch-charge.Make the lower power consumption of chip, reduce chip heating, the stability of lifting chip.Ditch
The thickness of the silicon oxide layer of groove inwall side can be less than the thickness of the silicon oxide layer of described trench bottom surfaces.Make chip be difficult by
Puncture, the ability of the lifting anti-over-pressed and anti-excessively stream of chip, thus lift the service life of chip.Silica layer growth according to demand
（Deposit）Time, obtain different-thickness silicon oxide layer, thus obtaining different electrical properties, applied widely.Add whole
Only need this single parameter of control time during work, control difficulty little.
Brief description
Fig. 1 is the top view of the chip array of wafer in this utility model,
Fig. 2 is this utility model chip structure top view,
Fig. 3 is that another kind of arrangement mode of the power MOSFET cellular with bucking electrode in this utility model chips is overlooked
Figure,
Fig. 4 is that the third arrangement mode of the power MOSFET cellular with bucking electrode in this utility model chips is overlooked
Figure,
Fig. 5 is A-A sectional view in Fig. 2,
Fig. 6 is a kind of structural representation of the power MOSFET cellular with bucking electrode in this utility model,
Fig. 7 is another kind of structural representation of the power MOSFET cellular with bucking electrode in this utility model,
Fig. 8 is the third structural representation of the power MOSFET cellular with bucking electrode in this utility model,
Fig. 9 is the 4th kind of structural representation of the power MOSFET cellular with bucking electrode in this utility model,
Figure 10 is the epitaxial layer substrate of the power MOSFET cellular with bucking electrode and epitaxial layer structure in this utility model
Sectional view,
Figure 11 is that the first interarea of the power MOSFET cellular with bucking electrode in this utility model makes grid grid oxygen
Change the structure sectional view of layer and gate-source polysilicon,
Figure 12 is the manufacture p type island region domain of the power MOSFET cellular with bucking electrode and N-type region domain in this utility model
Structure sectional view,
Figure 13 is that the structure of the making insulating medium layer of the power MOSFET cellular with bucking electrode in this utility model is cutd open
View,
Figure 14 is that the insulating medium layer selective etch of the power MOSFET cellular with bucking electrode in this utility model is complete
Stop structure sectional view after window,
Figure 15 is the structure sectional view after the etching groove with the power MOSFET cellular of bucking electrode in this utility model,
Figure 16 is the knot forming silicon oxide layer in the groove of the power MOSFET cellular with bucking electrode in this utility model
Structure sectional view,
Figure 17 is the filling source polysilicon in groove of the power MOSFET cellular with bucking electrode in this utility model
And return carved structure sectional view,
Figure 18 is having etched after unnecessary silicon oxide layer of the power MOSFET cellular with bucking electrode in this utility model
Structure sectional view,
Figure 19 is the covering source metal of the power MOSFET cellular with bucking electrode and drain electrode gold in this utility model
Belong to the structure sectional view after layer,
Figure 20 is the using effect figure of the power MOSFET cellular with bucking electrode in this utility model.
In figure 1 is wafer, and 2 is chip, 20, it is terminal pressure ring, 21 is cellular array, and 211 is epitaxial layer, and 2111 is ditch
Groove, 2112 is silicon oxide layer, and 2113 is source polysilicon, and 212 is gate polysilicon layer, and 213 is grid oxic horizon, and 214 is N
Type region, 215 is p type island region domain, and 216 is insulating medium layer, and 217 is source metal, and 218 is substrate, and 219 is drain metal
Layer.
Specific embodiment
This utility model as shown in Fig. 1-2 0, a kind of power MOSFET cellular with bucking electrode, including epitaxial layer 211,
First interarea of described epitaxial layer 211 is provided with p type island region domain 215 and N-type region domain 214, and the second interarea of described epitaxial layer 211 sets
There is substrate 218, described substrate 218 is provided with drain metal layer 219；First interarea of described epitaxial layer 211 is provided with gate polycrystalline
Silicon layer 212, is provided with grid oxic horizon 213 between described gate polysilicon layer 212 and described epitaxial layer 211；Described gate polycrystalline
The top of body silicon layer 212 covers source metal 217, between described source metal 217 and described gate polysilicon layer 212 according to
Secondary it is provided with silicon oxide layer 2112 and insulating medium layer 216；The side of described epitaxial layer 211 is provided with groove 2111, described groove
Filling source polysilicon in 2111, described source polysilicon upper surface is less than N polar region domain 214, higher than P pole sections bottom 215；Institute
State and between source polysilicon and the side wall of described groove 2111, be provided with silicon oxide layer 2112.Cleverly shielded gate structure is placed on
Below contact hole, reduce technique manufacture difficulty, corresponding manufacturing cost reduces.
Filling source polysilicon in described groove 2111 is so that source region（The region of filling source polysilicon in groove）Meeting exists
On the side wall of groove 2111 and silicon oxide layer 212 formed charge inducing, the electric charge of balance external Yanzhong, reach charge balance so that
Peak value electric field internally moves from device surface, reduces conducting resistance and the switch-charge of unit area.Make the power consumption of chip
Reduce, reduce chip heating, the stability of lifting chip.
Described epitaxial layer 211 is provided with gate trench, and in described gate trench, filling grid polycrystalline silicon forms gate polycrystalline
Silicon layer 212, is provided with grid oxic horizon 213 between described gate polysilicon layer 212 and described gate trench.As shown in fig. 6, being cellular
A kind of structural representation so that grid is concordant with the upper surface of epitaxial layer 211, be easy to process.As shown in fig. 7, described grid
What polysilicon layer 212 projected sets on said epitaxial layer there, is provided between described gate polysilicon layer 212 and described epitaxial layer 211
Grid oxic horizon 213.The chip that can be constituted according to the cellular that different application scenarios selects different structure, applied widely.
The thickness of the silicon oxide layer 2112 of the inwall of described groove 2111 is equal to the oxygen of the inwall bottom surface of described groove 2111
The thickness of SiClx layer 2112.So ensure that cellular is obtained in that uniform electrical property.However, it is possible to according to different uses
Occasion, the thickness of the silicon oxide layer 2112 of the inwall of described groove 2111 is less than the silicon oxide of the inwall bottom surface of described groove 2111
The thickness of layer 2112.Chip is difficult breakdown, the ability of the lifting anti-over-pressed and anti-excessively stream of chip, thus lift making of chip
Use the life-span.The time of growth selection silicon oxide layer according to demand, then pass through back carving technology, so that the inwall of groove 2111
The thickness of silicon oxide layer 2112 is less than the thickness of the silicon oxide layer 2112 of inwall bottom surface of described groove 2111, thus obtaining difference
Electrical property, make the applied widely of chip, lifting chip service life and stability.
A kind of chip comprising the power MOSFET cellular with bucking electrode, the described unit of the planar MOSFET with bucking electrode
Born of the same parents are square, rectangle, regular hexagon or circle are uniformly laid on the chip.Described planar MOSFET cellular is rectangular
When, single planar MOSFET cellular is distributed on chip in the strip suitable with Chip-wide or length, or equal in storiform
Even it is arranged on chip.Different arrangement forms can be adopted according to the different demands of user, obtain different electrical properties.
As shown in Figure 10-19, it is the processing technique substep structural representation of the power MOSFET cellular with bucking electrode, is
It is easy to skilled artisan understands that and being easy to describe, using two power MOSFET cellulars with bucking electrode side by side chatting
State processing technique, process as follows：
1）Make gate polysilicon layer and grid oxic horizon in the first interarea of epitaxial layer；
1.1）Body is put into boiler tube internal oxidition and forms oxide layer；
1.2）In oxide layer, depositing polysilicon forms grid layer；
1.3）Carry out selective etch using dry etching, remove unnecessary oxide layer and polysilicon；
2）Inject and adopt furnace anneal to form p type island region domain and N-type region domain；
3）Deposit insulating medium layer；
3.1）Grid layer deposits dielectric, forms insulating medium layer；
3.2）Carry out selective etch using dry etching, remove unnecessary dielectric；
A, make groove structure, using being dry-etched in etching groove on epitaxial layer；Gash depth at 8-35 μm, less than etc.
Thickness in epitaxial layer.
B, on the inwall of groove silicon oxide deposition layer, by body pass through gaseous chemical formation of deposits silicon oxide layer；
C, filling polysilicon；
D, carry out back carving using dry etching, remove unnecessary polysilicon；The upper surface of polysilicon is less than under N-type region domain
Edge, less than the upper edge in p type island region domain；
E, remove unnecessary silicon oxide layer using dry etching；Need to remove the oxide layer on trench wall polysilicon top,
Ensure that front metal and N-type and p type island region domain form Ohmic contact, thus forming intact electrical property it is ensured that chip stability.
Filling source polysilicon in described groove 2111 is so that source region（The region of filling source polysilicon in groove）Meeting exists
On the side wall of groove 2111 and silicon oxide layer 212 formed charge inducing, the electric charge of balance external Yanzhong, reach charge balance so that
Peak value electric field internally moves from device surface, reduces conducting resistance and the switch-charge of unit area.Make the power consumption of chip
Reduce, reduce chip heating, the stability of lifting chip.
4）Source metal is covered above insulating medium layer；
5）Cover drain metal layer in substrate second interarea, form complete structure cell, finish.
Claims (6)
1. the power MOSFET cellular with bucking electrode, including epitaxial layer, the first interarea of described epitaxial layer is provided with p type island region domain
With N-type region domain, the second interarea of described epitaxial layer is provided with substrate, and described substrate is provided with drain metal layer；It is characterized in that,
First interarea of described epitaxial layer is provided with gate polysilicon layer, is provided between described gate polysilicon layer and described epitaxial layer
Grid oxic horizon；
The top of described gate polycrystalline body silicon layer covers source metal, described source metal and described gate polysilicon layer it
Between be sequentially provided with silicon oxide layer and insulating medium layer；
The side of described epitaxial layer is provided with groove, filling source polysilicon in described groove, and described source polysilicon upper surface is low
In N polar region domain, higher than P pole sections bottom；
It is provided with silicon oxide layer between the side wall of described source polysilicon and described groove.
2. the power MOSFET cellular with bucking electrode according to claim 1 is it is characterised in that set on described epitaxial layer
There is gate trench, in described gate trench, filling grid polycrystalline silicon forms gate polysilicon layer, described gate polysilicon layer and institute
State and between gate trench, be provided with grid oxic horizon.
3. the power MOSFET cellular with bucking electrode according to claim 2 is it is characterised in that described grid polycrystalline silicon
What layer was prominent sets on said epitaxial layer there, is provided with grid oxic horizon between described gate polysilicon layer and described epitaxial layer.
4. the power MOSFET cellular with bucking electrode according to claim 2 is it is characterised in that described grid polycrystalline silicon
Layer is concordant with above described epitaxial layer, is provided with grid oxic horizon between described gate polysilicon layer and described epitaxial layer.
5. the power MOSFET cellular with bucking electrode according to claim 3 or 4 is it is characterised in that described groove
The silicon oxide layer thickness of side wall is identical with the thickness of the silicon oxide layer of the bottom surface of described groove.
6. the power MOSFET cellular with bucking electrode according to claim 3 or 4 is it is characterised in that described groove
The thickness of the silicon oxide layer of the side of inwall is less than the thickness of the silicon oxide layer of the bottom surface of inwall of described groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621005083.4U CN205959988U (en) | 2016-08-30 | 2016-08-30 | Take shielding electrode's power MOSFET cellular |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621005083.4U CN205959988U (en) | 2016-08-30 | 2016-08-30 | Take shielding electrode's power MOSFET cellular |
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| CN205959988U true CN205959988U (en) | 2017-02-15 |
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| CN201621005083.4U Expired - Fee Related CN205959988U (en) | 2016-08-30 | 2016-08-30 | Take shielding electrode's power MOSFET cellular |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158975A (en) * | 2016-08-30 | 2016-11-23 | 扬州扬杰电子科技股份有限公司 | The power MOSFET cellular of a kind of band bucking electrode and processing technique thereof |
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2016
- 2016-08-30 CN CN201621005083.4U patent/CN205959988U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158975A (en) * | 2016-08-30 | 2016-11-23 | 扬州扬杰电子科技股份有限公司 | The power MOSFET cellular of a kind of band bucking electrode and processing technique thereof |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170215 Termination date: 20170830 |