CN102347232B - Dry etching method of silicon - Google Patents
Dry etching method of silicon Download PDFInfo
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- CN102347232B CN102347232B CN201110300744.1A CN201110300744A CN102347232B CN 102347232 B CN102347232 B CN 102347232B CN 201110300744 A CN201110300744 A CN 201110300744A CN 102347232 B CN102347232 B CN 102347232B
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Abstract
The invention provides a dry etching method of silicon. The method comprises the following steps of: carrying out dry etching after a step of removing a natural oxide layer and before a step of etching silicon so as to remove polymers, wherein etching gases used for carrying out dry etching comprise Cl2 and O2, the flow rate of the Cl2 is in the range of 60sccm-150sccm, and the flow rate of the O2 is in the range of 5sccm-20sccm. By using the dry etching method, a surface of an etching stop layer on the lower surface of the silicon is flat and smooth.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to a kind of dry etching method of silicon.
Background technology
With the appearance of polysilicon gate (Poly Gate) metal-oxide semiconductor (MOS) (MOS) device, polysilicon becomes gradually
The main force of advanced device material.In addition to as mos gate pole, polysilicon is also widely used for dynamic RAM
Bit line in the deep groove capacity pole plate filling of (Dynamic Random Access Memory, DRAM), flash technology and word
Line etc..The realization of these techniques all be unable to do without the dry etching technology of silicon.The dry etching technology of described silicon also includes shallow trench
Etching of the monocrystalline silicon etching of isolation and metal silicide etc..
More technology with regard to etching polysilicon, refer to the China of Publication No. CN1851049A and CN101436536A
Patent application.
Below taking etch and form polysilicon gate as a example, the dry etching technology of silicon in prior art is described.
When polysilicon layer exposes in atmosphere, one layer of natural oxidizing layer will be formed on the surface of polysilicon layer, natural
The main component of oxide layer is silicon dioxide, so before etches polycrystalline silicon, needing first to remove the natural oxidizing layer on its surface.
The etching polysilicon of prior art can be divided into two stages, with reference to shown in Fig. 1, including：
Step S1, carries out first step dry etching, removes the natural oxidizing layer on described polysilicon layer surface, the described first step
The etching gas of dry etching include CF4And CHF3；
Step S2, carries out second step dry etching, with the gate oxide below polysilicon layer as etching stop layer, removal portion
Divide described polysilicon layer, form polysilicon gate, the etching gas of described second step dry etching include HBr and HeO2, described grid
The material of oxide layer is silicon dioxide.
But find after above-mentioned etch step, the surface roughness of gate oxide, out-of-flatness, or even also can present
Zigzag.
Similarly, during other dry etchings of silicon, during such as monocrystal silicon being performed etching, position also occurs
Rough surface, irregular phenomenon in the etching stop layer of monocrystal silicon lower surface.
Above-mentioned out-of-flatness may affect follow-up semiconductor technology quality.
Therefore, how during the dry etching of silicon it is ensured that being located at the surfacing of the etching stop layer of silicon lower surface
Smooth just become those skilled in the art's problem demanding prompt solution.
Content of the invention
The problem that the present invention solves is to provide a kind of dry etching method of silicon, so that being located at silicon following table after etching silicon
The surfacing of the etching stop layer in face is smooth.
For solving the above problems, the invention provides a kind of dry etching method of silicon, after removing removing natural oxidizing layer,
And before etching silicon, carry out dry etching.
Alternatively, the described etching gas carrying out dry etching include Cl2(chlorine) and O2(oxygen).
Alternatively, described Cl2Flow rate scope include 60sccm (standard-state cubic
Centimeter per minute, marks every point of condition milliliter)～150sccm；Described O2Flow rate scope include 5sccm～
20sccm.
Alternatively, the etching air pressure range of described dry etching includes 4 millitorr～15 millitorrs；The scope bag of source radio-frequency power
Include 200W (watt)～500W；The scope of biasing radio-frequency power includes 100W～300W.
Alternatively, the time range of described dry etching includes 5s (second)～10s.
Alternatively, described go removing natural oxidizing layer to adopt dry etching, etching gas include CF4(carbon tetrafluoride) and CHF3
(fluoroform).
Alternatively, the etching gas of the described dry etching removing removing natural oxidizing layer also include O2.
Alternatively, described CF4Flow rate scope include 15sccm～25sccm；CHF3Flow rate scope include
35sccm～45sccm；O2Flow rate scope include 45sccm～55sccm.
Alternatively, described silicon includes polysilicon；Described etching silicon adopts dry etching, and etching gas include HBr (bromination
Hydrogen) and HeO2(peroxidating helium).
Alternatively, the flow rate scope of described HBr includes 80sccm～150sccm；Described HeO2Flow rate model
Enclose including 5sccm～15sccm.
Alternatively, the etching air pressure range of the dry etching of described etching silicon includes 45 millitorr～80 millitorrs；Source radio frequency work(
The scope of rate includes 100W～300W；The scope of biasing radio-frequency power includes 50W～200W.
Alternatively, the time range of the dry etching of described etching silicon includes 25s～45s.
Alternatively, described silicon includes monocrystal silicon or polysilicon.
Compared with prior art, the present invention has advantages below：
1) after removing removing natural oxidizing layer, and before etching silicon, carry out dry etching, to remove polymer, thus
Ensure that the surfacing of the etching stop layer being located at silicon lower surface after etching silicon is smooth.
2), in alternative, the described etching gas carrying out dry etching include Cl2And O2, wherein：Cl2Polymer is sent out
Raw physical bombardment effect, O2There is chemical reaction with the carbon containing thing in polymer, such that it is able to the light polymerization removing silicon face
Thing it is ensured that etching silicon before silicon surface very clean.
3), in alternative, the etching gas of etching natural oxidizing layer can include O2, by being passed through appropriate oxygen, can
To reduce the generation of polymer in course of reaction.
Brief description
Fig. 1 is the schematic flow sheet of the dry etching method of prior art silicon；
Fig. 2 is the schematic flow sheet of the dry etching method of silicon in embodiment of the present invention；
Fig. 3 is the semiconductor structure schematic diagram before embodiment of the present invention etching；
Fig. 4 is the structural representation that the embodiment of the present invention carries out before first step dry etching；
Fig. 5 is the structural representation that the embodiment of the present invention carries out before second step dry etching；
Fig. 6 is the structural representation that the embodiment of the present invention carries out after second step dry etching；
Fig. 7 is the structural representation that the embodiment of the present invention carries out after the 3rd step dry etching.
Specific embodiment
Understandable for enabling the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Elaborate a lot of details in the following description in order to fully understand the present invention, but the present invention is acceptable
To be implemented different from alternate manner described here using other, therefore the present invention is not limited by following public specific embodiment
System.
Just as described in the background section, prior art is after using two step dry etching method etches polycrystalline silicon layers, many
The surface roughness of the gate oxide below crystal silicon layer, out-of-flatness, or even also can assume zigzag.Study through inventor and find：
Adopting CF4And CHF3During carrying out first step dry etching, the etching gas of first step dry etching are removing nature oxygen
While changing layer, this etching gas also can be higher because of the ratio (i.e. C/F) of carbon atom and fluorion, thus in polysilicon layer table
Face generates much block polymer (polymer), and described polymer includes carbon containing thing etc..Similarly, when using other etchings
When gas removes removing natural oxidizing layer, described etching gas also can be reacted with polysilicon layer, thus in the life of polysilicon layer surface
Become polymer.This polymer is equivalent to and forms micro- mask (Micro-mask) on the surface of polysilicon layer, and this micro- mask hinders
The normal etching of polysilicon layer below.The table of etching stop layer after therefore carrying out second step dry etching, will be led to
Face is very coarse, or even assumes zigzag.
In order to overcome the problems referred to above, the invention provides a kind of dry etching method of silicon, go removing natural oxidizing layer it
Afterwards, and before etching silicon, increased a step dry etching, to remove the polymer of extra generation, thus when etching silicon, silicon
Surface cleaner, the surface of the etching stop layer positioned at silicon lower surface obtaining after final etching silicon is very smooth and smooth,
And be more not in zigzag.
It is described in detail below in conjunction with the accompanying drawings.
With reference to shown in Fig. 2, the dry etching method of the silicon that present embodiment provides includes：
Step S11, carries out first step dry etching, removes removing natural oxidizing layer；
Step S12, carries out second step dry etching, removes polymer；
Step S13, carries out the 3rd step dry etching, removes unnecessary silicon.
Hereinafter still taking form polysilicon gate as a example illustrated by etches polycrystalline silicon layer, but it should not limit the guarantor of the present invention
Shield scope.
First, provide the semiconductor structure before etching, described semiconductor structure includes from top to bottom successively：Semiconductor substrate
100th, gate oxide 200 and polysilicon layer 300.
With reference to shown in Fig. 3, in order to realize the etching to partly described polysilicon layer 300, on described polysilicon layer 300 according to
Secondary formation hard mask layer 400 and photoresist layer 500.
Wherein, described Semiconductor substrate 100 can be the silicon substrate including fleet plough groove isolation structure (STI) 110, described grid
The material of oxide layer 200 can be silicon dioxide, and the material of described hard mask layer 400 can be silicon oxynitride, and its here is only
Citing, should not limit the scope of the invention.
With reference to shown in Fig. 4, before etches polycrystalline silicon layer 300, need first with the photoresist layer 500 after exposure imaging for covering
Mould, remove part hard mask layer 400, then remaining photoresist layer 500 is removed, then using remaining hard mask layer 400 as
Mask, performs etching to partial polysilicon layer 300.The technology of removal photoresist layer 500 and hard mask layer 400 and prior art phase
Same, will not be described here.
There is one layer of natural oxidizing layer 600 because polysilicon layer 300 exposes aerial surface, therefore in etches polycrystalline
Before silicon layer 300, need first to remove described natural oxidizing layer 600.
The present embodiment removes described natural oxidizing layer 600 and adopts first step dry etching, described first step dry etching
Etching gas can include CF4、CHF3And O2, wherein：CF4Flow rate scope can include 15sccm～25sccm, such as：
15sccm, 18sccm, 22sccm or 25sccm；CHF3Flow rate scope can include 35sccm～45sccm, such as：
35sccm, 39sccm, 41sccm or 45sccm；O2Flow rate scope can include 45sccm～55sccm, such as：
45sccm, 47sccm, 53sccm or 55sccm；The etching air pressure range of described first step dry etching can include 5 millitorrs～
15 millitorrs, such as：5 millitorrs, 7 millitorrs, 10 millitorrs or 15 millitorrs；The scope of source radio-frequency power can include 400W～600W, such as：
400W, 450W, 550W or 600W；The scope of biasing radio-frequency power can include 50W～300W, such as：50W, 150W, 200W or
300W；The time range of described first step dry etching can include 10s～35s, such as：10s, 15s, 25s or 35s.Need
Bright, can also be made a return journey removing natural oxidizing layer 600 from other etching gas in other embodiments of the invention, such as：Can
Only to select CF4And CHF3, and do not include O2.
This step passes through CF4Or CHF3React with natural oxidizing layer 600, thus generate volatile gas (including：
SiF4, CO or CO2), to remove removing natural oxidizing layer 600.Wherein, the present embodiment is when carrying out first step dry etching, by being passed through
Appropriate oxygen, can reduce the generation of polymer in course of reaction.
Then, carry out second step dry etching, to remove polymer 700.
With reference to shown in Fig. 5, during removing removing natural oxidizing layer 600, due to etching gas CF4And CHF3In polysilicon
The surface of layer 300 easily generates much block polymer 700.Therefore, embodiment adds removing the step of polymer 700
When suddenly, to ensure etches polycrystalline silicon layer 300, described polysilicon layer 300 relatively clean, the surface of the gate oxide 200 after etching
Relatively flat smooth.
The present embodiment removes described polymer and adopts second step dry etching, the etching gas of described second step dry etching
Cl can be included2And O2, wherein：Cl2Flow rate scope include 60sccm～150sccm, such as：60sccm、88sccm、
100sccm or 150sccm；O2Flow rate scope include 5sccm～20sccm, such as：5sccm, 7sccm, 15sccm or
20sccm；The etching air pressure range of described second step dry etching can include 4 millitorr～15 millitorrs, such as：4 millitorrs, 5 millitorrs,
10 millitorrs or 15 millitorrs；The scope of source radio-frequency power can include 200W～500W, such as：200W, 250W, 350W or 500W；Partially
The scope putting radio-frequency power can include 100W～300W, such as：100W, 150W, 200W or 300W；Described second step dry etching
Time range can include 5s～10s, such as：5s, 7s, 8s or 10s.
The gas Cl of isotropic etching is selected in this step2And O2, isotropic etching is carried out to polymer 700, and
While removing polymer 700, also can remove remaining a small amount of natural oxidizing layer 600, thus ensure that polysilicon layer 300 table
The cleaning in face.Described etching gas Cl2Etching to polysilicon layer 300 and gate oxide 200 (the present embodiment is silicon dioxide)
Select than it is ensured that on STI 110 loss of corresponding silicon dioxide less.Meanwhile, Cl2Physics is occurred to bang in polymer 700
Hit effect, O2There is chemical reaction with the carbon containing thing in polymer 700, such that it is able to light removal polysilicon layer 300 surface
Polymer 700, specifically refer to shown in Fig. 6.
This step passes through Cl2/O2Physical-chemical reaction and polymer 700 between, thus generate volatile gas (bag
Include CO or CO2), to remove polymer 700.
Then, with reference to shown in Fig. 7, carry out the 3rd step dry etching, remove unnecessary polysilicon layer 300.
The present embodiment removes polysilicon layer 300 and adopts the 3rd step dry etching, with gate oxide 200 as etching stop layer,
The etching gas of described 3rd step dry etching can include HBr and HeO2, wherein：The flow rate scope of HBr includes
80sccm～150sccm, such as：80sccm, 100sccm, 120sccm or 150sccm；HeO2Flow rate scope include
5sccm～15sccm, such as：5sccm, 7sccm, 10sccm or 15sccm；The etching air pressure range of described 3rd step dry etching
45 millitorr～80 millitorrs can be included, such as：45 millitorrs, 50 millitorrs, 65 millitorrs or 80 millitorrs；The scope of source radio-frequency power can be wrapped
Include 100W～300W, such as：100W, 150W, 250W or 300W；The scope of biasing radio-frequency power can include 50W～150W, such as：
50W, 75W, 125W or 150W；The time range of described 3rd step dry etching can include 25s～45s, such as：25s、35s、
40s or 45s.
It should be noted that in other embodiments of the present invention, the etching gas in the 3rd step dry etching and each parameter
Scope can change, and specifically can determine, it is for this area by factors such as the thickness of polysilicon layer 300 to be removed
Known to technical staff is, therefore here should not limit the scope of the invention.
This step passes through HBr/HeO2React with polysilicon layer 300, generate SiBr4Or BrxOyDeng unnecessary to remove
Polysilicon layer 300, wherein x and y is the ratio of the number of Br atom and O atom.
Finally can remove remaining hard mask layer 400, and carry out the etching of gate oxide 200, to ultimately form grid
Structure, it is same as the prior art, therefore will not be described here.
It should be noted that above-described embodiment is taking the etching of polysilicon gate as a example to illustrate, the present invention other
In embodiment, can also realize to the etching of polysilicon or the etching to monocrystal silicon in the case of other using the inventive method,
It should not limit the scope of the invention.
Although the present invention is own being disclosed as above with preferred embodiment, the present invention is not limited to this.Any art technology
Personnel, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should
When being defined by claim limited range.
Claims (8)
1. a kind of dry etching method of silicon it is characterised in that
After removing removing natural oxidizing layer, and before etching silicon, carry out dry etching, etching gas include Cl2And O2；
Described go removing natural oxidizing layer to adopt dry etching, etching gas include CF4、CHF3And O2；
Described silicon includes monocrystal silicon or polysilicon；Described etching silicon adopts dry etching, and etching gas include HBr and HeO2.
2. the dry etching method of silicon as claimed in claim 1 is it is characterised in that described Cl2Flow rate scope include
60sccm～150sccm；Described O2Flow rate scope include 5sccm～20sccm.
3. the dry etching method of silicon as claimed in claim 1 is it is characterised in that the etching air pressure range of described dry etching
Including 4 millitorr～15 millitorrs；The scope of source radio-frequency power includes 200W～500W；Biasing radio-frequency power scope include 100W～
300W.
4. the dry etching method of silicon as claimed in claim 1 is it is characterised in that the time range of described dry etching includes
5s～10s.
5. the dry etching method of silicon as claimed in claim 1 is it is characterised in that described CF4Flow rate scope include
15sccm～25sccm；CHF3Flow rate scope include 35sccm～45sccm；O2Flow rate scope include 45sccm
～55sccm.
6. the dry etching method of silicon as claimed in claim 1 is it is characterised in that the flow rate scope of described HBr includes
80sccm～150sccm；Described HeO2Flow rate scope include 5sccm～15sccm.
7. the dry etching method of silicon as claimed in claim 1 is it is characterised in that the etching of the dry etching of described etching silicon
Air pressure range includes 45 millitorr～80 millitorrs；The scope of source radio-frequency power includes 100W～300W；The scope of biasing radio-frequency power
Including 50W～200W.
8. the dry etching method of silicon as claimed in claim 1 is it is characterised in that the time of the dry etching of described etching silicon
Scope includes 25s～45s.
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| CN201110300744.1A CN102347232B (en) | 2011-09-28 | 2011-09-28 | Dry etching method of silicon |
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| CN104882375B (en) * | 2014-02-28 | 2018-05-25 | 无锡华润上华科技有限公司 | The semiconductor devices engraving method and method for forming semiconductor devices of a kind of anti-defect |
| CN110911280A (en) * | 2019-12-05 | 2020-03-24 | 上海华虹宏力半导体制造有限公司 | Method for forming metal silicide |
| US11915933B2 (en) | 2020-09-18 | 2024-02-27 | Changxin Memory Technologies, Inc. | Manufacturing method of semiconductor structure |
| CN114203545A (en) * | 2020-09-18 | 2022-03-18 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1198588A (en) * | 1997-03-31 | 1998-11-11 | 日本电气株式会社 | Etching method for device layer in semiconductor |
| CN101777485A (en) * | 2009-01-12 | 2010-07-14 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11330045A (en) * | 1998-05-08 | 1999-11-30 | Nec Corp | Method for etching laminated film of oxide film and silicon layer |
| CN1851049A (en) * | 2005-12-02 | 2006-10-25 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Polycrystalline silicon etching method for improving line roughness |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1198588A (en) * | 1997-03-31 | 1998-11-11 | 日本电气株式会社 | Etching method for device layer in semiconductor |
| CN101777485A (en) * | 2009-01-12 | 2010-07-14 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method |
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