CN1851049A - Polycrystalline silicon etching method for improving line roughness - Google Patents

Polycrystalline silicon etching method for improving line roughness Download PDF

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Publication number
CN1851049A
CN1851049A CN 200510126289 CN200510126289A CN1851049A CN 1851049 A CN1851049 A CN 1851049A CN 200510126289 CN200510126289 CN 200510126289 CN 200510126289 A CN200510126289 A CN 200510126289A CN 1851049 A CN1851049 A CN 1851049A
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China
Prior art keywords
etching
flow
eroding
electrode power
chiseling
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CN 200510126289
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Chinese (zh)
Inventor
孙静
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Beijing North Microelectronics Co Ltd
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Beijing North Microelectronics Co Ltd
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Priority to CN 200510126289 priority Critical patent/CN1851049A/en
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Abstract

The invention relates to the chiseling and the eroding method of the several crystal silicon bar, the process is showed below: (1) the chiseling and eroding process before the beginning chisel; (2) the beginning chisel; (3) the main chisel: (4) the exceeding chisel. The chiseling and eroding process of the beginning chisel acts before the multicrystal chiseling and the eroding and after the hard hiding film chiseling and eroding, the SF3 or NF3 is served as the reactive gas, or the one sort or the several sorts of CxHyFz, Cl2, O2, are choose. The eroding method can wipe off the polymer remain of the light glue on the surface of the silicon, the effect of the roughness degree is reduced.

Description

A kind of polycrystalline silicon etching method that improves line roughness
Technical field
The present invention relates to a kind of polycrystalline silicon etching method, more particularly, the present invention relates to a kind of polycrystalline silicon etching method that can improve the roughness of lines.
Background technology
Etching polysilicon is the common technology in the semiconductor fabrication.Along with the integrated level raising of unicircuit, the lines of etching are more and more thinner, and the live width size was dwindled half in average per 6 years, and the development of lithographic technique can not adapt with it, and this causes lines more and more coarse.In deep-submicron device production technology, line roughness becomes day by day influences the stumbling-block that yield improves.
Below, be example with polysilicon grating structure shown in Fig. 1, polycrystalline silicon etching method in the prior art is described, wherein Reference numeral 1 is a silicon layer, the 2nd, silicon dioxide layer, the 3rd, polysilicon layer, the 4th, hard mask, the 5th, optical cement.Described silicon gate structure is taked the lithographic method of usefulness, and as shown in the table comprising the steps: (1) just carved; (2) the main quarter; (3) spend quarter.The processing parameter of above-mentioned steps is as follows:
Upper electrode power (W) Lower electrode power (W) Pressure (mTorr) CxHyFz flow (sccm) Cl 2Flow (sccm) HBr flow (sccm) He flow (sccm) HeO 2Flow (sccm) Time (s)
Just carve 250-400 20-80 7-15 20-100 0-100 2-60
The main quarter 300-450 20-80 7-20 0-100 100-300 0-50 2-90
Spend quarter 200-350 40-120 40-80 100-400 0-200 0-50 2-180
Wherein, C xH yF z: x=1; Y=0,1; Z=2x+2-y; Or x=2; Y=0; Z=2x+2; Or x=4; Y=0,1; Z=2x-y.
The lines that obtain with the aforesaid method etching as shown in Figure 2, as can be seen from the figure, lines are coarse, rectilinearity is poor.The organic polymer that causes coarse reason of lines and photoresist material to produce in etching process is residual much relations.This is because in etching process, optical cement and reactant gases generation chemical reaction, resultant is not taken away fully, the irregular silicon chip surface that remains in of partial polymer, become little mask of next step lines etching, thereby caused the nonlinearity of lines etching structures.
Summary of the invention
(1) technical problem that will solve
Purpose of the present invention aims to provide a kind of can the solution in the etching process because the etching polysilicon novel process of the line roughness problem that the optical cement residue produces.
(2) technical scheme
For achieving the above object, the present inventor provides a kind of new gate etching process, and the concrete technology of this step is:
(1) just carves preceding etching;
(2) just carve;
(3) the main quarter;
(4) spend quarter.
Wherein used process gas is SF in the step (1) 6Or NF 3, preferred SF 6, it is further characterized in that described process gas also comprises and is selected from C xH yF z, Cl 2And O 2In one or more gases, at C xH yF zIn, x=1; Y=0,1; Z=2x+2-y; Or x=2; Y=0; Z=2x+2; Or x=4; Y=0,1; Z=2x-y, preferred CF 4
Lithographic method of the present invention after it is further characterized in that hard mask etching, carries out the etching of step (1) before the etching polysilicon, in step (1), and SF 6Or NF 3Flow be 5-200sccm; When using mixed gas, the overall process gas flow is 5-1000sccm, wherein SF 6Or NF 3Flow be 5-200sccm, the flowrate proportioning of other gases does not have particular determination; Upper electrode power is 50-500w, and lower electrode power is 0-100w, and pressure is 0-100mTorr.The time that this step is carried out is 2-100s.
The condition of existing technology is adopted in step in the lithographic method of the present invention (2)-(4), is promptly just carving in the step C in the reactant gases xH yF zFlow be 20-100sccm, Cl 2Flow be 0-100sccm, upper electrode power is 250-400w, lower electrode power is 20-80w, pressure is 7-15mTorr, described C xH yF zIn the gas, x=1; Y=0,1; Z=2x+2-y; Or x=2; Y=0; Z=2x+2; Or x=4; Y=0,1; Z=2x-y.The time that this step is carried out is 2-60s.
Carve in the step Cl in the reactant gases main 2Flow be that the flow of 0-100sccm, HBr is 100-300sccm and He and O 2The flow of mixed gas is 0-50sccm, and upper electrode power is 300-450w, and lower electrode power is 20-80w, and pressure is 7-20mTorr, and the time that this step is carried out is 2-90s.
Crossing in the step at quarter, the flow of HBr is that the flow of 100-400sccm, He is 0-200sccm in the reactant gases, and He and O 2Flow be 0-50sccm, upper electrode power is 200-350w, lower electrode power is 40-120w, pressure is 40-80mTorr, the time 2-180s that this step is carried out.
The present invention is applicable to 500nm-65nm technology lines etching.
(3) beneficial effect
Technology of the present invention can well be removed the polymer residue of optical cement at silicon face under the prerequisite that does not change hardware design, thereby has improved the problem of line roughness, satisfies the needs of advanced gate etching process.This method is simple, has not only avoided the parameter that The Hardware Design increased, has guaranteed the stability of technology; Can also avoid system upgrade, save the writing spending.
Description of drawings
Fig. 1 is the structural representation before the polysilicon gate etching;
The lines of Fig. 2 for obtaining with the prior art lithographic method
The lines of Fig. 3-7 for obtaining with lithographic method of the present invention.
Wherein the observation equipment used of Fig. 2-7 is the S-4700 awkward silence at a meeting scanning electronic microscope that Hitachi, Ltd produces.
Embodiment
Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiment only to be used to the present invention is described and be not used in and limit the scope of the invention.
Embodiment 1
Technology (etching) equipment: the commercial etching machine of northern microelectronics
Processing step:
(1) just carves: CF in the reactant gases 4Flow be 50sccm, Cl 2Flow be 0sccm, upper electrode power is 350w, lower electrode power is 40w, pressure is 10mTorr, the time that this step is carried out is 5 seconds.
(2) the main quarter: Cl in the reactant gases 2Flow be that the flow of 10sccm, HBr is 150sccm and HeO 2Flow be 10sccm, upper electrode power is 300w, lower electrode power is 80w, pressure is 7mTorr, the time that this step is carried out is 30 seconds.
(3) spend quarter: the flow of HBr is that the flow of 100sccm, He is 100sccm in the reactant gases, and HeO 2Flow be 15sccm, upper electrode power is 250w, lower electrode power is 100w, pressure is 80mTorr, the time that this step is carried out is 60 seconds.
Observe (magnification is 120,000 times) with the HitachiS-4700 field emission scanning electron microscope, as shown in Figure 2, the lines after the gained etching are coarse, and rectilinearity is poor.
Embodiment 2
According to the method for embodiment 1, after difference was hard mask etching, etching before carrying out before the etching polysilicon just carving was with SF 6As reactant gases, flow is 100sccm, and upper electrode power is 200w, and lower electrode power is 0w, and pressure is 60mTorr.
As shown in Figure 3, the line edge after the gained etching is smooth, and rectilinearity is good.(magnification is 150,000 times)
Embodiment 3
According to the method for embodiment 2, difference is with NF 3As reactant gases, flow is 5sccm, and upper electrode power is 500w, and lower electrode power is 0w, and pressure is 0Torr.
As shown in Figure 4, the line edge after the gained etching is smooth, and rectilinearity is good.(magnification is 8.5 ten thousand times)
Embodiment 4
According to the method for embodiment 2, difference is with SF 6, Cl 2And O 2As reactant gases, total gas flow rate is 1000sccm, wherein SF 6Be 200sccm, Cl 2Be 600sccm, O 2Be 200sccm, upper electrode power is 500w, and lower electrode power is 0w, and pressure is 80Torr.
As shown in Figure 5, the line edge after the gained etching is smooth, and rectilinearity is good.(magnification is 100,000 times)
Embodiment 5
According to the method for embodiment 2, difference is with SF 6And C 4HF 3As reactant gases, total gas flow rate is 800sccm, wherein SF 6Be 50sccm, upper electrode power is 50w, and lower electrode power is 0w, and pressure is 100Torr.
As shown in Figure 6, the line edge after the gained etching is smooth, and rectilinearity is good.(magnification is 150,000 times)
Embodiment 6
According to the method for embodiment 2, difference is with NF 3, CF 4And C 2F 6As reactant gases, the overall process gas flow is 400sccm, wherein NF 3Be 90sccm, CF 4Be 300sccm, C 2F 6Be 10sccm, upper electrode power is 90w, and lower electrode power is 0w, and pressure is 30Torr.
As shown in Figure 7, the line edge after the gained etching is smooth, and rectilinearity is good.(magnification is 150,000 times)

Claims (6)

1, a kind of polycrystalline silicon etching method, its step is as follows: just carved etching, (2) before just carved (1), (3) are main carves and (4) are crossed and carved, and wherein used process gas is SF in the step (1) 6Or NF 3
2, lithographic method as claimed in claim 1 is characterized in that used process gas is SF in the described step (1) 6
3, lithographic method as claimed in claim 1 or 2 is characterized in that used process gas also comprises in the described step (1) to be selected from C xH yF z, Cl 2And O 2In one or more gases, at C xH yF zIn, x=1, y=0,1, z=2x+2-y; Or x=2, y=0, z=2x+2; Or x=4, y=0,1; Z=2x-y.
4, lithographic method as claimed in claim 1 or 2 is characterized in that used process gas also comprises CF in the described step (1) 4
5, lithographic method as claimed in claim 1 or 2 is characterized in that process gas flow is 5-200sccm in the described step (1), and upper electrode power is 50-500w, and lower electrode power is 0w, and pressure is 0-100mTorr.The time that this step is carried out is 2-100s.
6, lithographic method as claimed in claim 3 is characterized in that process gas flow is 5-1000sccm, wherein SF in the described step (1) 6Or NF 3Flow be 5-200sccm.
CN 200510126289 2005-12-02 2005-12-02 Polycrystalline silicon etching method for improving line roughness Pending CN1851049A (en)

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Application Number Priority Date Filing Date Title
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347232A (en) * 2011-09-28 2012-02-08 上海宏力半导体制造有限公司 Dry etching method of silicon
CN101777485B (en) * 2009-01-12 2015-01-14 北京北方微电子基地设备工艺研究中心有限责任公司 Etching method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101777485B (en) * 2009-01-12 2015-01-14 北京北方微电子基地设备工艺研究中心有限责任公司 Etching method
CN102347232A (en) * 2011-09-28 2012-02-08 上海宏力半导体制造有限公司 Dry etching method of silicon

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