CN1309867C - Polycrystal silicon etching process with reduced micro channel effect - Google Patents
Polycrystal silicon etching process with reduced micro channel effect Download PDFInfo
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- CN1309867C CN1309867C CNB2004100871009A CN200410087100A CN1309867C CN 1309867 C CN1309867 C CN 1309867C CN B2004100871009 A CNB2004100871009 A CN B2004100871009A CN 200410087100 A CN200410087100 A CN 200410087100A CN 1309867 C CN1309867 C CN 1309867C
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Abstract
The present invention relates to an etching technique for multicrystal silicon, which comprises the following steps: (1) etching hard mask films, (2) degumming; (3) etching multicrystal silicon; (4) over etching: the flow quantity of hydrogen bromide in reaction gases is from 100 to 500 sccm, the flow quantity of nitrogen is from 1 to 50 sccm, the flow quantity of helium / oxygen is from 0 to 100 sccm, the power of an upper electrode and the power of a lower electrode are respectively from 400 to 1500 W and from 0 to 200 W, and the pressure is from 10 to 50 mTorr. The present invention aims at a novel structure of a hard mask film layer, and the hard mask film layer is composed of oxides which etch RCHX+ silicon by carbon tetrafluoride; small amounts of polymers of (CF2)n can be formed by fluorine and carbon; therefore, the side wall of the hard mask film layer is protected; the addition of the oxygen can generate more F atoms, the etching of the hard mask film layer is accelerated, and the generation of micro-channels is reduced.
Description
Technical field
The present invention relates to the improvement of polycrystalline silicon etching process, the technology after the improvement can reduce the phenomenon of the frequent little raceway groove (Mircotrench) that occurs in the etching polysilicon process.
Background technology
In deep submicron process, along with the etching polysilicon lines are more and more thinner, the lines depth-width ratio after the etching is also just increasing at present, and the phenomenon of little like this raceway groove (Mircotrench) will be obvious more.The generation of little raceway groove (Mircotrench) mainly is because the anisotropy of electronics in etching process makes on its upper layer of material that is accumulated in polysilicon, produces electric field.Positive charge in the etching gas has the same tropism of etching, under the effect of lower electrode bias, should vertically bombard polysilicon surface, but because the existence of this electric field, changed the direction of motion of positive charge, make its bombardment of relatively concentrating at the edge of polysilicon, thereby produce little raceway groove (Mircotrench) phenomenon, as shown in Figure 2.Mentioned a kind of etching structure in the United States Patent (USP) that one piece of patent No. is US20040092089, the material of its hard mask layer and traditional hard mask layer is different.But the etching technics of the hard mask material of this patent also is not enough to eliminate fully micro-channel phenomenon.
Summary of the invention
The purpose of this invention is to provide a kind of polycrystalline silicon etching process that can eliminate little raceway groove (Mircotrench) phenomenon basically.
The objective of the invention is to reach by the following technical programs:
Polysilicon silicon chip erosion pre-structure is as follows:
(1) bottom is a silicon chip;
(2) growth layer of silicon dioxide 10-50 dust on the silicon chip;
(3) growth one deck polysilicon 1000-3000 dust on the silicon-dioxide;
(4) the hard mask of growth one deck on the polysilicon; Hard mask is divided into double-layer structure, and the upper strata is RCHX, and wherein R is Si, Ge, and B, Sn, Fe, a kind of among the Ti, X is O, N, S, a kind of among the F, thickness is at the 300-500 dust.Lower floor is the oxide compound of silicon, and thickness is at the 100-200 dust.
Silicon chip topmost is the optical cement figure after the photoetching.
A kind of polycrystalline silicon etching process, its step is as follows:
1, the hard mask of etching: the flow of fluoro-gas tetrafluoro-methane is 0-80sccm in the reactant gases, and the flow of oxygen is 0-15sccm, and the flow of argon gas is 0-500sccm, and upper/lower electrode power is respectively 400-1000w, 0-1000w, and pressure is 5-20mTorr;
2, remove photoresist: the employing independently chamber of removing photoresist is removed photoresist;
3, etching polysilicon:
The flow of oxygen is 1-5sccm in the reactant gases, and the flow of nitrogen is 1-50sccm, and the flow of methylene fluoride is 0-100sccm, and the flow of chlorine is 50-500sccm, and upper/lower electrode power is respectively 400-1500w, 0-1000w, and pressure is 20-100mTorr;
4, over etching:
The flow of hydrogen bromide is 100-500sccm in the reactant gases, the flow of nitrogen is 1-50sccm, the flow of helium/oxygen (wherein the volume ratio of helium is at 60-80%) is 0-100sccm, and upper/lower electrode power is respectively 400-1500w, 0-200w, and pressure is 10-50mTorr.
A kind of optimal technical scheme, it is characterized in that: the flow of fluoro-gas tetrafluoro-methane is 10-70sccm in the reactant gases in the described step 1, the flow of oxygen is 5-10sccm, the flow of argon gas is 50-300sccm, upper/lower electrode power is respectively 600-800w, 100-500w, and pressure is 10-15mTorr.
A kind of optimal technical scheme, it is characterized in that: in the described step 3 reactant gases in the flow of oxygen be 2-4sccm, the flow of nitrogen is 10-30sccm, the flow of methylene fluoride is 40-70sccm, the flow of chlorine is 150-300sccm, upper/lower electrode power is respectively 800-1200w, 100-800w, and pressure is 40-60mTorr.
A kind of optimal technical scheme, it is characterized in that: the flow of hydrogen bromide is 200-400sccm in the reactant gases in the over etching of described step 4, the flow of nitrogen is 10-30sccm, the flow of helium/oxygen (wherein the volume ratio of helium is at 60-80%) is 10-50sccm, upper/lower electrode power is respectively 800-1200w, 80-150w, and pressure is 20-40mTorr.
Tetrafluoro-methane and chlorine have polymkeric substance to produce, oxygen, and nitrogen increases pressure, helps polymer deposition.
During near etching terminal, the etching speed of HBr gas is low, to SiO
2Selection than high, can the balance etching speed, and lower electrode power is generally very low.
According to the present invention,, thereby produce with in the past at the oxide compound that uses silicon and oxynitride different etching technics during as hard mask layer (Hardmask) material at the structure of novel hard mask layer (Hardmask).In the process of etching hard mask layer, use the hard mask layer of the oxide compound composition of tetrafluoro-methane etching RCHX+ silicon, fluorine and carbon can form a spot of (CF
2)
nPolymkeric substance, thereby the sidewall of protection hard mask layer, the adding of oxygen can produce more F atom, quickens the etching of hard mask layer.
The etching polysilicon step in two steps, use methylene fluoride gas in the process main quarter, increase along with etching depth, it is big that depth-width ratio becomes, little channelling effect begins to produce, and in plasma body, derives from the hydrogen in RCHX and the methylene fluoride because mass of ion is light, radius is little, is easy to accumulate in the sidewall and the bottom of etching window.Formation (CF will be impelled in the place that hydrogen concentration is high
2)
nCover polysilicon sidewall and etching surface edge, so just protected the etching surface edge, reduced F/C in addition, slow down etching speed, help polymer deposition than (less than 4) by the transition etching.Chlorine also can form (SiCL with silicon
2) n polymkeric substance protection polysilicon sidewall.Nitrogen can reduce the temperature of bombardment electric charge in the plasma, the while control pressure, and this moment, the numerical value of pressure was higher, provided the sufficient time to polymer deposition.
In the over etching process, use Si/SiO
2Selection can etch away the resistates of polysilicon so completely than high HBr gas, is unlikely to SiO simultaneously
2There is the phenomenon of undercutting to take place.This moment, the power of lower electrode was preferably zero, reduced isoionic bombarding energy.
The present invention adopts polymkeric substance protection, and the high selectivity gas etching increases chamber pressure, improves nitrogen flow, and the way that reduces electronic temp and reduce lower electrode bias reduces and eliminates little raceway groove (Mircotrench).
The present invention is described in detail but and do not mean that limiting the scope of the invention below by the drawings and specific embodiments.
Description of drawings
Fig. 1 is the structural representation of etching polysilicon.
Fig. 2 is existing etching polysilicon effect partial enlarged drawing.
Fig. 3 is an etching polysilicon effect partial enlarged drawing of the present invention.
Embodiment
The comparative example 1
Polysilicon silicon chip erosion pre-structure is as follows:
(1) bottom is a silicon chip;
(2) growth layer of silicon dioxide 20 dusts on the silicon chip;
(3) growth one deck polysilicon 1500 dusts on the silicon-dioxide;
(4) oxide compound of the method for CVD grown silicon on polysilicon and the hard mask layer of oxynitride, thickness 500 dusts;
(5) silicon chip topmost is the optical cement figure after the photoetching.
A kind of polycrystalline silicon etching process, its step is as follows:
(1) the hard mask of etching: fluoro-gas in the reactant gases mainly is a tetrafluoro-methane, and flow is 100sccm, and the flow of oxygen is 30sccm, and the flow of argon gas is 200sccm, and upper/lower electrode power is respectively 1000w, 150w, and pressure is 2mTorr;
(2) remove photoresist: the employing independently chamber of removing photoresist is removed photoresist;
(3) etching polysilicon:
The flow of oxygen is 15sccm in the reactant gases, and the flow of tetrafluoro-methane is 80sccm, and the flow of hydrogen bromide is 150sccm, and upper/lower electrode power is respectively 700w, 60w, and pressure is 10mTorr;
(4) over etching:
The flow of hydrogen bromide is 300sccm in the reactant gases, and the flow of helium/oxygen is 80sccm, and upper/lower electrode power is respectively 750w, 0w, and pressure is 15mTorr.
As shown in Figure 2, the etching line edge of the structure of gained etch polysilicon has little raceway groove.
As shown in Figure 1, polysilicon silicon chip erosion pre-structure is as follows:
(1) bottom 4 is a silicon chip;
(2) silicon-dioxide 3 of growth one deck 40 dusts on the silicon chip;
(3) polysilicon 2 of growth one deck 1500 dusts on the silicon-dioxide;
(4) hard mask layer 1 of the oxide compound of the method for PECVD grown silicon on polysilicon and RCHX, thickness 600 dusts;
(5) silicon chip topmost is the optical cement figure after the photoetching.
A kind of polycrystalline silicon etching process, its step is as follows:
(1) the hard mask of etching: the flow of fluoro-gas tetrafluoro-methane is 60sccm in the reactant gases, and the flow of oxygen is 10sccm, and the flow of argon gas is 10sccm, and upper/lower electrode power is respectively 900w, 200w, and pressure is 10mTorr;
(2) remove photoresist: the employing independently chamber of removing photoresist is removed photoresist;
(3) etching polysilicon:
The flow 5sccm of oxygen in the reactant gases, the flow of nitrogen is 40sccm, and the flow of methylene fluoride is 90sccm, and the flow of chlorine is 300sccm, and upper/lower electrode power is respectively 1000w, 500w, and pressure is 50mTorr;
(4) over etching:
The flow of hydrogen bromide is 300sccm in the reactant gases, and the flow of nitrogen is 45sccm, and the flow of helium/oxygen (the helium volume ratio accounts for 70%) is 80sccm, and upper/lower electrode power is respectively 800w, 0w, and pressure is 40mTorr.
Polysilicon silicon chip erosion pre-structure is as follows:
(1) bottom is a silicon chip;
(2) growth layer of silicon dioxide 25 dusts on the silicon chip;
(3) growth one deck polysilicon 2000 dusts on the silicon-dioxide;
(4) oxide compound of the method for PECVD grown silicon on polysilicon and the hard mask layer of RCHX, thickness 500 dusts:
(5) silicon chip topmost is the optical cement figure after the photoetching.
A kind of polycrystalline silicon etching process, its step is as follows:
(1) the hard mask of etching: the flow of fluoro-gas tetrafluoro-methane is 10sccm in the reactant gases, and the flow of oxygen is 2sccm, and the flow of argon gas is 40sccm, and upper/lower electrode power is respectively 400w, 1000w, and pressure is 20mTorr;
(2) remove photoresist: the employing independently chamber of removing photoresist is removed photoresist;
(3) etching polysilicon:
The flow 4sccm of oxygen in the reactant gases, the flow of nitrogen is 35sccm, and the flow of methylene fluoride is 80sccm, and the flow of chlorine is 50sccm, and upper/lower electrode power is respectively 1400w, 50w, and pressure is 20mTorr;
(4) over etching:
The flow of hydrogen bromide is 500sccm in the reactant gases, and the flow of nitrogen is 35sccm, and the flow of helium/oxygen (volume ratio of helium accounts for 60%) is 100sccm, and upper/lower electrode power is respectively 1500w, 200w, and pressure is 50mTorr.
Polysilicon silicon chip erosion pre-structure is as follows:
(1) bottom is a silicon chip;
(2) growth layer of silicon dioxide 15 dusts on the silicon chip;
(3) growth one deck polysilicon 1500 dusts on the silicon-dioxide;
(4) oxide compound of the method for PECVD grown silicon on polysilicon and the hard mask layer of RCHX, thickness 400 dusts;
(5) silicon chip topmost is the optical cement figure after the photoetching.
A kind of polycrystalline silicon etching process, its step is as follows:
(1) the hard mask of etching: the flow of fluoro-gas tetrafluoro-methane is 40sccm in the reactant gases, and the flow of oxygen is 15sccm, and the flow of argon gas is 500sccm, and upper/lower electrode power is respectively 800w, 100w, and pressure is 5mTorr;
(2) remove photoresist: the employing independently chamber of removing photoresist is removed photoresist;
(3) etching polysilicon:
The flow 3sccm of oxygen in the reactant gases, the flow of nitrogen is 3sccm, and the flow of methylene fluoride is 7sccm, and the flow of chlorine is 200sccm, and upper/lower electrode power is respectively 400w, 1000w, and pressure is 100mTorr;
(4) over etching:
The flow of hydrogen bromide is 100sccm in the reactant gases, and the flow of nitrogen is 3sccm, the flow 6sccm of helium/oxygen (volume ratio of helium accounts for 80%), and upper/lower electrode power is respectively 400w, 100w, and pressure is 10mTorr.
The structure of gained etch polysilicon does not produce micro-channel phenomenon in etching lines bottom as shown in Figure 3.
Claims (5)
1, a kind of polycrystalline silicon etching process, its step is as follows:
(1) the hard mask of etching: the flow of fluoro-gas tetrafluoro-methane is 10-70sccm in the reactant gases, and the flow of oxygen is 5-10sccm, and the flow of argon gas is 50-300sccm, and upper/lower electrode power is respectively 600-800w, 100-500w, and pressure is 10-15mTorr;
(2) remove photoresist: the employing independently chamber of removing photoresist is removed photoresist;
(3) etching polysilicon:
The flow of oxygen is 2-4sccm in the reactant gases, and the flow of nitrogen is 10-30sccm, and the flow of methylene fluoride is 40-70sccm, and the flow of chlorine is 150-300sccm, and upper/lower electrode power is respectively 800-1200w, 100-800w, and pressure is 40-60mTorr;
(4) over etching:
The flow of hydrogen bromide is 200-400sccm in the reactant gases, and the flow of nitrogen is 10-30sccm, and the flow of the mixed gas of helium and oxygen is 10-50sccm, and upper/lower electrode power is respectively 800-1200w, 80-150w, and pressure is 20-40mTorr.
2, polycrystalline silicon etching process according to claim 1 is characterized in that: in the mixed gas of helium and oxygen, the volume ratio of helium is at 60-80% described in the described step (4).
3, according to the polycrystalline silicon etching process described in the claim 2, it is characterized in that: in the helium of described step (4) and the mixed gas of oxygen, the volume ratio of helium is 70%.
4, polycrystalline silicon etching process according to claim 3 is characterized in that: the hard mask of etching in the described step (1) is divided into double-layer structure, and the upper strata is RCHX, and wherein R is Si, Ge, B, Sn, Fe, a kind of among the Ti, X is O, N, S, a kind of among the F, lower floor is the oxide compound of silicon.
5, polycrystalline silicon etching process according to claim 4 is characterized in that: the thickness on described upper strata is at the 300-500 dust, and the thickness of described lower floor is at the 100-200 dust.
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| CN101241853B (en) * | 2007-02-06 | 2010-09-29 | 中芯国际集成电路制造(上海)有限公司 | A grid making method for improving multi-crystal silicon grid side profile |
| CN102376571B (en) * | 2010-08-19 | 2015-12-16 | 中芯国际集成电路制造(上海)有限公司 | Manufacture the method for semiconductor device |
| CN104124203B (en) * | 2013-04-28 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | The forming method of interconnection structure |
| CN104779151B (en) * | 2014-01-13 | 2018-01-26 | 北大方正集团有限公司 | A kind of polycrystalline silicon etching method |
| CN107403787B (en) * | 2017-08-02 | 2020-02-21 | 武汉新芯集成电路制造有限公司 | Method for forming metal isolation gate |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5094712A (en) * | 1990-10-09 | 1992-03-10 | Micron Technology, Inc. | One chamber in-situ etch process for oxide and conductive material |
| JPH06163478A (en) * | 1992-11-18 | 1994-06-10 | Nippondenso Co Ltd | Dry etching method of semiconductor |
| JPH11260799A (en) * | 1998-03-13 | 1999-09-24 | Hitachi Ltd | Fine working method of thin film |
| CN1110843C (en) * | 1998-01-16 | 2003-06-04 | 日本电气株式会社 | Method for etching silicon layer |
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2004
- 2004-10-28 CN CNB2004100871009A patent/CN1309867C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5094712A (en) * | 1990-10-09 | 1992-03-10 | Micron Technology, Inc. | One chamber in-situ etch process for oxide and conductive material |
| JPH06163478A (en) * | 1992-11-18 | 1994-06-10 | Nippondenso Co Ltd | Dry etching method of semiconductor |
| CN1110843C (en) * | 1998-01-16 | 2003-06-04 | 日本电气株式会社 | Method for etching silicon layer |
| JPH11260799A (en) * | 1998-03-13 | 1999-09-24 | Hitachi Ltd | Fine working method of thin film |
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Address after: 100176 8 Wenchang Avenue, Beijing economic and Technological Development Zone, Beijing Patentee after: Beijing North China microelectronics equipment Co Ltd Address before: 100016 floor 2, block M5, 1 Jiuxianqiao East Road, Chaoyang District, Beijing. Patentee before: Beifang Microelectronic Base Equipment Proces Research Center Co., Ltd., Beijing |