CN100377313C - Method for increasing deep submicron multiple crystalline silicon grating etching uniformity - Google Patents

Abstract

The present invention discloses a method for enhancing the corrasion evenness of a deep sub-micron polysilicon gate, which is composed of the five steps of corrasion and degumming of a hard mask layer, main corrasion of polysilicon, grid corrasion, formation of a micro groove, etc. In the present invention, the micro groove is formed at the bottom of a line, which reduces the channel width to some extent, and controls line pattern, and accordingly, the device performance is enhanced.

Description

Improve the method for deep submicron multiple crystalline silicon grating etching uniformity

Technical field

The present invention relates to a kind of method that improves deep submicron multiple crystalline silicon grating etching uniformity.The method also can form micronotch (little groove) in the lines bottom, has reduced channel width to a certain extent, has controlled the lines pattern, thereby has improved the performance of device.

Background technology

At present, traditional grid etch technology often avoids occurring undercutting, " beak " phenomenon in order to obtain steep figure when the etching of lines.But along with further dwindling of semiconductor device, existing lithographic capabilities can not adapt to the line size that reduces day by day gradually.Therefore the potentiality of excavation process become necessary.

When the technology of 0.3um characteristic size became main flow, just the someone proposed and carries out the T-shape processing step.Promptly form grid structure wide at the top and narrow at the bottom by increasing processing step and gaseous species, this method can reduce the requirement to photoetching effectively, has lowered the difficulty that interconnection is aimed at simultaneously again.But this method is very strict to the requirement of process conditions, need define the process time of each step and the proportion relation of each gas rigorously, and process window is less, can not be applicable to large-scale operation.

Summary of the invention

The purpose of this invention is to provide a kind of method that improves deep submicron multiple crystalline silicon grating etching uniformity.

This method at grid structure, comprise successively from top to bottom: the photoresist layer that photoetching is good is the organic carbonaceous material, about 3000A-5000A; Hard mask layer, 400A-2000A; Polysilicon layer, 1500A-5000A; Gate oxide, 15A-100A; Bottom is a silicon substrate.

For achieving the above object, the present invention adopts steps A, B, C, D and E to constitute (gas component of the present invention all adopts percent by volume) successively:

A. hard mask layer is carried out etching: behind hard mask etching (hardmask open), remove photoresist.Etching gas comprises the NF of 40-60% ₃Or SF ₆, 20-50% Cl ₂Ar (all being volume ratio) with 10-20%.

To the etching of hard mask, mainly consisting of of gas contains F gas and Cl ₂, Ar.F and Cl are reactive material in the etching process, contain F gas and can adopt NF ₃Or SF ₆, reduce the generation of polymer; Behind plasma exciatiaon, Ar ⁺Mainly play the effect of physical bombardment, so that open the firm molecular link of hard mask layer, the carrying out of accelerated reaction.The substrate bias of this step etching is-and 100V is to-200V, and power 80W could guarantee higher etch rate like this.Preferably, etching gas comprises the NF of 40-60vt% ₃, 20-50vt% Cl ₂Ar (all being volume ratio) with 10-20vt%.

B. remove photoresist: feed big flow (3000～4000sccm) O ₂Removing of photoresist by plasma or in the chamber that independently removes photoresist, remove photoresist.

Because depth-width ratio (aspect ratio) further strengthens in deep submicron process, if therefore under the situation that keeps photoresist, continue etching, the sustainable growth of depth-width ratio will inevitably cause serious antenna effect so, causes gate insulation layer to puncture, even component failure.Therefore, this method is promptly removed photoresist behind hardmask open.Can feed big flow O ₂Removing of photoresist by plasma or in the chamber that independently removes photoresist, remove photoresist.

C. polysilicon is carried out main etching: etching gas comprises the CHF of 10-30vt% ₃, 40-80vt% Cl ₂He/O with 10-30vt% ₂Mist (O ₂Account for He/O ₂The 30vt% of mist).

The substrate bias of etching polysilicon (main etching) is-100V is to-200V, could form good passivation layer like this on sidewall.Substrate bias power is 50～80W, at 70W better effects is arranged.

It is pointed out that if polysilicon layer be entrained in distribution difference on the whole wafer, mixing such as existing N type on the same wafer has the P type to mix again, so merely at Cl ₂Etch rate exists very big difference under the effect of this a kind of etching agent, is difficult to guarantee the uniformity of etching.Be directed to this point, it is close to the etching polysilicon speed of N type or P type to contain F gas, mixes to contain the uniformity that F gas helps etch rate.But because the etch rate of F is too high, caused quarter or sidewall to corrode easily, this method is selected CHF for use ₃, because CHF ₃In course of reaction, can produce a lot of fluorinated polymer, can the passivation sidewall, so not only guaranteed the uniformity of etch rate but also can not influence the steep of sidewall.

D. in the over etching stage of grid, used gas must have good selectivity (at least 150: 1, with respect to insulating barrier under the grid, just oxide layer).The gas that wherein contains Br, Cl and O has good selectivity; The reaction of HBr and polysilicon than chlorine slowly many, so the etching of HBr is controlled profile easily.The HBr of gases used composition: 70-90vt%, the Cl of 0-10vt% ₂He/O with 10-20vt% ₂Mist (O ₂Account for He/O ₂The 30vt% of mist).The substrate bias power of over etching is 40～50W.

E. little groove forms the stage, the gas O of this moment ₂Content increases, and substrate bias should be littler or be zero simultaneously.So just can avoid destroying thin oxide layer, simultaneously to grid line bar bottom etching, gases used can be by the HBr of 50-80vt% and the He/O of 20-50vt% ₂Mist (O ₂Account for He/O ₂The 30vt% of mist).The selection ratio in this stage can reach 200: 1 or be higher.Can control the formation of little groove in this step process according to the time.

Advantage of the present invention is: the application of this method can reduce the further requirement to photoetching technique, has guaranteed the uniformity of the steep and whole wafer of etching profile simultaneously, has improved the performance of the semiconductor device of being done.

Description of drawings

Fig. 1 is little groove structure schematic diagram of the present invention;

Fig. 2 is the profile as a result of the embodiment of the invention 1.The FE-SEM4700 of Hitachi image, accelerating voltage 1kV, 100,000 times of multiplication factors.

Among the figure, 1 is grid, and 2 is microflute, and 3 is gate insulation layer, and 4 is substrate.

Embodiment

The embodiment that provides below is used for further setting forth the present invention, and does not constitute limitation of the scope of the invention.

1. material

Used and other the gas of embodiment is provided by the special gas in Hong Kong company, and purity is all greater than 99.999%.

2. equipment

Use RAINBOW4420 etching polysilicon machine to handle.

Embodiment 1～5 is shown in the 4th page table 1.

As shown in Figure 2,, form microflute 2, can improve the performance of the semiconductor device of being done in the bottom of grid 1 through processing method of the present invention.

Table 1

Step	Embodiment 1	Embodiment 2	Embodiment 3	Embodiment 4	Embodiment 5
						Hard mask etching	V is 200sccm 60%NF 3 30％Cl 210%Ar P is 100W	V is 200sccm 60%NF 3 20％Cl 220%Ar P is 90W	V is 200sccm 40%NF 3 40％Cl 220%Ar P is 100W	V is 200sccm 45%SF 6 40％Cl 215%Ar P is 90W	V is 200sccm 40%SF 6 50％Cl 210%Ar P is 100W
Remove photoresist	O 23500sccm P is 0W	O 23500sccm P is 0W	O 23500sccm P is 0W	O 23500sccm P is 0W	O 23500sccm P is 0W
						The polysilicon main etching	V is 200sccm 10%CHF 3 80％Cl 2 10％He/O 2P is 80W	V is 200sccm 30%CHF 3 40％Cl 2 30％He/O 2P is 50W	V is 200sccm 20%CHF 3 65％Cl 2 15％He/O 2P is 70W	V is 200sccm 15%CHF 3 70％Cl 2 15％He/O 2P is 70W	V is 200sccm 20%CHF 3 60％Cl 2 20％He/O 2P is 75W
Over etching	V is 150sccm 70%HBr 10%Cl 2 20％He/O 2P is 50W	V is 150sccm 90%HBr 0%Cl 2 10％He/O 2P is 50W	V is 150sccm 75%HBr 5%Cl 2 20％He/O 2P is 40W	V is 150sccm 75%HBr 10%Cl 2 15％He/O 2P is 50W	V is 150sccm 80%HBr 0%Cl 2 20％He/O 2P is 40W
						Little etching groove	V is 150sccm 80%HBr 20%He/O 2P is 40W	V is 150sccm 75%HBr 25%He/O 2P is 40W	V is 150sccm 50%HBr 50%He/O 2P is 50W	V is 150sccm 80%HBr 20%He/O 2P is 40W	V is 150sccm 60%HBr 40%He/O 2P is 50W

In the table, V is a total gas flow rate, and P is a substrate bias power.

Claims (9)

1. a method that improves deep submicron multiple crystalline silicon grating etching uniformity is characterized in that, adopt steps A, B, C, D and E to constitute successively: A. carries out etching to hard mask layer; B. feed O ₂Removing of photoresist by plasma or in the chamber that independently removes photoresist, remove photoresist; C. polysilicon is carried out main etching; D. grid is carried out over etching; E. form little groove; In the described steps A, etching gas is the NF of 40-60vt% ₃Or SF ₆, 20-50vt% Cl ₂Ar with 10-20vt%.

2. the method for raising deep submicron multiple crystalline silicon grating etching uniformity according to claim 1 is characterized in that: among the described step B, and O ₂The flow of plasma is 3000～4000sccm.

3. the method for raising deep submicron multiple crystalline silicon grating etching uniformity according to claim 1 is characterized in that: among the described step C, etching gas is the CHF of 10-30vt% ₃, 40-80vt% Cl ₂He/O with 10-30vt% ₂Mist, wherein O ₂Account for He/O ₂The 30vt% of mist.

4. the method for raising deep submicron multiple crystalline silicon grating etching uniformity according to claim 1 is characterized in that: among the described step D, and the HBr of gases used composition: 70-90vt%, the Cl of 0-10vt% ₂He/O with 10-20vt% ₂Mist, wherein O ₂Account for He/O ₂The 30vt% of mist.

5. the method for raising deep submicron multiple crystalline silicon grating etching uniformity according to claim 1 is characterized in that: in the described step e, and the HBr of gases used composition: 50-80vt% and the He/O of 20-50vt% ₂Mist, wherein O ₂Account for He/O ₂The 30vt% of mist.

6. the method for raising deep submicron multiple crystalline silicon grating etching uniformity according to claim 1 is characterized in that: and in the described steps A, substrate bias is-and 100V is to-200V, power 80W.

7. the method for raising deep submicron multiple crystalline silicon grating etching uniformity according to claim 1 is characterized in that: among the described step C, substrate bias power is 50～80W.

8. the method for raising deep submicron multiple crystalline silicon grating etching uniformity according to claim 7 is characterized in that: among the described step C, substrate bias power is 70W.

9. the method for raising deep submicron multiple crystalline silicon grating etching uniformity according to claim 1 is characterized in that: among the described step D, substrate bias power is 40～50W.