CN100397590C - Gate etching process - Google Patents
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- CN100397590C CN100397590C CNB2005101262657A CN200510126265A CN100397590C CN 100397590 C CN100397590 C CN 100397590C CN B2005101262657 A CNB2005101262657 A CN B2005101262657A CN 200510126265 A CN200510126265 A CN 200510126265A CN 100397590 C CN100397590 C CN 100397590C
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Abstract
The present invention provides a gate etching process capable of increasing the control ability of grid etching critical dimension, which comprises a BT step, a main etching step and an over etching step, wherein gas used in the main etching step is selected from one of N< 2 >O, NO, NO< 2 >, NO< 3 >, N< 2 >O< 5 > and the mixed gas of Cl< 2 > and HBr. The gate etching process provided by the present invention is suitable for all grid etching devices and can increase the control ability of critical dimension of the gate etching process in all etching processes respectively using an SiON layer as a hard mask.
Description
Technical field
The present invention relates to a kind of gate etching process, specifically, relate to a kind of gate etching process that can improve grid etching critical size (CD) control ability.
Background technology
Photoetching process and gate etching process are the important steps that realizes semiconductor manufacturing feature size, development along with semiconductor technology, the lines of grid etching are more and more narrow, realize that in gate etching process the difficulty of critical size (CD, Critical Dimension) control also constantly raises thereupon.
Along with the grid lines are more and more thinner, traditional utilize the photoresistance pattern (the normal light resistance layer is very thick because the defective of self can't satisfy the needs of technology for mask carries out the technology of silicon materials etching, about 3000-6000 dust, and present lines are more and more thinner, the 500-1300 dust is only arranged, therefore the depth-to-width ratio during etching is very big, and the difficulty that process gas diffuses into the mask lines is very big; In addition, the 248-193nm photoresist that adopts during sophisticated semiconductor is made is very easy to distortion under condition of plasma, can't guarantee the smooth transfer of photoresistance pattern, that is to say that CD control is poor).Therefore, semiconductor fabrication process adds SiON layer or SiO between photoresist layer and polysilicon layer at present
2/ SiON double-decker is called hard mask (Hard Mask).In the gate etching process, at first with the photoresistance design transfer to hard mask layer, photoresist layer is removed, harder mask pattern is transferred to polysilicon layer, form Si-gate, at last hard mask layer is removed.Before photoetching process begins, film layer structure is followed successively by silicon chip (Si Substrate) grid oxide layer (Oxide) 10-80 dust/polysilicon (Poly Si) 1000-2000 dust/hard mask (HardMask is SiON or SiO2/SiON double-decker) 300-500 dust/photoresistance (PR) 3000-6000 dust on the silicon chip.
After film layer structure adds hard mask layer, silicon chip film layer structure when gate etching process begins then becomes the silicon chip/grid oxide layer 10-80 dust/hard mask 300-500 of polysilicon 1000-2000A/ dust by original silicon chip/grid oxide layer 10-80 dust/polysilicon 1000-2000 dust/photoresistance 3000-6000 dust, but gate etching process itself does not change, still be divided into BT (Breakthrough runs through) step, the main quarter (Mainetch) step, cross quarter (Overetch) step three key steps (will lead sometimes carve the step be divided into for two steps and carry out, the process gas kind slightly changes).The wherein main step at quarter is the main body etch step, main carve the step SiON layer (Hard Mask) etching selection ratio (is referred to the etch rate of Si and ratio to the etch rate of SiON, this ratio is big more, then in the process of etching Si, the minimizing of SiON is few more) not high, in etching technics, cause the hard mask layer damage, the etching line thickness obviously narrows down before than etching, deviation appears in CD control, (Critical DimensionControl) is bad for the critical size control ability of etching technics, and this can't accept in being lower than the semiconductor fabrication process of 100nm.So, still need to provide a kind of gate etching process that can improve the critical size control ability.
Summary of the invention
(1) technical problem that will solve
Purpose of the present invention aims to provide a kind of gate etching process, can improve the critical size control ability to satisfy the needs of advanced gate etching process.
(2) technical scheme
For achieving the above object, the present inventor provides a kind of new gate etching process, comprises that BT goes on foot (running through the step), the main quarter goes on foot and cross the step at quarter, and employed gas is for being selected from N in the wherein said main step at quarter
2O, NO, NO
2, NO
3, N
2O
5In a kind of and Cl
2, HBr mist.Preferred Cl
2, HBr and N
2The mist of O.
Employed gas was CF during described BT went on foot
4, C
2F
6, Cl
2In a kind of.
Employed gas is HBr, He and O in the described step at quarter excessively
2Mist.
Wherein main carve the step and cross carve in the step that usage ratio does not have special requirement between the employed all gases.
For the BT step, last RF (radio-frequency power supply) power is 200-400W, and following RF power is 30-100W, and chamber pressure is the 5-15 millitorr, and gas flow is 30-100sccm.
Carve the step for main, last RF power is 250-450W, and following RF power is 30-100W, and chamber pressure is the 5-30 millitorr, and total gas flow rate is 80-310sccm, wherein Cl
2Be 10-50sccm, HBr is 50-200sccm, N
2O, NO, NO
2, NO
3, N
2O
5In a kind of be 20-60sccm.
Carve the step for crossing, last RF power is 250-450W, and following RF power is 30-100W, and chamber pressure is the 5-90 millitorr, and total gas flow rate is 155-530sccm, and wherein HBr is 50-250sccm, and He is 100-250sccm, O
2Be 5-30sccm.
Gate etching process of the present invention possesses the ability (being fit to as 180nm technology, 130nm technology, 90nm technology etc.) of the etching technics of realizing a plurality of technology and to the etching power of different form ratios groove.
Carve the gate etching process master and to use N in the step
2O, NO, NO
2, NO
3, N
2O
5In a kind of gas replace O
2, owing in etching plasma, will have N, O atom or free radical, can effectively restrain process gas and SiON chemical reaction takes place, thereby improve main etching selection ratio of carving step process gas SiON.Former master's step process gas at quarter is 20 to the etching selection ratio of SiON: 1-40: 1; Use N
2O, NO, NO
2, NO
3, N
2O
5In a kind of gas replace O
2After, master's step process gas at quarter can reach 60 to the etching selection ratio of SiON: 1-120: 1, make and carve in the step etching technics that the SiON layer can sustain damage hardly main, thus the critical size control ability of raising gate etching process.
By the awkward silence at a meeting sem observation, SiON damage obviously weakens as can be seen, through to after the measurement of live width before and after the etching as can be known CD Bias obviously reduce, adding N be described
2O, NO, NO
2, NO
3, N
2O
5In a kind of gas after, the CD control ability is significantly improved.
Gate etching process provided by the invention is applicable to all grid etching apparatuss, adopts in the etching technics of SiON layer as hard mask at all and all can improve gate etching process critical size control ability.
(3) beneficial effect
This method can only improve gate etching process critical size control ability by gaseous species and the proportioning that changes main carving technology step in the gate etching process under the prerequisite that does not change hardware designs, satisfy the needs of advanced gate etching process.This method is simple, has not only avoided the parameter that The Hardware Design increased, has guaranteed the stability of technology; Can also avoid system upgrade, save the writing spending.
Description of drawings
Fig. 1 is a silicon chip cross section micrograph after the existing gate etching process etching
Fig. 2 is silicon chip cross section micrograph after the gate etching process etching of the present invention
Device therefor is the S-4700 awkward silence at a meeting scanning electron microscopy that Hitachi, Ltd produces, and multiplication factor is 150,000 times.
Embodiment
Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiment only to be used to the present invention is described and be not used in and limit the scope of the invention.
Embodiment 1
Use silicon etching equipment to be the commercial machine of northern microelectronics 200mm.
The pattern piece silicon chip structure that is adopted is: silicon chip/silicon dioxide (10-100 dust)/polysilicon (1300-2000 dust)/silicon dioxide (100-150 dust)/silicon oxynitride (200-300 dust).It is on silicon dioxide/silicon oxynitride double-decker that the etching figure is transferred to hard mask by photoresistance.Has 80-260nm live width figure on the pattern piece.
In the etching technics, at first import silicon chip into etching reaction chamber, fixing by electrostatic chuck absorption, chamber temp is controlled to be 60 ℃, silicon temperature control system design temperature is 60 ℃, blow system pressure and be set at 8 holders for improving the He gas back of the body that temperature homogeneity adds, after the auxiliary process conditional stability, carry out etching technics.
BT goes on foot etching: the primary thin layer of silicon dioxide (autoxidation forms in the air, and thickness is generally at the 5-20 dust) of removing polysilicon surface.Concrete process conditions are as follows: chamber pressure 7 millitorrs, last RF power 300W, following RF power 80W, process gas CF
4Or C
2F
6Flow 50sccm.Process time 5s.
The main step etching of carving: etching is removed most unwanted silicon materials, forms the silicon gate structure main body, is the main part of etching technics, and the critical size control ability of this step has significant effects to final etching result.Concrete process conditions are as follows: chamber pressure 15 millitorrs, and last RF power 350W, following RF power 50W, process gas is Cl
230sccm, HBr 170sccm, O
2The mist of 10sccm, process time control detects control by end-point detecting system.
Cross and carve the step etching: it is perfect to be used for that the Si-gate shape that the main step at quarter etches is done further finishing.Concrete process conditions are as follows: chamber pressure 80 millitorrs, and last RF power 250W, following RF power 50W, process gas are 180sccm HBr, 100sccm He, 8sccm O
2The mist of forming, process time 50s.
After etching technics is finished; by the awkward silence at a meeting sem observation; the SiON layer is impaired as can be seen; the both sides damage is particularly evident; form round end; SiON in both sides of the edge etches away fully; cause these silicon materials of wishing to keep of edge owing to the protection that loses hard mask is etched away (see figure 1) for hard mask covers; measure the live width of etching front and back by the CD 5 point measurement methods that adopt standard; lines obviously narrow down after can finding etching; deviation (data see Table 1) appears in CD control, and this is unacceptable in being lower than the semiconductor fabrication process of 100nm.Main carve the step etch rate be 1637 dusts/minute.
The CD Bias (nm) of table 1 traditional handicraft
| Measure coordinate | Live width (nm) before the etching | Live width after the etching (nm) | CD Bias (nm) (back value-preceding value) |
| (1，3) | 96.5 | 90.2 | -6.3 |
| (4，3) | 92.3 | 85.1 | -7.2 |
| (4，1) | 94.7 | 87.7 | -7.0 |
| (7，3) | 93.4 | 86.6 | -6.8 |
| (4，5) | 94.4 | 88.7 | -5.7 |
Embodiment 2
According to embodiment 1 described method, difference is, feeds by 15sccmCl main the quarter in the step
2, 140sccm HBr and 50sccm N
2The mist that O forms, other main step process conditions of carving comprise: chamber pressure 15 millitorrs, last RF power 350W, following RF power 40W, process time control detects control by end-point detecting system.
After gate etching process is finished, by awkward silence at a meeting sem observation silicon chip cross section pattern, the SiON layer (see figure 2) that can sustain damage hardly as can be seen, measure the live width of etching front and back by the CD 5 point measurement methods that adopt standard, CD Bias obviously reduces as can be seen, and the CD control ability is significantly improved (seeing Table 2).Main carve the step etch rate be 1461 dusts/minute.
The CD Bias (nm) of table 2 technology of the present invention
| Measure coordinate | Live width (nm) before the etching | Live width after the etching (nm) | CD Bias (nm) (back value-preceding value) |
| (1，3) | 93.9 | 90.6 | -3.3 |
| (4，3) | 94.3 | 91.7 | -2.6 |
| (4，1) | 96.5 | 93.5 | -3.0 |
| (7，3) | 95.1 | 91.9 | -3.2 |
| (4，5) | 94.9 | 92.1 | -2.8 |
The present embodiment test features is the 90nm live width, can reflect the 90nm process results, and is well-known, technology has downward compatibility, in the time of can satisfying high-end 90nm technology, the 130nm of low side, 180nm technology etc. can meet the demands fully, and technological parameter can be adjusted to some extent certainly.
Embodiment 3
According to embodiment 1 described method, difference is, feeds by 30sccmCl main the quarter in the step
2, the mist formed of 130sccm HBr and 30sccm NO, other main step process conditions of carving comprise: chamber pressure 15 millitorrs, last RF power 350W, following RF power 40W, process time control is detected by end-point detecting system and controls.
After gate etching process was finished, test result was found: each point CD Bias＜4.0nm in the sheet, and the CD control ability has clear improvement equally than embodiment 1, and the damage of SiON layer is very little.Main carve the step etch rate raise be 1549 dusts/minute.
Embodiment 4
According to embodiment 1 described method, difference is, feeds by 30sccmCl main the quarter in the step
2, 125sccm HBr and 15sccm N
2O
5The mist of forming, other main step process conditions of carving comprise: chamber pressure 10 millitorrs, last RF power 350W, following RF power 50W, process time control detects control by end-point detecting system.
After gate etching process was finished, test result was found: each point CD Bias＜5nm in the sheet, owing to feed N
2The O amount is less, and the CD control ability only improves than embodiment 1.Main carve the step etch rate be 1525 dusts/minute.
Claims (4)
1. gate etching process, its step comprise and run through the step, mainly carve the step and cross and carve the step, use SiON or SiO in the gate etching process
2/ SiON double-decker is characterized in that as hard mask employed gas is for being selected from N in the described main step at quarter
2O, NO, NO
2, NO
3, N
2O
5In a kind of and Cl
2, HBr mist.
2. technology as claimed in claim 1 is characterized in that employed gas is N in the described main step at quarter
2O and Cl
2, HBr mist.
3. technology as claimed in claim 1 is characterized in that describedly running through that employed gas is CF in the step
4, C
2F
6, Cl
2In a kind of.
4. technology as claimed in claim 1 is characterized in that employed gas is HBr, He and O in the described step at quarter excessively
2Mist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101262657A CN100397590C (en) | 2005-12-02 | 2005-12-02 | Gate etching process |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101262657A CN100397590C (en) | 2005-12-02 | 2005-12-02 | Gate etching process |
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| Publication Number | Publication Date |
|---|---|
| CN1851875A CN1851875A (en) | 2006-10-25 |
| CN100397590C true CN100397590C (en) | 2008-06-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101262657A Active CN100397590C (en) | 2005-12-02 | 2005-12-02 | Gate etching process |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194678B (en) * | 2010-03-11 | 2013-07-24 | 中芯国际集成电路制造(上海)有限公司 | Method for etching grid |
| CN102456078B (en) * | 2010-10-18 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Database for etching rate distribution curves of layer to be etched, and forming and using methods |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07273093A (en) * | 1994-04-01 | 1995-10-20 | Sony Corp | Plasma etching method |
| CN1607651A (en) * | 2003-09-30 | 2005-04-20 | 艾格瑞系统有限公司 | Methods for cleaning processing chambers |
| CN1616367A (en) * | 2004-07-12 | 2005-05-18 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Multicrystal silicon etching process capable of avoiding forming burr on channel bottom |
-
2005
- 2005-12-02 CN CNB2005101262657A patent/CN100397590C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07273093A (en) * | 1994-04-01 | 1995-10-20 | Sony Corp | Plasma etching method |
| CN1607651A (en) * | 2003-09-30 | 2005-04-20 | 艾格瑞系统有限公司 | Methods for cleaning processing chambers |
| CN1616367A (en) * | 2004-07-12 | 2005-05-18 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Multicrystal silicon etching process capable of avoiding forming burr on channel bottom |
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Address after: No. 8, Wenchang Avenue, Beijing economic and Technological Development Zone, 100176 Patentee after: Beijing North China microelectronics equipment Co Ltd Address before: 100016 Jiuxianqiao East Road, Chaoyang District, Chaoyang District, Beijing Patentee before: Beifang Microelectronic Base Equipment Proces Research Center Co., Ltd., Beijing |