JP2005045053A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which a hard mask is used having high etching resistance and fine adhesiveness to a ground layer such as a silicon oxide film and a silicon nitride film and allowed to be easily removed. <P>SOLUTION: The manufacturing method of the semiconductor device comprises a process for stacking an Si-contained amorphous carbon layer of which the Si content is 0.1-10 wt% on a ground layer, a process for forming a photoresist mask on the Si-contained amorphous carbon layer, a process for forming a hard mask by using the photoresist mask as a mask and patterning the Si-contained amorphous carbon layer, and a process for patterning the ground layer by using the hard mask as a mask. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a semiconductor device, and in particular, a semiconductor using a hard mask that has high etch resistance and good adhesion to an underlying layer such as a silicon oxide film or a silicon nitride film and is easy to remove. The present invention relates to a device manufacturing method.

  In manufacturing a semiconductor device such as a DRAM, when forming a pattern such as a through hole on an underlayer such as an interlayer insulating film, a photoresist is applied on the underlayer, and the obtained photoresist film is patterned. The underlying layer is etched using as a mask. In recent years, with the miniaturization of semiconductor devices, it is required to form fine patterns.

  In order to form a fine pattern, it is necessary to increase the resolution of the pattern. To that end, it is necessary to reduce the film thickness of the photoresist film from the viewpoint of the depth of focus during exposure. However, when the film thickness of the photoresist film is reduced, the etch resistance is lowered and the function as a mask may not be achieved. Therefore, instead of etching using a photoresist mask, a hard mask having a high etch selectivity with the underlying layer is provided between the photoresist layer and the underlying layer, and the pattern of the photoresist mask is once transferred to the hard mask. Further, a method of patterning the underlayer using a hard mask as a mask is used.

  As a material for the hard mask, silicon oxide, silicon nitride, or the like having a large etch selectivity with respect to the base layer is used. However, when such a hard mask is used, a necessary etch selectivity cannot be obtained if the underlying layer includes a silicon oxide film or a silicon nitride film. Therefore, as hard masks for obtaining etch selectivity for these films, Patent Documents 1 to 3 propose using amorphous carbon, and Patent Document 3 further using polysilicon and amorphous silicon as hard masks. . A hard mask made of amorphous carbon is a preferable hard mask particularly in the sense that it can be easily removed (stripped).

However, it is difficult for a hard mask made of amorphous carbon to obtain an etch selectivity with a photoresist film containing carbon as a main component. Therefore, Patent Documents 1 and 2 adopt a process in which an intermediate layer is further interposed between the hard mask and the photoresist film, and the pattern of the photoresist mask is once transferred to the intermediate layer and then transferred to the hard mask. is doing. This intermediate layer also functions as an antireflection film, and suppresses light reflection from the underlayer when the photoresist film is exposed to increase the pattern resolution.
JP 2002-12972 (paragraph 0013) JP 2002-194547 A (paragraph 0013) JP 10-56080 (paragraph 0025)

  By the way, in a recent DRAM manufactured based on a fine design rule of less than 0.11 μm, when forming a cylindrical storage electrode of a capacitor, a deep hole having a depth exceeding 3 μm is formed as a through hole in the base layer. It may be necessary to open a deep hole exceeding 4 μm. Such deep hole opening is necessary, for example, for reducing crosstalk between wirings accompanying the miniaturization of patterns.

  In fine design rules, the self-alignment contact technology is often used. In the self-alignment contact technology, a thick etching stopper film such as a nitride film called a cap is provided on the gate electrode or the digit line, and etching is performed on the cap. Etching to stop automatically. Therefore, a DRAM having a design rule of less than 0.11 μm has sufficient etch resistance to withstand deep hole opening in a base layer including a silicon oxide film and a silicon nitride film and patterning using a thick nitride film as a cap. A hard mask is required.

  When the present inventor used amorphous carbon as a hard mask, it was found that this hard mask has a problem that the etching resistance cannot be sufficiently ensured in patterning with a design rule lower than 0.11 μm. This problem is particularly prominent when the pattern width is 0.09 μm or less, and has occurred in patterning a portion where deep holes and lines having a large aspect ratio are dense. In this case, if the thickness of the hard mask is increased, the etch resistance is improved, but new problems such as a decrease in throughput, an increase in manufacturing cost, a variation in processing dimensions, and a fall of the line pattern occur.

  Further, according to the experiments by the present inventors, the amorphous carbon film has insufficient adhesion to the silicon oxide film or the silicon nitride film, and the amorphous carbon film is formed from the amorphous carbon formed on the base layer made of the silicon oxide film or the silicon nitride film. It has been found that the mask pattern easily collapses even with the same aspect ratio as the mask made of other materials, and a good yield of the semiconductor device cannot be obtained.

  On the other hand, although the hard mask made of amorphous silicon has relatively good etch resistance, it is difficult to remove from the underlying layer after etching, and extra steps may increase due to the removal of the hard mask. understood.

  In view of the above, the present invention provides a semiconductor device that performs patterning on a base layer such as a silicon oxide film or a silicon nitride film using a hard mask that has high etch resistance and good adhesion and is easy to remove. It aims at providing the manufacturing method of.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the first aspect of the present invention includes a step of depositing a Si-containing amorphous carbon layer on a base layer,
Forming a photoresist mask on the Si-containing amorphous carbon layer;
Patterning the Si-containing amorphous carbon layer using the photoresist mask as a mask to form a hard mask;
And a step of patterning the underlayer using the hard mask as a mask.

The method for manufacturing a semiconductor device according to the second aspect of the present invention includes a step of sequentially depositing a Si-containing amorphous carbon layer and an intermediate layer on a base layer,
Forming a photoresist mask on the intermediate layer;
Patterning the intermediate layer using the photoresist mask as a mask to form an intermediate mask;
Patterning the Si-containing amorphous carbon layer using the intermediate mask as a mask to form a hard mask;
And a step of patterning the underlayer using the hard mask as a mask.

  According to the method for manufacturing a semiconductor device according to the first aspect of the present invention, a silicon oxide film or a silicon nitride film is obtained by using, as a hard mask, Si-containing amorphous carbon having a high etch selectivity with respect to a silicon oxide film or a silicon nitride film. Good etch resistance can be ensured for the formation of deep holes in the underlayer such as the above and patterning using a thick nitride film as a cap. Further, by using a hard mask made of Si-containing amorphous carbon, it is possible to facilitate removal of the hard mask from the underlayer as compared with a hard mask made of amorphous silicon.

  Furthermore, since Si-containing amorphous carbon has good adhesion to a silicon oxide film or a silicon nitride film, the pattern collapse of the hard mask pattern formed on the base layer made of these films is suppressed, and the semiconductor device Yield can be improved. Therefore, a large aspect ratio can be adopted even in a fine pattern. Further, when oxygen is added to the etching gas, oxygen and a hard mask made of Si-containing amorphous carbon react to form an oxide film on the surface of the hard mask, so that side etching of the hard mask can be suppressed. . Therefore, a hard mask with little dimensional variation can be obtained, and thereby a fine pattern with high dimensional accuracy can be formed.

  The hard mask made of Si-containing amorphous carbon used in the present invention can manufacture a semiconductor device that forms a fine and high-density pattern, which is difficult to apply with a conventional hard mask made of amorphous carbon or the like.

  Incidentally, when the Si-containing amorphous carbon layer has a low Si content, the etch selectivity with respect to the photoresist film is lowered. Therefore, in the method for manufacturing a semiconductor device according to the second aspect of the present invention, an intermediate layer having a high etch selectivity between the Si-containing amorphous carbon layer and the photoresist film is provided between the Si-containing amorphous carbon layer and the photoresist layer. By interposing, the pattern of the photoresist mask can be accurately transferred to the hard mask through the intermediate mask.

  In the present invention, preferably, the intermediate layer has a light reflection preventing function. Thereby, when performing exposure to the photoresist film, light reflection from an underlayer or the like can be suppressed, and a photoresist mask having higher resolution can be obtained.

  In the present invention, it is preferable that the intermediate layer includes at least one of a silicon oxide layer and a silicon oxynitride layer. In the present invention, it is preferable that the intermediate layer includes a silicon oxynitride layer having a thickness of 50 nm or less and a silicon oxide layer having a thickness of 20 nm to 60 nm formed on the silicon oxynitride layer. . Good effects can be obtained.

  In a preferred embodiment of the present invention, the intermediate layer includes at least one other Si-containing amorphous carbon layer. In this case, after depositing the Si-containing amorphous carbon layer constituting the hard mask, by changing the Si content rate, it can be continuously deposited in the same chamber, so the number of steps can be reduced.

  In the present invention, preferably, the Si content of the other Si-containing amorphous carbon layer is in the range of 20 wt% to 80 wt%. Since the Si-containing amorphous carbon layer having a Si content in the range of 20 wt% to 80 wt% has a high etch selectivity with respect to the Si-containing amorphous carbon layer and the photoresist layer having a low Si content, the intermediate layer It can be suitably applied to.

In a preferred embodiment of the present invention, the Si content of the Si-containing amorphous carbon layer is in the range of 0.1 wt% to 10.0 wt%. When the Si content of the Si-containing amorphous carbon layer is 0.1% by weight or more, a better etch selectivity can be obtained between the Si-containing amorphous carbon and the silicon oxide film or silicon nitride film. Therefore, sufficient etch resistance can be ensured even in the manufacturing process of a semiconductor device whose design rule is less than 0.11 μm. Further, when the Si content of the Si-containing amorphous carbon layer is 10.0% by weight or less, the hard mask made of Si-containing amorphous carbon can be easily removed without substantially affecting the shape of the underlayer. I can do it. Such a hard mask can be easily removed by, for example, ashing in which a plasma such as a fluorocarbon-based gas, ammonia, or NF ₃ is added to oxygen plasma.

  In a preferred embodiment of the present invention, the Si content of the Si-containing amorphous carbon layer is in the range of 0.1 wt% to 5.0 wt%. When the Si content of the Si-containing amorphous carbon layer is 5.0% by weight or less, the hard mask made of Si-containing amorphous carbon can be easily removed by ashing using only ordinary oxygen plasma.

In a preferred embodiment of the present invention, prior to the step of depositing the Si-containing amorphous carbon layer, an amorphous carbon layer is deposited on the underlayer,
In the step of forming the hard mask, the Si-containing amorphous carbon layer and the amorphous carbon layer are simultaneously patterned to form the hard mask.

  Amorphous carbon is easier to remove from a base layer made of a silicon oxide film or a silicon nitride film than Si-containing amorphous carbon. Therefore, the hard mask can be easily removed by setting the film thickness such that only amorphous carbon remains after etching using the hard mask. In this case, the Si-containing amorphous carbon layer can be continuously deposited in the same chamber by changing the Si content after depositing the amorphous carbon layer.

  In a preferred embodiment of the present invention, the Si-containing amorphous carbon layer is deposited by plasma enhanced chemical vapor deposition using a mixed gas containing a hydrocarbon compound gas and a silicon compound gas. This is a preferred mode of depositing a Si-containing amorphous carbon layer.

In the present invention, preferably, the hydrocarbon compound gas is methane (CH ₄ ), ethane (C ₂ H ₆ ), propane (C ₃ H ₈ ), butane (C ₄ H ₁₀ ), acetylene (C ₂ H). ₂ ), propylene (C ₃ H ₆ ), and propyne (C ₃ H ₄ ). In the present invention, it is preferable that the silicon compound gas includes at least one of monosilane (SiH ₄ ), disilane (Si ₂ H ₆ ), and tetramethylsilane (Si (CH ₃ ) ₄ ). In the present invention, it is preferable that the mixed gas further includes at least one of helium (He) and argon (Ar).

  In a preferred embodiment of the present invention, the Si-containing amorphous carbon layer is deposited using a parallel plate type plasma CVD apparatus or a high density plasma CVD apparatus. Compared with a parallel plate type plasma CVD apparatus, the high density plasma CVD apparatus has a feature that a high density plasma can be obtained under a low pressure and the decomposition efficiency of the source gas is high. Therefore, at the same Si content, deposit an Si-containing amorphous carbon layer that obtains a higher etch selectivity for a silicon oxide film or a silicon nitride film than an Si-containing amorphous carbon layer deposited by a parallel plate plasma CVD apparatus. Can do.

In a preferred embodiment of the present invention, all or a part of the Si-containing amorphous carbon layer is removed by a plasma containing at least one of oxygen plasma, ammonia plasma, and fluorocarbon plasma. In a preferred embodiment of the present invention, all or part of the Si-containing amorphous carbon layer is a plasma containing at least one of CF ₄ plasma, C ₂ F ₆ plasma, and C ₃ F ₈ plasma. Removed. When the Si content of the Si-containing amorphous carbon is high, the Si-containing amorphous carbon can be easily removed by using oxygen plasma and ammonia plasma or fluorocarbon plasma in combination.

  Hereinafter, with reference to the drawings, the present invention will be described in more detail based on exemplary embodiments according to the present invention.

First Embodiment FIG. 1 is a cross-sectional view showing a configuration of a parallel plate plasma CVD apparatus used for deposition of Si-containing amorphous carbon in the first embodiment. The parallel plate type plasma CVD apparatus 400 includes a plate-type reactor 401. The reactor 401 includes a deposition chamber 402, a wafer susceptor 403 that holds a semiconductor substrate (wafer) 422, a showerhead-type electrode 404 having a large number of holes through which a mixed gas passes, and a gas diffusion plate 405 that diffuses the mixed gas. An insulating ring 410 is provided between the showerhead type electrode 404 and the deposition chamber 402. The wafer susceptor 403 also functions as a lower electrode corresponding to the shower head type electrode 404 as an upper electrode, and is grounded.

  The deposition chamber 402 includes a gas nozzle 406 that supplies a mixed gas into the deposition chamber 402, an exhaust chamber 407 from which the reacted gas is temporarily exhausted, an exhaust line 408 that exhausts the gas in the exhaust chamber 407 to the outside, and a semiconductor substrate. A gate valve 409 for taking in and out 422 is provided. The exhaust line 408 includes a pressure regulating valve (not shown) and regulates the pressure in the deposition chamber 402 to a predetermined pressure. The wafer susceptor 403 has a built-in heater and can be moved up and down with the semiconductor substrate 422 placed thereon. When depositing on the semiconductor substrate 422, the wafer susceptor 403 is set at the deposition position shown in FIG. At this time, it is set at a wafer transfer position (not shown).

  The parallel plate type plasma CVD apparatus 400 includes a carbon source gas line (CSL) 411, a silicon source gas line (SSL) 412, and a carrier gas line (CL) as gas supply systems connected to the gas nozzle 406. 413. The CSL 411, SSL 412, and CL 413 are provided on the gas nozzle 406 side with respect to the mass flow controllers (MFC) 414, 415, and 416 that are connected to the respective gas sources and adjust the flow rate of the gas, and these MFCs 414, 415, and 416. Gas valves 417, 418, and 419, respectively.

  The gas supplied from the CSL 411, SSL 412, and CL 413 is mixed before reaching the gas nozzle 406, and after passing through the gas nozzle 406, is diffused by the gas diffusion plate 405 so as to be evenly distributed throughout the shower head type electrode 404. The light is supplied onto the semiconductor substrate 422 through a large number of holes provided in the shower head type electrode 404. By adjusting the partial pressures of CSL411, SSL412, and CL413, films having various composition ratios of silicon (Si), carbon (C), and hydrogen (H) can be formed. In this embodiment, the holes of the showerhead-type electrode 404 are straight holes with respect to the gas passage direction. However, if a conical hole is used, the decomposition efficiency by gas plasma can be further increased.

  A high-frequency power source 420 capable of supplying 13.56 MHz power and a low-frequency power source 421 capable of supplying 400 KHz power, which are electrically connected to the shower head type electrode 404, are provided. Supply power for plasma excitation. The other ends of the high-frequency power source 420 and the low-frequency power source 421 are grounded.

  In order to deposit Si-containing amorphous carbon using the parallel plate type plasma CVD apparatus 400, the following process is performed. First, the semiconductor substrate 422 is inserted into the reactor 401 from the gate valve 409, placed on the wafer susceptor 403 at the wafer transfer position, and then the wafer susceptor 403 is set at the deposition position. Subsequently, the semiconductor substrate 422 is heated to 300 ° C. to 560 ° C. by a heater built in the wafer susceptor 403. In the present embodiment example, heating is performed to 540 ° C.

Next, by operating the gas supply system, while supplying a predetermined flow rate of the mixed gas from the gas nozzle 406 into the deposition chamber 402, the pressure adjustment valve is controlled to adjust the inside of the deposition chamber 402 to a predetermined pressure. In this embodiment, methane (CH ₄ ) is used as the carbon source gas supplied from the CSL 411, monosilane (SiH ₄ ) is used as the silicon source gas supplied from the SSL 412, and He is used as the carrier gas supplied from the CL 413. Each was used. The pressure in the deposition chamber 402 can be set in the range of 1 torr to 10 torr, but in this embodiment, it is set to 4 torr in order to maintain the uniformity of the film thickness.

As carbon source gas, in addition to methane, ethane (C ₂ H ₆ ), propane (C ₃ H ₈ ), butane (C ₄ H ₁₀ ), acetylene (C ₂ H ₂ ), propylene (C ₃ H ₆₎ ), Hydrocarbon compounds such as propyne (C ₃ H ₄ ), and mixtures thereof. These gases are gases used in the conventional process of depositing amorphous silicon.

As the silicon source gas, in addition to monosilane, silicon compound gas such as disilane (Si ₂ H ₆ ), tramethylsilane (Si (CH ₃ ) ₄ ), and a mixture thereof can be used. As the carrier gas, an inert gas such as helium (He) or argon (Ar) can be used.

When the pressure in the deposition chamber is stabilized and the temperature of the semiconductor substrate 422 reaches a predetermined temperature, power is supplied between the shower head type electrode 404 and the wafer susceptor 403 using the high frequency power source 420 and the low frequency power source 421. , Generate plasma. Thereby, deposition of Si-containing amorphous carbon is started on the semiconductor substrate 422. At this time, the high frequency power source, set in the range of ^{0.5W / cm 2 ~3.5W / cm 2} , preferably set in a range of ^{2.0W / cm 2 ~2.5W / cm 2} . Low-frequency power source is set in the range of ^{0.5W / cm 2 ~2.0W / cm 2} , preferably set in a range of ^{1.0W / cm 2 ~1.5W / cm 2} .

  When the Si-containing amorphous carbon layer reaches a desired film thickness, the power supply from the high-frequency power source 420 and the low-frequency power source 421 is stopped, and then the supply of the mixed gas from the gas supply system is stopped to complete the deposition. To do. Finally, the wafer susceptor 403 is lowered to the wafer transfer position, and the semiconductor substrate 422 is taken out from the gate valve 409.

  The Si-containing amorphous carbon layer deposited by the parallel plate type plasma CVD apparatus in the present embodiment has a high etch selectivity with respect to the silicon oxide film or the silicon nitride film, and is good for the silicon oxide film or the silicon nitride film. Has good adhesion. In addition, removal from a silicon oxide film or a silicon nitride film is easier than amorphous silicon. Furthermore, when etching the underlayer using the Si-containing amorphous carbon layer as a hard mask, if oxygen is added to the etching gas, the oxygen and the Si-containing amorphous carbon react to form an oxide film on the surface. The side etching of the hard mask can be suppressed.

  By the way, when Si-containing amorphous carbon is deposited on the semiconductor substrate 422 as described above, Si-containing amorphous carbon is also deposited on the inner wall of the deposition chamber 402. If the Si-containing amorphous carbon layer deposited on the inner wall of the deposition chamber 402 is left as it is, the Si-containing amorphous carbon layer is peeled off on the semiconductor substrate 422 due to stress in the layer and becomes particles, thereby deteriorating the yield of the semiconductor device. Therefore, it is preferable to periodically perform cleaning to remove Si-containing amorphous carbon deposited on the inner wall of the deposition chamber 402.

  Conventionally, when amorphous carbon is deposited on the semiconductor substrate 422, the amorphous carbon deposited on the inner wall of the deposition chamber 402 can be removed by a known method using oxygen plasma or the like. In the present embodiment, the Si-containing amorphous carbon can be removed using oxygen plasma in the same manner as the amorphous carbon when the Si content is low. In this case, it is preferable to perform cleaning every time after the deposition of the Si-containing amorphous carbon or once every several depositions.

On the other hand, when the Si content of the Si-containing amorphous carbon increases, it is difficult to remove it with only oxygen plasma. In this case, when NF ₃ or fluorocarbon gas excited by remote plasma is used in combination, it can be efficiently removed. For supplying these gases, a cleaning gas line (not shown) can be used.

Experimental example 1
The present inventors performed etching on the silicon oxide film using a hard mask made of Si-containing amorphous carbon, and conducted an experiment to investigate the relationship between the Si content of Si-containing amorphous carbon and the etch selectivity, and FIG. The result shown by (circle) in the graph of a) and (b) was obtained. FIG. 2B is a graph in which the horizontal axis of the graph of FIG.

Here, etch selectivity is
Etch selectivity = (etch rate of work material) / (hard mask etch rate)
The higher the etch selectivity, the higher the resistance of the mask to etching. In this experimental example, the material to be processed is silicon oxide.

  As can be seen from FIG. 2A, the etch selectivity increases as the Si content of the Si-containing amorphous carbon layer increases from 0% by weight, and becomes maximum when the Si content is 50% by weight to 80% by weight. Thereafter, it rapidly decreases, and in the case of amorphous silicon having a Si content of 100% by weight, it decreases to a level that is not significantly different from the etch selectivity of amorphous carbon. Further, as can be seen from FIG. 2B, the etch selectivity increases by adding silicon, but there is almost no difference from the amorphous carbon layer if it is less than 0.1% by weight.

  From the viewpoint of the etch selectivity, the Si content is most preferably in the range of 50 wt% to 80 wt%. However, when the Si content of the Si-containing amorphous carbon layer exceeds about 10% by weight, removal becomes difficult. Therefore, by setting the Si content in the Si-containing amorphous carbon layer to 0.1 wt% or more and 10 wt% or less, the Si-containing amorphous carbon layer has a high etch selectivity with respect to the silicon oxide film and can be easily removed. Can be obtained.

Second Embodiment FIG. 3 is a cross-sectional view showing a configuration of a high-density plasma CVD apparatus used for deposition of Si-containing amorphous carbon in a second embodiment of the present invention. High-density plasma CVD devices include inductive coupling type, electron cyclotron resonance (ECR) type, and helicon wave type depending on the plasma source, all of which can produce high-density plasma under a low pressure of several mtorr. It has the feature of high gas decomposition efficiency. In addition, a highly dense film can be deposited by having a bias power source for drawing the decomposed and ionized source gas into the semiconductor substrate. For this reason, conventionally, it has been used as a means for improving the gap filling property of the silicon oxide film.

The high-density plasma CVD apparatus 500 is an inductively coupled high-density plasma CVD apparatus, and includes a sheet-type reactor 501. The reactor 501 includes a wafer susceptor 502 that holds a semiconductor substrate 529, a ceramic dome 503 that covers the wafer susceptor 502 and is made of alumina (Al ₂ O ₃ ), and a coiled electrode provided outside the ceramic dome 503. 504. Wafer susceptor 502 incorporates an electrostatic induction chuck (ESC) (not shown). Further, the semiconductor substrate 529 can be moved up and down, and when depositing on the semiconductor substrate 529, the deposition position shown in the figure is set, and when the semiconductor substrate 529 is taken in and out of the reactor 501, Set at a wafer transfer position (not shown).

  The reactor 501 further performs exhaust of two gas nozzles, a first gas nozzle 505 provided on the ceramic dome 503 and a second gas nozzle 506 provided on the ceramic dome 503 so as to surround the upper portion of the wafer susceptor 502. An exhaust line 507 and a gate valve 508 for taking in and out the semiconductor substrate 529 are provided. The exhaust line 507 includes a turbo molecular pump (not shown), and the inside of the reactor 501 can be controlled to a predetermined pressure by exhausting a predetermined flow rate of gas.

  The high-density plasma CVD apparatus 500 has a first gas supply system connected to the first gas nozzle 505 and a second gas supply system connected to the second gas nozzle 506. The first gas supply system includes a first CSL 509, a first SSL 510, and a first CL 511, and includes first MFCs 512, 513, and 514 and first gas valves 515, 516, and 517, respectively. The second gas supply system 506 includes a second CSL 518, a second SSL 519, and a second CL 520, and includes second MFCs 521, 522, and 523, and second gas valves 524, 525, and 526, respectively.

Each of the first gas supply system and the second gas supply system has the same configuration as the gas supply system of the first embodiment. By adjusting the gas flow rate ratio between the first gas supply system and the second gas supply system, the uniformity of the film thickness of the deposited Si-containing amorphous carbon can be adjusted.

  The coiled electrode 504 is connected to a first high frequency power supply 527 that can supply power of 2 MHz. The first high frequency power supply 527 supplies power to the coiled electrode 504 to generate high-density plasma in the deposition chamber by inductive coupling. Can be generated. The wafer susceptor 502 is connected to a second high frequency power source 528 capable of supplying a high frequency power of 13.56 MHz. The second high frequency power source 528 supplies the high frequency power to the wafer susceptor 502 and the plasma generated by inductive coupling and the wafer susceptor. During 923, a bias is applied, and ions that are dissociated into plasma can be induced to the substrate surface. The other ends of the first high frequency power supply 527 and the second high frequency power supply 528 are grounded.

  The Si-containing amorphous carbon layer is deposited using the high-density plasma CVD apparatus 500 as follows. First, the semiconductor substrate 529 is inserted into the reactor 501 from the gate valve 508 and placed on the wafer susceptor 502 at the wafer transfer position, and then the wafer susceptor 502 is raised and set at a predetermined deposition position. At this time, when the temperature of the semiconductor substrate 529 at the time of reaction is desired to be 400 ° C. or lower, the semiconductor substrate 529 is chucked by an electrostatic induction chuck with a built-in wafer susceptor 502, and the semiconductor substrate 529 is heated by heat conduction from the back surface. Prevent the temperature from rising. When the semiconductor substrate 529 is chucked, the temperature of the semiconductor substrate 529 is controlled by the pressure of He flowing from a gas nozzle (not shown) between the back surface of the semiconductor substrate 529 and the wafer susceptor 502.

  Next, while supplying a mixed gas at a predetermined flow rate from the first gas supply system and the second gas supply system, exhaust is performed by the turbo molecular pump in the exhaust line 507, and the inside of the reactor 501 is controlled to have a predetermined pressure. . The pressure in the reactor 501 can be set in a range of 1 mtorr to 10 mtorr, but is set to 6 mtorr in this embodiment. When the pressure in the reactor 501 is stabilized, a high frequency power of 2 MHz is applied from the first high frequency power supply 527 to the coiled electrode 504, and a high frequency power of 13.56 MHz is applied from the second high frequency power supply 528 to the wafer susceptor 502. The deposition of Si-containing amorphous carbon is started on the substrate 529.

  In an apparatus corresponding to an 8-inch wafer, the power of the first high-frequency power source 527 is set in the range of 1000 W to 4000 W, preferably in the range of 1500 W to 3500 W. The power of the second high frequency power supply 528 is set in the range of 0 W to 4000 W, preferably in the range of 1000 W to 3500 W.

  When the film thickness of the Si-containing amorphous carbon layer reaches a desired film thickness, the power supply from the first high-frequency power source 527 and the second high-frequency power source 528 is stopped, and then from the first gas supply system and the second gas supply system The supply of the mixed gas is stopped and the deposition is finished. Finally, the wafer susceptor 502 is lowered to a predetermined wafer transfer position, and the semiconductor substrate 529 is taken out from the gate valve 508.

  According to the present embodiment example, in addition to the effects of the first embodiment example, the Si-containing amorphous carbon layer deposited by the high-density plasma CVD apparatus in the present embodiment example is the parallel plate type plasma of the first embodiment example. It has a higher etch selectivity with respect to a silicon oxide film or a silicon nitride film than a Si-containing amorphous carbon layer deposited by a CVD apparatus.

Experimental example 2
As in the case of Experimental Example 1, the inventor performed etching on the silicon oxide film using a hard mask made of Si-containing amorphous carbon, and the relationship between the Si content of the Si-containing amorphous carbon layer and the etch selectivity. An experiment was conducted to obtain a result indicated by Δ in the graphs of FIGS. 2 (a) and 2 (b).

  As can be seen from these figures, when the deposition is performed using the high-density plasma CVD apparatus 500, a higher etch selectivity with respect to the silicon oxide film can be obtained than when the deposition is performed using the parallel plate type plasma CVD apparatus 400. . Also in the case of this experimental example, as shown in FIG. 2B, when the Si content is about 0.1% by weight or more, the difference in etch selectivity is sufficiently larger than that of the amorphous silicon layer. In this embodiment, the inductively coupled high-density plasma CVD apparatus is used. However, the same effect can be obtained by using an ECR type or helicon wave type high-density plasma CVD apparatus. In Experimental Example 1 and Experimental Example 2, the etch selectivity between the Si-containing amorphous carbon layer and the silicon oxide film was examined. It seems that the same effect can be obtained between the film and the nitride film.

Third Embodiment FIG. 4A to FIG. 6E are cross-sectional views showing stepwise a method for manufacturing a semiconductor device according to a third embodiment of the present invention. The third embodiment is an example in which the present invention is applied to the opening of a through hole having a high aspect ratio. Processing of a silicon oxide film, contact hole, and opening of a through hole in a cylinder type capacitor of a DRAM are performed. It can be applied to holes and the like.

  First, an element such as a transistor is formed on the semiconductor substrate 101, and then a base layer 102 is deposited thereon. The underlayer 102 is a silicon oxide film, for example, and can be deposited using a known method such as a plasma chemical vapor deposition method. Next, an Si-containing amorphous carbon layer 103 having a Si content of 0.1 wt% to 10 wt% is deposited on the underlayer 102 according to the method described in the first embodiment or the second embodiment. The film thickness of the Si-containing amorphous carbon layer 103 can be appropriately set according to the film thickness of the underlayer 102 and the like, but when etching the underlayer 102 having the same film thickness, the film thickness of the amorphous silicon layer is 25. % To 50% can be set.

Next, an intermediate layer 110 made of a silicon oxynitride (SiON) film 104 having a thickness of 15 nm and a silicon oxide (SiO ₂ ) film 105 having a thickness of 30 nm formed on the silicon oxynitride film 104 is deposited. The intermediate layer 110 functions as an intermediate mask for patterning the Si-containing amorphous carbon layer 103 and also functions as an antireflection film.

  In this embodiment, the refractive index n and the absorption coefficient k of the silicon oxynitride film 104 are n = 1.96 and k = 0.30 with respect to the wavelength of 248 nm. The refractive index n and absorption coefficient k of the silicon oxide film 105 are n = 1.46 and k = 0.00 with respect to the wavelength of 248 nm. In the case where the function of the antireflection film is unnecessary, a single-layer silicon oxide film can be deposited instead of the intermediate layer 110. In this case, it is preferable to set the film thickness of the silicon oxide film in a range where there is little dimensional variation due to the influence of the optical multiple interference effect in the lithography process.

  Next, after applying a photoresist, a pattern is exposed, developed and transferred to the obtained photoresist layer to form a photoresist mask 106 (FIG. 4A). During the patterning, the intermediate layer 110 functions as an antireflection film. Next, as shown in FIG. 4B, using the photoresist mask 106 as a mask, the intermediate layer 110 is etched using an anisotropic dry etching method, and the pattern of the photoresist mask 106 is transferred to the intermediate layer 110. .

Subsequently, as shown in FIG. 5C, the Si-containing amorphous carbon layer 103 is patterned using an anisotropic dry etching method using the patterned intermediate layer 110 as an intermediate mask. If an SiO ₂ -based residue appears during this patterning, a fluorocarbon-based gas such as CF ₄ , C ₂ F ₆ , or C ₃ F ₈ or a mixture thereof is added to the etching gas. However, if these gases are added in a large amount, the etch selectivity between the intermediate layer 110 and the Si-containing amorphous carbon layer 103 is lowered. Therefore, it is preferable to add a small amount.

  Since the photoresist mask 106 has a higher etch rate than the Si-containing amorphous carbon layer 103, when the thickness of the Si-containing amorphous carbon layer 103 is appropriate, the intermediate mask 110 is formed when the patterning of the Si-containing amorphous carbon layer 103 is completed. Almost no upper photoresist mask 106 remains. If a small amount remains, it is completely removed in the next etching step.

  Next, as shown in FIG. 5D, the underlying layer 102 is etched using the patterned Si-containing amorphous carbon layer 103 as a hard mask.

  Next, as shown in FIG. 6E, the Si-containing amorphous carbon layer 103 is removed. When the Si content of the Si-containing amorphous carbon layer 103 does not exceed about 5.0% by weight, the Si-containing amorphous carbon layer 103 can be removed by ashing using normal oxygen plasma, as in the case of amorphous carbon.

When the Si content of the Si-containing amorphous carbon layer 103 exceeds 5.0% by weight, it is difficult to remove by ashing using only oxygen plasma, so ashing is performed by adding a fluorocarbon-based gas. Thereby, the Si-containing amorphous carbon layer 103 can be efficiently removed. As the fluorocarbon-based gas, CF ₄ , C ₂ F ₆ , C ₃ F ₈ , or a mixture thereof can be used.

  If the Si content of the Si-containing amorphous carbon layer 103 exceeds 10% by weight, it is difficult to remove the Si-containing amorphous carbon layer 103 even if a fluorocarbon-based gas plasma is added to the oxygen plasma as described above. is there. In this case, if the amount of fluorocarbon-based gas added is increased in an attempt to force removal, the material to be processed is etched thereby affecting its shape.

  According to the present embodiment example, in addition to the effects of the first embodiment example or the second embodiment example, the Si content of the Si-containing amorphous carbon layer 103 is set to 0.1 wt% to 10 wt%. Even in the manufacture of a semiconductor device having a design rule of less than 0.11 μm, a hard mask that has sufficient etch resistance and can be easily removed can be obtained.

  Conventionally, when a deep hole is to be formed in a silicon oxide film, a phenomenon called etch stop may occur. Etch stop is a condition in which fluorocarbon-based polymer is likely to be deposited to protect the sidewall of the silicon oxide film during etching, but the original etching stops due to excessive deposition of this polymer. Say. In order to prevent etch stop, oxygen may be added to the etching gas. However, when a hard mask made of amorphous carbon is used, this oxygen makes it easier for side etching of the hard mask to enter, and the hard mask pattern. However, there is a problem in the dimensional controllability because it spreads more than the pattern formed by lithography.

  However, if the Si-containing amorphous carbon of the present embodiment is used for the hard mask, this oxygen and silicon in the Si-containing amorphous carbon react to form an oxide film, thereby suppressing the side etch of the hard mask. it can.

Fourth Embodiment FIGS. 7A to 9F are cross-sectional views showing stepwise a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. The present embodiment is an example of an embodiment in which the present invention is applied to the formation of a line system pattern composed of a line pattern and a space. In this embodiment, formation of a digit line or bit line of a DRAM and formation of a contact by a self-alignment contact method will be described. The gate electrode and the like can be formed in the same manner as in this embodiment.

  First, a silicon oxide film 201 is formed on a semiconductor substrate 220 on which elements such as transistors and conductive plugs 221 are formed. Next, a tungsten nitride (WN) 202 having a thickness of 10 nm, a tungsten (W) 203 having a thickness of 70 nm, and a silicon nitride film 204 having a thickness of 180 nm are sequentially formed. Next, the Si-containing amorphous carbon layer 205 having a Si content of 0.1 wt% to 10 wt% is deposited according to the deposition method shown in the first embodiment or the second embodiment. Subsequently, an intermediate layer 210 including a silicon oxynitride film 206 having a thickness of 15 nm and a silicon oxide film 207 having a thickness of 30 nm formed on the silicon oxynitride film 206 is deposited.

  The intermediate layer 210 functions as an intermediate mask for patterning the Si-containing amorphous carbon layer 205 and also functions as an antireflection film. In this embodiment, the refractive index n and the absorption coefficient k of the silicon oxynitride film 206 are n = 1.96 and k = 0.30 with respect to the wavelength of 248 nm. The refractive index n and absorption coefficient k of the silicon oxide film 207 are n = 1.46 and k = 0.00 with respect to the measurement wavelength of 248 nm. If the function as an antireflection film is unnecessary, a single-layer silicon oxide film can be deposited instead of the intermediate layer 110. In this case, it is preferable to set the film thickness of the silicon oxide film in a range where there is little dimensional variation due to the influence of the optical multiple interference effect in the lithography process.

  Next, after applying a photoresist, a pattern is exposed to the obtained photoresist layer, developed, and transferred to form a photoresist mask 208 (FIG. 7A). During this patterning, the intermediate layer 210 functions as an antireflection film. Next, as shown in FIG. 7B, using the photoresist mask 208 as a mask, the intermediate layer 210 is etched using an anisotropic dry etching method, and the pattern of the photoresist mask 208 is transferred to the intermediate layer 210. To do.

Subsequently, as shown in FIG. 8C, using the intermediate layer 210 as an intermediate mask, the Si-containing amorphous carbon layer 205 is etched with an etching gas containing argon and oxygen plasma, and the pattern formed in the intermediate layer 210 is formed. Transferred to the Si-containing amorphous carbon layer 205. If SiO ₂ residue is generated during the patterning, a fluorocarbon gas such as CF ₄ , C ₂ F ₆ , or C ₃ F ₈ , or a mixture thereof is added to the etching gas.

  Next, as shown in FIG. 8D, the silicon nitride film 204, the tungsten film 203, and the upper portion of the tungsten nitride film 202 are etched using the Si-containing amorphous carbon layer 205 to which the pattern has been transferred as a hard mask. Next, as shown in FIG. 9E, the Si-containing amorphous carbon layer 205 is removed by ashing. Oxygen and argon plasma is used for ashing, but if it is difficult to remove, a little fluorocarbon gas is added.

  Next, as shown in FIG. 9F, a silicon nitride film is deposited on the entire surface and etched back to leave sidewalls on the sidewalls of the silicon nitride film 204, the tungsten film 203, and the tungsten nitride film 202. Then, a spacer 209 for self-alignment contact is formed.

  Subsequently, as shown in FIG. 10G, an interlayer insulating film 211 is formed, and a conductive contact plug 212 is formed using a self-aligned contact method. The hole forming method described in the third embodiment can be applied to the contact plug 212 as it is.

  Conventionally, in the formation of a line pattern, a pattern formed on a hard mask made of amorphous silicon tends to collapse, and a pattern with a high aspect ratio cannot be formed. In this embodiment, since the hard mask 205 made of Si-containing amorphous carbon has good adhesion to the silicon nitride film 204, the pattern is difficult to collapse, the pattern collapse margin is large, and the line pattern having a high aspect ratio. Can be formed. The increase in the pattern collapse margin is particularly advantageous when processing a line pattern having a design rule of about 0.1 μm.

  As an example, when the present inventor conducted an experiment in which a hard mask was applied to a 0.11 μm rule gate process using an 8-inch wafer, 226 pattern collapse defects were detected in the hard mask made of amorphous carbon. On the other hand, in the hard mask made of Si-containing amorphous carbon having a Si content of 5.0% by weight, only three defects due to pattern collapse were detected, and the number thereof was drastically reduced.

  In this embodiment, the silicon nitride film 204, the tungsten film 203, and the tungsten nitride film 202 are etched using the Si-containing amorphous carbon layer 205 as a hard mask. However, the tungsten film 203 and the tungsten nitride film 202 are etched using carbon. Sometimes you want to do it in the absence of In that case, first, after etching the silicon nitride film 204, the Si-containing amorphous carbon layer 205 is removed by ashing, and the upper portions of the tungsten film 203 and the tungsten nitride film 202 are etched using the silicon nitride film 204 as a mask. Can do.

Fifth Embodiment A fifth embodiment of the present invention will be described. From the experimental results of Experimental Examples 1 and 2 shown in FIGS. 2A and 2B, there is a range of Si content that is difficult to remove by oxygen plasma for Si-containing amorphous carbon. In the present embodiment, an example in which Si-containing amorphous carbon having a larger silicon content is used as an intermediate layer using the experimental results will be described.

  The semiconductor device manufacturing method according to the present embodiment is different from the semiconductor device manufacturing method according to the third embodiment in that the Si content is 20 to 80% by weight as the intermediate layer 110 shown in FIG. The same except that the Si-containing amorphous carbon layer is deposited. For adjusting the silicon content of the Si-containing amorphous carbon layer, the method shown in the first embodiment or the second embodiment can be used.

  According to the present embodiment example, the Si-containing amorphous carbon layer having a Si content of 20 to 80% by weight is compared with the Si-containing amorphous carbon layer and the photoresist layer having a Si content of 0.1 to 10% by weight. In the meantime, by having a high etch selectivity, it can function well as an intermediate layer. Also, a Si-containing amorphous carbon layer having a Si content of 0.1 wt% to 10 wt% used as a hard mask, and a Si-containing amorphous carbon layer having a Si content of 20 wt% to 80 wt% used as an intermediate layer. Can be continuously deposited by changing the gas flow rate ratio in the same chamber. Therefore, the number of processes can be reduced.

  Since the intermediate layer made of the silicon oxynitride film and the silicon oxide film used in the third embodiment example and the fourth embodiment example contains nitrogen in the composition, a trace amount of ammonia may be generated in the manufacturing stage. Therefore, when an ArF photoresist or the like is used as the photoresist, the ArF photoresist is easily affected by ammonia, so that the pattern dimension may vary. In the semiconductor device manufacturing method according to this embodiment, since the Si-containing amorphous carbon film is used as an intermediate layer, the generation of ammonia is suppressed, and even when a photoresist that is susceptible to ammonia is used, pattern dimensional variation is reduced. Can be suppressed.

Sixth Embodiment A sixth embodiment of the present invention will be described. The semiconductor device manufacturing method according to the present embodiment is different from the semiconductor device manufacturing method according to the sixth embodiment in that the Si content is 20 to 80 wt% as the intermediate layer 210 shown in FIG. The same except that the Si-containing amorphous carbon layer is deposited. For adjusting the silicon content of the Si-containing amorphous carbon layer, the method shown in the first embodiment or the second embodiment can be used. In the fifth embodiment and the sixth embodiment, a Si-containing amorphous carbon layer having a Si content of 20 to 80% by weight may be used as a part of the intermediate layer 110. Further, the intermediate layer composed of the Si-containing amorphous carbon layer having a Si content of 20 to 80% by weight can also be applied when amorphous carbon is used as a hard mask.

  Although the present invention has been described based on the preferred embodiment, the method for manufacturing a semiconductor device according to the present invention is not limited to the configuration of the above embodiment, and the configuration of the above embodiment. Thus, a method for manufacturing a semiconductor device subjected to various modifications and changes is also included in the scope of the present invention.

  The present invention can be applied to manufacture of a semiconductor device using a hard mask, and can be preferably applied to manufacture of a semiconductor device having a design rule of 0.11 μm or less.

It is a figure which shows the structure of the parallel plate type plasma CVD apparatus in the example of 1st Embodiment. FIG. 2A is a graph showing the Si content dependency of the etch selectivity, and FIG. 2B is a graph in which the horizontal axis of the graph of FIG. It is a figure which shows the structure of the high-density plasma CVD apparatus in the example of 2nd Embodiment. FIGS. 4A and 4B are cross-sectional views showing the manufacturing method of the semiconductor device of the third embodiment step by step. FIGS. 5C and 5D are cross-sectional views subsequent to FIG. 4 showing the method of manufacturing the semiconductor device of the third embodiment step by step. FIG. 6E is a cross-sectional view of a stage subsequent to FIG. 5, illustrating the manufacturing method of the semiconductor device of the third embodiment step by step. FIGS. 7A and 7B are cross-sectional views showing the manufacturing method of the semiconductor device of the fourth embodiment step by step. FIGS. 8C and 8D are cross-sectional views subsequent to FIG. 7, showing the method for manufacturing the semiconductor device of the fourth embodiment step by step. FIGS. 9E and 9F are cross-sectional views subsequent to FIG. 8 illustrating the method of manufacturing the semiconductor device of the fourth embodiment step by step. FIG. 10G is a cross-sectional view of the stage subsequent to FIG. 9, illustrating the method for manufacturing the semiconductor device of the fourth embodiment in stages.

Explanation of symbols

101: Semiconductor substrate 102: Underlayer 103: Si-containing amorphous carbon film 104: Silicon oxynitride film 105: Silicon oxide film 106: Photoresist mask 110: Intermediate layer 201: Silicon oxide film 202: Tungsten nitride film 203: Tungsten film 204 : Silicon nitride film 205: Si-containing amorphous carbon film 206: Silicon oxynitride film 207: Silicon oxide film 208: Photoresist mask 209: Spacer 210: Intermediate layer 211: Interlayer insulating film 212: Conductive plug 220: Interlayer insulating film 221 : Conductive plug 400: Parallel plate type plasma CVD apparatus 401: Reactor 402: Deposition chamber 403: Wafer susceptor 404: Shower head type electrode 405: Gas diffusion plate 406: Gas nozzle 407: Exhaust chamber 408: Exhaust line 40 : Gate valve 410: insulating ring 411: Carbon source gas line (CSL)
412: Silicon source gas line (SSL)
413: Carrier gas line (CL)
414, 415, 416: Mass flow controller (MFC)
417, 418, 419: gas valve 420: high frequency power supply 421: low frequency power supply 422: semiconductor substrate 500: high density plasma CVD apparatus 501: reactor 502: wafer susceptor 503: ceramic dome 504: coiled electrode 505: first gas nozzle 506: Second gas nozzle 507: exhaust line 508: gate valve 509: first CSL
510: First SSL
511: 1st CL
512, 513, 514: 1st MFC
515, 516, 517: first gas valve 518: second CSL
519: Second SSL
520: 2nd CL
521, 522, 523: 2nd MFC
524, 525, 526: second gas valve 527: first high frequency power source 528: second high frequency power source 529: semiconductor substrate

Claims (17)

Depositing a Si-containing amorphous carbon layer on the underlayer;
Forming a photoresist mask on the Si-containing amorphous carbon layer;
Patterning the Si-containing amorphous carbon layer using the photoresist mask as a mask to form a hard mask;
And a step of patterning the underlayer using the hard mask as a mask. A step of sequentially depositing an Si-containing amorphous carbon layer and an intermediate layer on the underlayer;
Forming a photoresist mask on the intermediate layer;
Patterning the intermediate layer using the photoresist mask as a mask to form an intermediate mask;
Patterning the Si-containing amorphous carbon layer using the intermediate mask as a mask to form a hard mask;
And a step of patterning the underlayer using the hard mask as a mask.   The method for manufacturing a semiconductor device according to claim 2, wherein the intermediate layer has a light reflection preventing function.   4. The method for manufacturing a semiconductor device according to claim 2, wherein the intermediate layer includes at least one of a silicon oxide layer and a silicon oxynitride layer.   5. The semiconductor device according to claim 4, wherein the intermediate layer includes a silicon oxynitride layer having a thickness of 50 nm or less and a silicon oxide layer formed on the silicon oxynitride layer and having a thickness of 20 nm to 60 nm. Production method.   The method for manufacturing a semiconductor device according to claim 2, wherein the intermediate layer includes at least one other Si-containing amorphous carbon layer.   The method for manufacturing a semiconductor device according to claim 6, wherein the Si content of the another Si-containing amorphous carbon layer is in a range of 20 wt% to 80 wt%.   The manufacturing method of the semiconductor device as described in any one of Claims 1-7 whose Si content rate of the said Si containing amorphous carbon layer is the range of 0.1 weight%-10.0 weight%.   The manufacturing method of the semiconductor device as described in any one of Claims 1-7 whose Si content rate of the said Si containing amorphous carbon layer is the range of 0.1 weight%-5.0 weight%. Prior to the step of depositing the Si-containing amorphous carbon layer, depositing an amorphous carbon layer on the underlayer,
The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the hard mask, the Si-containing amorphous carbon layer and the amorphous carbon layer are simultaneously patterned to form the hard mask.   The semiconductor device manufacturing according to any one of claims 1 to 10, wherein the Si-containing amorphous carbon layer is deposited by a plasma chemical vapor deposition method using a mixed gas containing a hydrocarbon compound gas and a silicon compound gas. Method. The hydrocarbon compound gas is methane (CH ₄ ), ethane (C ₂ H ₆ ), propane (C ₃ H ₈ ), butane (C ₄ H ₁₀ ), acetylene (C ₂ H ₂ ), propylene (C ₃ H _The method for manufacturing a semiconductor device according to claim 11, comprising at least one of ₆ ) and propyne (C ₃ H ₄ ). The semiconductor according to claim 11, wherein the silicon compound gas includes at least one of monosilane (SiH ₄ ), disilane (Si ₂ H ₆ ), and tetramethylsilane (Si (CH ₃ ) ₄ ). Device manufacturing method.   The method of manufacturing a semiconductor device according to claim 11, wherein the mixed gas further includes at least one of helium (He) and argon (Ar).   The manufacturing method of the semiconductor device as described in any one of Claims 11-14 with which the said Si containing amorphous carbon layer is deposited using a parallel plate type plasma CVD apparatus or a high-density plasma CVD apparatus.   The semiconductor device manufacturing according to any one of claims 1 to 15, wherein all or part of the Si-containing amorphous carbon layer is removed by plasma including at least one of oxygen plasma, ammonia plasma, and fluorocarbon plasma. Method. The whole or part of the Si-containing amorphous carbon layer is removed by plasma including at least one of CF ₄ plasma, C ₂ F ₆ plasma, and C ₃ F ₈ plasma. A method for manufacturing a semiconductor device according to claim 1.

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