CN109786327A - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN109786327A CN109786327A CN201711104656.8A CN201711104656A CN109786327A CN 109786327 A CN109786327 A CN 109786327A CN 201711104656 A CN201711104656 A CN 201711104656A CN 109786327 A CN109786327 A CN 109786327A
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Abstract
A kind of semiconductor devices and forming method thereof, wherein method includes: offer semiconductor substrate, there is adjacent the first fin and the second fin in the semiconductor substrate, also there is the separation layer of covering the first fin and the second fin partial sidewall in the semiconductor substrate；The first initial dopant layer is formed on the first fin；The second initial dopant layer is formed on the second fin, the second initial dopant layer is adjacent with the first initial dopant layer；Oxidation processes are carried out to the first initial dopant layer and the second initial dopant layer, so that the first initial dopant layer is formed the first doped layer and the first oxide layer positioned at the first doping layer surface, the second initial dopant layer is made to form the second oxide layer of the second doped layer and the second doping layer surface；Remove the first oxide layer and the second oxide layer.The performance of the method raising semiconductor devices.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor devices and forming method thereof.
Background technique
With the rapid development of semiconductor processing technology, semiconductor devices is towards higher component density and higher
The direction of integrated level is developed.Transistor is just widely used at present as most basic semiconductor devices, traditional flat crystal
Pipe dies down to the control ability of channel current, generates short-channel effect and leads to leakage current, the final electricity for influencing semiconductor devices
Learn performance.
In order to overcome the short-channel effect of transistor, inhibit leakage current, the prior art proposes fin formula field effect transistor
(Fin FET), fin formula field effect transistor are a kind of common multi-gate devices, and the structure of fin formula field effect transistor includes: position
In the fin and dielectric layer of semiconductor substrate surface, the side wall of fin described in the dielectric layer covering part, and dielectric layer surface
Lower than at the top of fin；Gate structure positioned at the top and sidewall surfaces of dielectric layer surface and fin；Positioned at the grid knot
Source region and drain region in the fin of structure two sides.
However, the electric property of semiconductor devices is poor in the prior art.
Summary of the invention
Present invention solves the technical problem that being to improve a kind of semiconductor devices and forming method thereof, to improve semiconductor devices
Performance.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of offer semiconductor substrate, comprising: provide semiconductor
Substrate has adjacent the first fin and the second fin in the semiconductor substrate, also has the first fin of covering on the substrate
The separation layer in portion and the second fin partial sidewall；The first initial dopant layer is formed on the first fin；It is formed on the second fin
Second initial dopant layer, the second initial dopant layer are adjacent with the first initial dopant layer；It is initial to the first initial dopant layer and second
Doped layer carries out oxidation processes, and the first initial dopant layer is made to form the first doped layer and positioned at the first of the first doping layer surface
Oxide layer makes the second initial dopant layer form the second oxide layer of the second doped layer and the second doping layer surface；Removal first
Oxide layer and the second oxide layer.
Optionally, carrying out the technique of oxidation processes to the first initial dopant layer and the second initial dopant layer includes: dry method oxygen
Chemical industry skill or wet process oxidation technology.
Optionally, first oxide layer with a thickness of 10 angstroms~50 angstroms.
Optionally, removing first oxide layer and the technique of the second oxide layer includes: dry etch process.
Optionally, before forming the first initial dopant layer and the second initial dopant layer, shape on the semiconductor substrate
At the first grid structure across the first fin and the second grid structure across the second fin, the first grid structure covering
The atop part surface and partial sidewall surface of first fin, the second grid structure cover the atop part table of the second fin
Face and partial sidewall surface.
Optionally, the forming step of the first initial dopant layer includes: the first grid knot for being developed across the first fin
After structure, the first groove is formed in the fin of first grid structure two sides, and the first initial dopant layer is formed in the first groove.
Optionally, the technique for forming the first initial dopant layer includes epitaxial growth technology.
It optionally, further include to first initial dopant during being epitaxially-formed the first initial dopant layer
Layer carries out doping in situ, adulterates the first ion in the first initial dopant layer.
Optionally, when the first grid structure is used to form P-type device, the material of the first initial dopant layer includes mixing
The miscellaneous SiGe for having the first ion, the conduction type of the first ion are p-type；When the first grid structure is used to form N-type device
When, the material of the first initial dopant layer includes the silicon doped with the first ion, and the conduction type of the first ion is N-type.
It optionally, further include in first grid structure before the formation of the first groove after forming first grid structure
Sidewall surfaces form the first side wall.
Optionally, after first side wall formation, before the first groove is formed, to the gate structure and the first side
First fin of wall two sides carries out ion implanting, forms the first lightly doped district.
It optionally, include: to be formed on second fin the step of forming the second initial dopant layer on the second fin
After the second grid structure of the second fin, the second side wall is formed in second grid structure two sides；Formed the second side wall it
Afterwards, ion implanting is carried out to the second fin of the second side wall sidewall surfaces and forms the second lightly-doped layer；Form the second lightly-doped layer
Afterwards, the second groove is formed in the second side wall two sides；The second initial dopant layer is formed in the second groove.
Optionally, the technique for forming the second initial dopant layer includes epitaxial growth technology.It is being epitaxially-formed
It further include that doping in situ is carried out to the second initial dopant layer during two initial dopant layers；In second initial dopant layer
With the second ion.
Optionally, when the second grid structure is used to form P-type device, the material of the second initial dopant layer includes mixing
The miscellaneous SiGe for having the second ion, the conduction type of the second ion are p-type；When the second grid structure is used to form N-type device
When, the material of the second initial dopant layer includes the silicon doped with the second ion, and the conduction type of the second ion is N-type.
Optionally, the semiconductor substrate includes memory block and logic area, has the first fin and the second fin on memory block
Portion has third fin on logic area；The separation layer is also located at the portion on semiconductor substrate logic area and covering third fin
Divide side wall；The forming method of the semiconductor devices further include: the third of third fin is developed across on the third fin
Gate structure, third gate structure cover the atop part surface and partial sidewall surface of third fin；In third gate structure
Two sides form third groove；Third source and drain doping layer is formed in third groove.
Optionally, also there is fourth fin adjacent with third fin on the semiconductor substrate logic area；The isolation
Layer is also located at the partial sidewall on semiconductor substrate logic area and covering the 4th fin；The forming method of the semiconductor devices is also
It include: the 4th gate structure that the 4th fin is developed across on the 4th fin, the 4th gate structure covers the 4th fin
Atop part surface and partial sidewall surface；The 4th groove is formed in the 4th gate structure two sides；It is formed in the 4th groove
4th source and drain doping layer.
Optionally, before forming the first oxide layer, protective layer is formed on logic area；The forming step of the protective layer
It include: in the first initial dopant layer, the second initial dopant layer, third source and drain doping layer and the 4th source and drain doping layer surface shape
At protective film；The protective film on the first initial dopant layer and the second initial dopant layer is removed, in third source and drain doping layer and the 4th
Protective layer is formed on source and drain doping layer.
Optionally, the protective layer with a thickness of 30 angstroms~80 angstroms；The material of the protective layer includes: silica, nitridation
Silicon, silicon oxynitride, silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.
Optionally, the step of removing the protective film on memory block the first initial dopant layer and the second initial dopant layer include:
Patterned layer is formed on protective film；The first initial dopant layer using the patterned layer as exposure mask, on etching removal memory block
With the protective film of the second initial dopant layer surface.
The present invention also provides a kind of semiconductor devices formed using above-mentioned any one method.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In the forming method for the semiconductor devices that technical solution of the present invention provides, on the first doped layer and the second doped layer
The first oxide layer and the second oxide layer are formed, the first oxide layer and the second oxide layer pass through oxidation the first initial dopant layer and second
The material of initial dopant layer surface and formed, part the first initial dopant layer and the second initial dopant layer can be consumed.Removal first
After oxide layer and the second oxide layer, due to consuming part the first initial dopant layer and the second initial dopant layer, first initially mixes
The distance between diamicton and the second initial dopant layer increase accordingly, reduce the first doped layer and the second doped layer be connected it is general
Rate, and then improve the performance of device.
Further, the device density of the logic area of semiconductor devices is smaller, and distance is larger between fin, third doped layer and
4th doped layer is not easy to contact, the guarantor of third source and drain doping layer and the 4th source and drain doping layer due to protective layer in oxidation process
Shield, is not oxidized, and volume is relatively large, and surface area is larger, can reduce the contact resistance of logic area device, so that work electricity
Flow performance that is larger, and then improving device.
Detailed description of the invention
Fig. 1 to Fig. 2 is a kind of structural schematic diagram of semiconductor devices；
Fig. 3 to Figure 13 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
Specific embodiment
As described in background, the performance for the semiconductor devices that the prior art is formed is poor.
A kind of forming method of SRAM device please refers to Fig. 1 and Fig. 2, and Fig. 2 is the sectional view of the cutting line A-a along Fig. 1,
Include: that semiconductor substrate 100 is provided, in semiconductor substrate 100 with adjacent the first fin 110 and the second fin 111 and
Cover the separation layer 101 of 111 partial sidewall of 110 partial sidewall of the first fin and the second fin；Is developed across on separation layer
The first grid structure 130 of one fin 110；The first source and drain is formed in the first fin 110 of 130 two sides of first grid structure to mix
Diamicton 150；The second grid structure 140 of the second fin 111 is developed across on separation layer；In 140 two sides of second grid structure
The second fin 111 in form the second source and drain doping layer 160,150 phase of the second source and drain doping layer 160 and the first source and drain doping layer
It is adjacent.
However, the performance for the SRAM memory that the above method is formed is poor, the device is located at the memory block of SRAM device,
When the first grid structure, which is used to form, to pull up transistor, the type of the transistor is p-type, first source and drain doping
The epitaxial material of layer 150 is SiGe, and for SiGe during extension, the speed of growth on different crystal orientations is variant, in<111>crystal orientation
Upper growth is most slow, and extension crystal face can stop on (111) crystal face, and will continue to grow in other faces, to form tip.Phase
Answer when second grid structure is also used for being formed and pull up transistor, the second source and drain doping layer 160 also will form tip.With half
Conductor device develops towards high density, and it is also smaller and smaller to form the distance between transistor of semiconductor devices, the second source and drain
Space between doped layer 160 and the first source and drain doping layer 150 is smaller and smaller, and the second source and drain doping layer 160 and the first source and drain are mixed
Diamicton 150 is readily attached together, so that the second source and drain doping layer 160 and the first source and drain doping layer 150 are easy to happen bridge joint, bridge
Connecing can leak electricity between latter two unrelated device, and then influence the performance for being formed by SRAM device.
In order to solve the above-mentioned technical problem, technical solution of the present invention passes through to the first initial dopant layer and the second initial dopant
Layer carries out oxidation and forms oxide layer, consumes part the first initial dopant layer and the second initial dopant layer, and removal is formed by oxidation
Layer increases so that the distance between the first doped layer and the second doped layer are opposite, reduces probability connected therebetween,
To improve the performance of device.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Fig. 3 to Figure 13 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
Fig. 3 and Fig. 4 are please referred to, Tu4Zhong corresponding A area is sectional view of the Fig. 3 along the direction M-M1, and it is Fig. 3 that the area B is corresponded in Fig. 4
Sectional view along the direction M2-M3 provides semiconductor substrate 200.
The semiconductor substrate includes memory block I, in the memory block I semiconductor substrate have the first adjacent fin,
Second fin and separation layer, the separation layer cover the first fin and the second fin partial sidewall.
In the present embodiment, being formed by device is SRAM device, and the first fin is used to form the upper crystal pulling of SRAM device
Pipe, the second fin is formed by type of device and the first fin, and to be formed by type of device identical, is also used for forming SRAM device
Pull up transistor.
In one embodiment, the first fin is used to form pulling up transistor for SRAM device, and the second fin is used to form
The pull-down transistor of SRAM device.In another embodiment, the first fin is used to form the pull-down transistor of SRAM device, the second fin
The type of device that portion is used to form can be identical as the type for the device that the first fin is used to form, and can also be different.
The material of the semiconductor substrate includes the semiconductor materials such as silicon, germanium, SiGe, GaAs, indium gallium arsenic, wherein silicon
Material includes monocrystalline silicon, polysilicon or amorphous silicon.The substrate can also be semiconductor-on-insulator structure, on the insulator
Semiconductor structure includes insulator and the semiconductor material layer on insulator, and the material of the semiconductor material layer includes
The semiconductor materials such as silicon, germanium, SiGe, GaAs, indium gallium arsenic.
In the present embodiment, the material of the semiconductor substrate 200 is monocrystalline silicon.
There is adjacent the first fin 211 and the second fin 212 in the memory block I semiconductor substrate.
First fin is used to form the first transistor, and second fin is used to form second transistor.This implementation
In example, the first transistor is adjacent with second transistor.In actual process, second is determined according to institute's circuit layout to be formed
The type of transistor.In the present embodiment, the first transistor is to pull up transistor, therefore the first transistor type is p-type, the second crystal
For pipe also to pull up transistor, the type of second transistor is p-type.
In the present embodiment, first fin 211 and the second fin 212 pass through the graphical semiconductor substrate 200
It is formed.In other embodiments, it may is that formation fin material layer on the semiconductor substrate, then the graphical fin
Portion's material layer, to form fin.
In the present embodiment, the material of the first fin 211 and the second fin 212 is monocrystalline silicon.In other embodiments, fin
Material be monocrystalline germanium silicon or other semiconductor materials.
The semiconductor substrate also has logic area II, has third fin in the semiconductor substrate 200 of the logic area II
Portion 213, the third fin 213 are used to form third transistor.Have the 4th in the semiconductor substrate 200 of the logic area II
Fin (not shown), the 4th fin are used to form the 4th transistor, and the 4th transistor is adjacent with third transistor.Institute
Third fin 213 and the 4th fin is stated to be formed by the graphical semiconductor substrate 200.
In the present embodiment, further includes: form separation layer 201 in the semiconductor substrate 200, the separation layer 201 covers
The partial sidewall surface of lid the first fin 211, the second fin 212, third fin 213 and the 4th fin.The separation layer 201
Material includes silica.
Referring to FIG. 5, Fig. 5 is consistent with Fig. 4 profile direction, the first fin is developed across in the semiconductor substrate 200
211 first grid structure 221, first grid structure 221 are pushed up across the part of the first fin 211 and the first fin 211 of covering
Portion surface and partial sidewall surface；It is developed across the second grid structure 222 of the second fin 212 on semiconductor substrate 200, the
Two gate structures 222 are across the atop part surface and partial sidewall surface of the second fin 212 and the second fin 212 of covering.
First grid structure 221 includes the gate dielectric layer across the first fin 211, the gate electrode layer on gate dielectric layer
And the protective layer 202 at the top of gate electrode layer.Second grid structure 222 include across the second fin 212 gate dielectric layer,
Gate electrode layer on gate dielectric layer and the protective layer at the top of gate electrode layer 202.First gate dielectric layer is separated positioned at A
201 part of the surface of absciss layer and the atop part surface and partial sidewall surface for covering the first fin 111.Second gate dielectric layer position
201 part of the surface of absciss layer is separated in B and covers the atop part surface and partial sidewall surface of the second fin 112.
In the present embodiment, the material of the first gate dielectric layer and the second gate dielectric layer is silica.In other embodiments,
The material of one gate dielectric layer and the second gate dielectric layer is high K dielectric material (K is greater than 3.9).First gate electrode layer and second gate electricity
The material of pole layer is polysilicon.
In the present embodiment, the top surface of first grid structure 221 also has first grid protective layer 202, the second gate
The top surface of pole structure 222 also has second gate protective layer 203.The first grid protective layer 202 and second gate protective layer 203
Material be SiN, SiCN, SiBN or SiON.
In the present embodiment, further includes: form third gate structure in semiconductor substrate 200 and separation layer 201 and (do not scheme
Show), third gate structure is across the atop part surface and partial sidewall surface of third fin and covering third fin；Partly leading
The 4th gate structure (not shown) is formed in body substrate 200 and separation layer 201, the 4th gate structure is across the 4th fin and covering
The atop part surface and partial sidewall surface of 4th fin.
The third gate structure includes across the third gate dielectric layer of third fin and on third gate dielectric layer
Third gate electrode layer.4th gate structure includes across the 4th gate dielectric layer of the 4th fin and positioned at the 4th gate dielectric layer
On the 4th gate electrode layer.Third gate dielectric layer is located at the part top that third separates 201 part of the surface of absciss layer, covers third fin
Portion surface and partial sidewall surface.4th gate dielectric layer is located at the 4th portion for separating 201 part of the surface of absciss layer, covering the 4th fin
Divide top surface and partial sidewall surface.The material of third gate dielectric layer and the 4th gate dielectric layer is silica, the third grid
The material of electrode layer and the 4th gate electrode layer is polysilicon.
In the present embodiment, the top surface of third gate structure also has third grid protective layer (not shown), the 4th grid
The top surface of structure also has the 4th grid protective layer (not shown).The material of the third grid protective layer and the 4th grid protective layer
For SiN, SiCN, SiBN or SiON.
Referring to FIG. 6, the side wall in first grid layer forms the first side wall 231.
First side wall 231, which is used as, protects the first grid layer side wall, and the grid layer being subsequently formed is avoided shape occur
Looks defect influences the electric property of semiconductor structure.
The forming step of first side wall 231 includes: to form first on the separation layer 201 and the first gate dielectric layer
Spacer material layer, the first spacer material layer cover the partial sidewall surface and atop part surface of first fin 211
And the side wall and top surface of the first grid layer；It is etched back to the first spacer material layer, until exposing described the
The top surface of one gate dielectric layer and the first grid layer forms on the first gate dielectric layer and is covered in the first grid layer
First side wall of side wall.
The formation process of the first spacer material layer is chemical vapor deposition process, physical gas-phase deposition or atom
One of layer depositing operation or multiple combinations.The material of first side wall 231 include silica, silicon nitride, silicon oxynitride,
Silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.
In the present embodiment, the formation process of the first spacer material layer is chemical vapor deposition process.First side
The material of wall 231 is silicon nitride.First side wall with a thickness of 20 angstroms~40 angstroms.
The technique for being etched back to the first spacer material layer is anisotropic dry etching, the technique of the dry etching
Parameter are as follows: the fluorine-containing gas of use (such as CH3F、CH2F2Or CHF3), argon gas and oxygen, be 200W-400W in etching power,
The pressure of etching cavity is 30mtorr-200mtorr, and etching temperature is 40 DEG C -60 DEG C.
First gate dielectric layer can protect the of the first side wall two sides when being etched back to the first spacer material layer
One fin.
First side wall 231 is also located at 212 partial sidewall of the second fin, second grid layer side wall, third fin point side
Wall, third grid layer side wall, the 4th fin partial sidewall and the 4th grid layer side wall.
With continued reference to FIG. 6, being formed after first side wall 231, to the first of 221 two sides of first grid structure
Fin 212 carries out ion doping, forms first grid structure 221 and 240 two sides of the first side wall form the first lightly doped district and (do not scheme
Show).
The technique for carrying out ion doping to the first fin 212 of 221 two sides of first grid structure is ion implanting work
Ion is lightly doped for first in skill, the ion implanting ion.
First lightly doped district is located at 240 two sides of first grid structure 221 and the first side wall, and the first side wall 240 increases
The distance between first lightly doped district can reduce by first distance that ion horizontal proliferation is lightly doped, and reduce short-channel effect.
First gate dielectric layer protects the first fin in ion implantation process.
When the type of the first transistor is p-type, the first conduction type that ion is lightly doped is p-type；When described
When the type of one transistor is N-type, the first conduction type that ion is lightly doped is N-type.
In the present embodiment, the type of the first transistor is p-type, and described first ion is lightly doped is arsenic ion, energy
Range is 1KeV~10KeV, dosage range 1E14atom/cm2~1E16atom/cm2, tilt angle is 0~30 degree；It is described
Tilt angle is the folder where injection direction and semiconductor substrate 200 (front is semiconductor substrate 200) between the normal of plane
Angle.
In other embodiments, the type of the first transistor is N-type, and described first ion is lightly doped is boron ion, energy
Amount range is 0.5KeV~5KeV, dosage range 1E14atom/cm2~1E16atom/cm2, tilt angle is 0~30 degree；Institute
State the angle between the normal that tilt angle is 200 place plane of injection direction and semiconductor substrate.
In the present embodiment, further includes: ion doping is carried out to the second fin 212 of 222 two sides of second grid structure,
It forms second grid structure 222 and 231 two sides of the first side wall forms the second lightly doped district (not shown).To the second grid knot
The technique that second fin 212 of 222 two sides of structure carries out ion doping is ion implantation technology, and the ion implanting ion is second
Ion is lightly doped.When the type of the second transistor is p-type, the second conduction type that ion is lightly doped is p-type；When described
When the type of second transistor is N-type, the second conduction type that ion is lightly doped is N-type.
In the present embodiment, the type of the second transistor is p-type, to the first fin of first grid structure two sides
While carrying out ion implanting, ion implanting, the ion note also are carried out to the second fin of second grid structure two sides
Enter ion and ion is lightly doped for second, forms the second lightly doped district in second grid structure two sides.Described second is lightly doped ion
For arsenic ion.
In other embodiments, the type of the second transistor is N-type.When the second transistor is N-type, described the
The forming step of two lightly-doped layers includes: to form the first mask layer in the area B after forming the first spacer material layer, and first
Mask layer defines the position in the area A, the first spacer material floor being etched back in the area A；The first side wall 231 and are formed in the area A
One lightly doped district；After first lightly doped district is formed, the second mask layer is formed in the area A；Formed in the area A the second mask layer it
Afterwards, the first mask layer in the area B is removed；After removing the first mask layer in the area B, the first spacer material for being etched back in the area B
Layer forms the first side wall in second grid layer side wall and the second fin partial sidewall；To described
Second fin 212 of bis- gate structure of MP1709248,222 two sides carries out ion doping, forms second grid structure
222 and 231 two sides of the first side wall formed the second lightly doped district (not shown).To the second of 222 two sides of second grid structure
The technique that fin 212 carries out ion doping is ion implantation technology, and ion is lightly doped for second in the ion implanting ion, described
Second is lightly doped ion as N-type.
With reference to Fig. 7 and Fig. 8, Fig. 7 is consistent with Fig. 6 profile direction, and Fig. 8 is sectional view of the Fig. 7 along the direction N-N1, is forming the
After one side wall 231, the mask layer 240 for being located at 201 surface of separation layer is formed in the partial sidewall of the first fin 211.
The mask layer 240 in the area A is located at the atop part surface of the first fin 211, the side wall of first grid structure 221 and top
Portion, A separate the surface of absciss layer 201, the partial sidewall of the second fin 212 and top surface, second grid structure 222 side wall and
Top, the surface in the area B, the atop part surface of third fin and partial sidewall surface, the side wall of third gate structure and top,
201 surface of separation layer, the atop part surface of the 4th fin and the side wall on partial sidewall surface, the 4th gate structure in third area
With 201 surface of separation layer at top and the 4th area.
In the present embodiment, first grid protective layer 202, second gate protective layer 203, third grid protective layer and the 4th grid are formd
Protective layer, the mask layer 240 are also located at first grid protective layer 202, second gate protective layer 203, third grid protective layer and the 4th
On grid protective layer.
The material of the mask layer 240 is SiN, SiCN, SiBN or SiON.The technique for forming mask layer 240 is deposition work
Skill, such as atom layer deposition process or plasma activated chemical vapour deposition technique.
In the present embodiment, the material of the mask layer 240 is SiN.The mask layer 240 with a thickness of 50 angstroms~100 angstroms.
The technique of the mask layer 240 is atom layer deposition process, the parameter of the atom layer deposition process include: the gas that uses for
SiH2Cl2And NH3Mixed gas, the flow of mixed gas is 1500sccm~4000sccm, pressure be 1mtorr~
10mtorr, temperature are 200 degrees Celsius~600 degrees Celsius, and frequency of depositing is 30 times~300 times.
Referring to FIG. 9, Fig. 9 is consistent with Fig. 8 profile direction, after the mask layer 240 is formed, the first fin 211 is removed
First side wall and mask layer 240 on surface etch the first fin 211 of 221 two sides of first grid structure, described first
The first groove (not shown) is formed in fin 211；After first groove shapes, first is formed in first groove
Initial dopant layer 251.
The technique for forming the first initial dopant layer 251 is epitaxial growth technology.It is initial being epitaxially-formed first
It further include that doping in situ is carried out to the first initial dopant layer 251 during doped layer 251, the Doped ions are the
One ion.
When the type of the first transistor is p-type, the material of the first initial dopant layer includes doped with the first ion
SiGe, the conduction type of the first ion is p-type；When the type of the first transistor is N-type, the first initial dopant layer
Material includes the silicon doped with the first ion, and the conduction type of the first ion is N-type.
In the present embodiment, the type of the first transistor is p-type, the material of the first initial dopant layer be doped with
The SiGe of phosphonium ion, first ion are boron ion.The material of first initial dopant layer is SiGe, and SiGe is in epitaxial process
In, the speed of growth on different crystal orientations is variant, grows up most slowly in 111 crystalline substances, and extension crystal face can stop on 111 crystal faces,
And will continue to grow in other faces, to form tip, i.e. the first initial dopant layer has tip.
In the present embodiment, further includes: the second initial dopant layer 252 is formed in the second fin 212, when described second initial
The forming step of doped layer includes: the first side wall and mask layer 240 for removing 211 surface of the second fin, etches the second gate
Second fin 212 of 222 two sides of pole structure, forms the second groove (not shown), described second in second fin 212
After groove shapes, the second initial dopant layer 252 is formed in second groove.
The technique for forming the second initial dopant layer 252 is epitaxial growth technology.It is initial being epitaxially-formed second
It further include that doping in situ is carried out to the second initial dopant layer 252 during doped layer 252, the Doped ions are the
Two ions.
When the type of the second transistor is p-type, the material of the second initial dopant layer includes doped with the second ion
SiGe, the conduction type of the second ion is p-type；When the type of the second transistor is N-type, the second initial dopant layer
Material includes the silicon doped with the second ion, and the conduction type of the second ion is N-type.
In the present embodiment, the type of the second transistor is p-type, during the first initial dopant layer of the formation
It is formed simultaneously the second initial dopant layer, the material of same second initial dopant layer is SiGe, it may have tip.
In other embodiments, the type of the second transistor is N-type, the forming step packet of the second initial dopant layer
It includes: after forming the first spacer material layer, forming the first mask layer in the area B, the first mask layer defines the position in the area A；
The first side wall 231 and the first lightly doped district are formed in the area A；After first lightly doped district is formed, the first grid knot is etched
First fin 211 of 221 two sides of structure, forms the first groove (not shown) in first fin 211, in first groove
After shape, the first initial dopant layer 251 is formed in first groove；It is formed after the first initial dopant layer 251,
The second mask layer is formed in the area A and the area B；Formed in the area A after the second mask layer, remove the area B on the first mask layer and
Second mask layer；After removing the first mask layer and the second mask layer in the area B, in second grid layer side wall and the second fin portion
Side wall is divided to form the first side wall and the second lightly doped district；After second lightly doped district is formed, the second grid structure 222 is etched
Second fin 212 of two sides, forms the second groove (not shown) in second fin 212, in second groove shapes
Later, the second initial dopant layer 252 is epitaxially formed in second groove, the material of the second initial dopant layer 252 is
Doped with the silicon of phosphonium ion.
In the present embodiment, further includes: form third groove in third gate structure two sides, be epitaxially formed in third groove
Third source and drain doping layer.The 4th groove is formed in the 4th gate structure two sides, the 4th source and drain is epitaxially formed in the 4th groove and mixes
Diamicton.
It is same in the first initial dopant layer 251 for forming p-type the first transistor when the third transistor type is p-type
When formed have P-type ion third source and drain doping layer 253；When the third transistor type is N-type, N-type the is being formed
Second initial dopant layer 252 of two-transistor is formed simultaneously the third source and drain doping layer 253 with N-type ion.
When the 4th transistor types are p-type, in the first initial dopant layer while shape for forming p-type the first transistor
At the 4th source and drain doping layer with P-type ion；When the 4th transistor types are N-type, N-type second transistor is being formed
The second initial dopant layer be formed simultaneously the 4th source and drain doping layer with N-type ion.
In other embodiments, logic area is not formed.
Before forming the first oxide layer, form protective layer on logic area, the forming step of the protective layer include:
The first initial dopant layer, the second initial dopant layer, third source and drain doping layer, the 4th source and drain doping layer surface form protection
Film；The protective film on the first initial dopant layer and the second initial dopant layer of memory block is removed, forms protective layer on logic area.
Please refer to Figure 10 and Figure 11.
Referring to FIG. 10, being formed after the first initial dopant layer 251 and the second initial dopant layer 252, at the beginning of described first
Protective film 204 is formed on beginning doped layer and the second initial dopant layer.
It further include the shape on the third source and drain doping layer 253 and the 4th source and drain doping layer for being located at logic area in the present embodiment
At protective film 204.
The protective layer 205 is protected during the first initial dopant of subsequent oxidation layer 251 and the second initial dopant layer 252
Protect the third source and drain doping layer 253 and the 4th source and drain doping layer of logic area.
The formation process of the protective film 204 includes: chemical vapor deposition process, physical gas-phase deposition or atomic layer
Depositing operation.
In the present embodiment, the formation process of the protective layer is atom layer deposition process, the atom layer deposition process ginseng
Number includes: the gas that uses for SiH2Cl2And NH3Mixed gas, the flow of mixed gas is 1500sccm~4000sccm,
Pressure is 1mtorr~10mtorr, and temperature is 200 degrees Celsius~600 degrees Celsius, and frequency of depositing is 20 times~100 times.
Figure 11 is please referred to, is formed after protective film 204, the first initial dopant layer 251 and second for removing memory block is initial
Protective film on doped layer 252 forms protective layer 205.
The protective film 204 on the first initial dopant layer 251 and the second initial dopant layer 252 is removed so as to subsequent oxidation first
Initial dopant layer and the second initial dopant layer.
The protective layer 205 with a thickness of 30 angstroms~80 angstroms.
205 thickness of protective layer is blocked up, and technique is be easy to cause to waste；205 thickness of protective layer is excessively thin, in oxidation the
It can not effective protection third source and drain doping layer and the 4th source and drain doping layer during one initial dopant layer and the second initial dopant layer.
The material of the protective layer 205 includes: silica, silicon nitride, silicon oxynitride, silicon oxide carbide, carbonitride of silicium or carbon
Silicon oxynitride.In the present embodiment, the material of the protective layer 205 is silicon nitride.
In the present embodiment, the protective film on the first initial dopant of memory block layer 251 and the second initial dopant layer 252 is removed
204 the step of includes: the formation patterned layer (not shown) on protective film 204；Using the patterned layer as exposure mask, etching removal
The protective film 204 on 252 surface of the first initial dopant layer 251 and the second initial dopant layer on memory block.
In the present embodiment, the protective film of etching removal the first initial dopant layer 251 and 252 surface of the second initial dopant layer
204 technique be wet-etching technology, the parameter of the wet-etching technology include: the wet etching generally use phosphoric acid with
The phosphoric acid etching liquid that the mixture of deionized water is formed, wherein the concentration of volume percent of phosphoric acid is 80%~90%, such as 86%
~87%, technological temperature is in 90 degrees Celsius~150 degree Celsius ranges, and such as 120 degrees Celsius.
In other embodiments, the protective film of etching removal the first initial dopant layer 251 and 252 surface of the second initial dopant layer
204 technique is dry etch process, and the parameter of the dry etch process includes: that the gas of use includes CH3F gas, nitrogen
Gas and oxygen, CH3The flow of F gas is 8sccm~50sccm, and the flow of the gas of nitrogen is 200sccm, and the flow of oxygen is
10sccm is 100W in etching power, and etching electric current is 30W~100W, and the pressure of etching cavity is 10mtorr~200mtorr,
Etch period is 4 seconds~50 seconds.
In other embodiments, protective layer is not formed, in the third source and drain doping layer and the 4th source and drain doping layer of logic area II
Upper formation third oxide layer and the 4th oxide layer.
Figure 12 is please referred to, after removing the protective film 204 on the first initial dopant layer 251 and the second initial dopant layer 252,
Oxidation processes are carried out to the first initial dopant layer 251 and the second initial dopant layer 252, first is formed on the first fin 2111 and mixes
Diamicton 261 has the first oxide layer 206 on first doped layer 261, forms the second doped layer 262 on the second fin 212, and second
There is the second oxide layer 207 on doped layer.First oxide layer and the second oxide layer are that the first initial dopant layer of oxidation and second are initial
Doped layer and formed, after rear extended meeting removes the first oxide layer and the second oxide layer, that is, consume part the first initial dopant layer and
Second initial dopant layer, the distance between the first initial dopant layer and the second initial dopant layer increase accordingly, and reduce first and mix
The probability that diamicton and the second doped layer are connected, and then improve the performance of device.
To the technique that the first initial dopant layer and the second initial dopant layer carry out oxidation processes include: dry oxidation technique or
Wet process oxidation technology.
In the present embodiment, the technique for carrying out oxidation processes to the first initial dopant layer and the second initial dopant layer is plasma
Body oxidation technology, the technological parameter of the plasma oxidation include: that temperature is 700 degrees Celsius~1000 degrees Celsius, when technique
Between be 100 seconds~1000 seconds, process pressure be 50torr~300torr, process gas O2And N2Mixed gas, O2With N2
Ratio is 1/20~1/5.
First oxide layer 206 with a thickness of 10A~50A.
The thickness of first oxide layer 206 is blocked up, the first initial dopant layer 251 and the second initial dopant layer 252
Consumption is excessive, influence device to be formed contact resistance；First oxide layer, 206 thickness is excessively thin, subsequent removal oxidation
After layer, it is closer between the first initial dopant layer 251 and the second initial dopant layer 252, is easy to happen bridge joint.
In the present embodiment, the type of the first transistor and second transistor is p-type, forms the first initial dopant layer
It is SiGe with the material of the second initial dopant layer, the shape of the first initial dopant layer and the second initial dopant layer is ∑ type.
Since the first initial dopant layer and the second initial dopant layer are adjacent, the first initial dopant layer and the second initial dopant layer surface
Tip be easy to be connected, during being aoxidized to the first initial dopant layer and the second initial dopant layer, since tip portion is connected,
Lower than the first initial dopant layer of tip portion and the second initial dopant layer surface due to being blocked without being oxidized, meanwhile,
It is since the first initial dopant layer or the second initial dopant layer tip portion are intersected by the different surface of normal direction, then described
The surface of first initial dopant layer or the second initial dopant layer tip portion is easier to be oxidized, so the oxygen that tip portion is formed
It is thicker to change layer, so that distance relatively far away from, reduces the two between the first doped layer and the second doped layer that are subsequently formed
Between be connected probability.In the present embodiment, matcoveredn on the third source and drain doping layer and the 4th source and drain doping layer of the logic area
Protection, will not be oxidized.
In other embodiments, the protective layer is not formed, to the third source and drain doping layer and the 4th source and drain of the logic area
Doped layer is aoxidized, and third oxide layer and the 4th oxide layer are formed.
Figure 13 is please referred to, after carrying out oxidation processes to the first initial dopant layer 251 and the second initial dopant layer 252, is gone
Except first oxide layer 206 and the second oxide layer 207.
The technique for removing first oxide layer 206 and the second oxide layer 207 is dry etch process, the dry etching
The parameter of technique includes: that the gas of use includes NH3Gas, NF3Gas and He, NH3The flow of gas be 200sccm~
500sccm, NF3The flow of gas is 20sccm~200sccm, and the flow of He is 600sccm~2000sccm, and pressure is
2torr~10torr, time are 20 seconds~100 seconds.
In the present embodiment, oxide layer is not formed in logic area.
In other embodiments, the third source and drain doping layer and the 4th source and drain doping layer of the logic area are aoxidized, shape
At third oxide layer and the 4th oxide layer；Remove third oxide layer and the 4th oxide layer, formed the effective source and drain doping layer of third and
4th effective source and drain doping layer.Between the effective source and drain doping layer of the third and the 4th effective source and drain doping layer distance farther out, hair
Raw bridge joint probability is lower.
The distance between adjacent first fin 211 and the second fin 212 are certain, the first initial dopant layer 251 and second
When volume between initial dopant layer 252 is larger, between the first initial dopant layer 251 and the second initial dopant layer 252 distance compared with
Closely.The first initial dopant layer 251 and the second initial dopant layer 252 are aoxidized, the first initial dopant of part is consumed
Layer 251 and the second initial dopant layer 252 form the first oxide layer 206 and the second oxide layer 207, remove 206 He of the first oxide layer
Second oxide layer 207, which is equivalent to, eliminates part the first initial dopant layer 251 and the second initial dopant layer 252, makes accordingly
It is formed by distance between the first doped layer 261 and the second doped layer 262 to increase, reduces the first doped layer 261 and second and mix
The connected probability of diamicton 262, improves the performance of device.
Correspondingly, the present embodiment also provides a kind of semiconductor devices formed using the above method.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor devices characterized by comprising
Semiconductor substrate is provided, there is adjacent the first fin and the second fin, the semiconductor lining in the semiconductor substrate
Also there is the separation layer of covering the first fin and the second fin partial sidewall on bottom；
The first initial dopant layer is formed on the first fin；
The second initial dopant layer is formed on the second fin, the second initial dopant layer is adjacent with the first initial dopant layer；
Oxidation processes are carried out to the first initial dopant layer and the second initial dopant layer, the first initial dopant layer is made to form the first doping
Layer and the first oxide layer positioned at the first doping layer surface make the second initial dopant layer form the second doped layer and are located at the
Second oxide layer of two doping layer surfaces；
Remove the first oxide layer and the second oxide layer.
2. the forming method of semiconductor devices as described in claim 1, which is characterized in that the first initial dopant layer and second
The technique that initial dopant layer carries out oxidation processes includes: dry oxidation technique or wet process oxidation technology.
3. the forming method of semiconductor devices as described in claim 1, which is characterized in that first oxide layer with a thickness of
10 angstroms~50 angstroms.
4. the forming method of semiconductor devices as described in claim 1, which is characterized in that removal first oxide layer and the
The technique of dioxide layer includes: dry etch process.
5. the forming method of semiconductor devices as described in claim 1, which is characterized in that formed the first initial dopant layer and
Before second initial dopant layer, it is developed across the first grid structure of the first fin on the semiconductor substrate and across second
The second grid structure of fin, the first grid structure cover the atop part surface and partial sidewall surface of the first fin,
The second grid structure covers the atop part surface and partial sidewall surface of the second fin.
6. the forming method of semiconductor devices as claimed in claim 5, which is characterized in that the shape of the first initial dopant layer
After including: the first grid structure for being developed across the first fin at step, formed in the fin of first grid structure two sides
First groove forms the first initial dopant layer in the first groove.
7. the forming method of semiconductor devices as claimed in claim 6, which is characterized in that form the first initial dopant layer
Technique include epitaxial growth technology.
8. the forming method of semiconductor devices as claimed in claim 7, which is characterized in that initial being epitaxially-formed first
During doped layer, further includes carrying out doping in situ to the first initial dopant layer, adulterated in the first initial dopant layer
First ion.
9. the forming method of semiconductor devices as claimed in claim 8, which is characterized in that when the first grid structure is used for
When forming P-type device, the material of the first initial dopant layer includes the SiGe doped with the first ion, the conduction type of the first ion
For p-type；When the first grid structure is used to form N-type device, the material of the first initial dopant layer includes doped with first
The silicon of ion, the conduction type of the first ion are N-type.
10. the forming method of semiconductor devices as claimed in claim 6, which is characterized in that formed first grid structure it
It afterwards, further include forming the first side wall on first grid structure side wall surface before the formation of the first groove.
11. the forming method of semiconductor devices as claimed in claim 10, which is characterized in that form it in first side wall
Afterwards, before the first groove is formed, ion implanting is carried out to the first fin of the gate structure and the first side wall two sides, forms the
One lightly doped district.
12. the forming method of semiconductor devices as claimed in claim 5, which is characterized in that form second on the second fin
The step of initial dopant layer includes: after being developed across the second grid structure of the second fin on second fin,
Two gate structure two sides form the second side wall；It is formed after the second side wall, the second fin of the second side wall sidewall surfaces is carried out
Ion implanting forms the second lightly-doped layer；After forming the second lightly-doped layer, the second groove is formed in the second side wall two sides；Second
The second initial dopant layer is formed in groove.
13. the forming method of semiconductor devices as claimed in claim 12, which is characterized in that form second initial dopant
The technique of layer includes epitaxial growth technology.It further include to described during being epitaxially-formed the second initial dopant layer
Two initial dopant layers carry out doping in situ；There is the second ion in second initial dopant layer.
14. the forming method of semiconductor devices as claimed in claim 13, which is characterized in that when the second grid structure is used
When forming P-type device, the material of the second initial dopant layer includes the SiGe doped with the second ion, the conductive-type of the second ion
Type is p-type；When the second grid structure is used to form N-type device, the material of the second initial dopant layer includes doped with
The silicon of two ions, the conduction type of the second ion are N-type.
15. the forming method of semiconductor devices as described in claim 1, which is characterized in that the semiconductor substrate includes depositing
Storage area and logic area have the first fin and the second fin on memory block, have third fin on logic area；The separation layer is also
On semiconductor substrate logic area and cover third fin partial sidewall；The forming method of the semiconductor devices is also wrapped
It includes: being developed across the third gate structure of third fin on the third fin, third gate structure covers third fin
Atop part surface and partial sidewall surface；Third groove is formed in third gate structure two sides；Is formed in third groove
Three source and drain doping layers.
16. the forming method of semiconductor devices as claimed in claim 15, which is characterized in that the semiconductor substrate logic area
On also have fourth fin adjacent with third fin；The separation layer is also located on semiconductor substrate logic area and covers the 4th
The partial sidewall of fin；The forming method of the semiconductor devices further include: be developed across the 4th fin on the 4th fin
4th gate structure in portion, the 4th gate structure cover the atop part surface and partial sidewall surface of the 4th fin；The 4th
Gate structure two sides form the 4th groove；The 4th source and drain doping layer is formed in the 4th groove.
17. the forming method of semiconductor devices as claimed in claim 16, which is characterized in that formed the first oxide layer it
Before, protective layer is formed on logic area；The forming step of the protective layer includes: at the beginning of the first initial dopant layer, second
Beginning doped layer, third source and drain doping layer and the 4th source and drain doping layer surface form protective film；Remove the first initial dopant layer and
Protective film on two initial dopant layers forms protective layer on third source and drain doping layer and the 4th source and drain doping layer.
18. the forming method of semiconductor devices as claimed in claim 16, which is characterized in that the protective layer with a thickness of 30
Angstrom~80 angstroms；The material of the protective layer includes: silica, silicon nitride, silicon oxynitride, silicon oxide carbide, carbonitride of silicium or carbon nitrogen
Silica.
19. the forming method of semiconductor devices as claimed in claim 16, which is characterized in that initially mix removal memory block first
The step of protective film on diamicton and the second initial dopant layer includes: that patterned layer is formed on protective film；With described graphical
Layer is exposure mask, the protective film of the first initial dopant layer and the second initial dopant layer surface on etching removal memory block.
20. a kind of according to claim 1 to the semiconductor devices that 19 any one methods are formed.
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| CN113497145A (en) * | 2020-04-01 | 2021-10-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method for forming semiconductor structure |
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