CN113497145A - Semiconductor structure and method for forming semiconductor structure - Google Patents

Semiconductor structure and method for forming semiconductor structure Download PDF

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CN113497145A
CN113497145A CN202010252067.XA CN202010252067A CN113497145A CN 113497145 A CN113497145 A CN 113497145A CN 202010252067 A CN202010252067 A CN 202010252067A CN 113497145 A CN113497145 A CN 113497145A
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layer
source
forming
opening
drain doping
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CN113497145B (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

A semiconductor structure and a forming method of the semiconductor structure are provided, wherein the method comprises the following steps: providing a substrate, wherein the substrate comprises a first area, the substrate is provided with a plurality of fin structures which are mutually separated, at least part of the fin structures are positioned in the first area, and the fin structures in the first area are internally provided with first source drain openings; forming an initial first source-drain doping layer in the first source-drain opening; forming dielectric layers on the substrate of the first area and the surface of the fin structure; forming a first opening in the dielectric layer; forming a first electrical interconnect layer within the first opening; forming a second opening penetrating through the first electrical interconnection layer and the initial first source-drain doping layer; and forming a first isolation structure in the second opening. Therefore, the performance of the semiconductor device is improved while the forming process of the semiconductor structure is simplified.

Description

Semiconductor structure and method for forming semiconductor structure
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in the integrated circuit is continuously reduced, so that the operation speed of the whole integrated circuit can be effectively increased.
In very large scale integrated circuits, the drive current of a transistor is typically increased by creating stress on the transistor, thereby increasing the carrier mobility of the transistor.
However, in the prior art, the steps of forming the semiconductor device are complicated, and the performance is to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, aiming at improving the performance of a semiconductor device while simplifying the forming process of the semiconductor structure.
To solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: the substrate comprises a first area, a plurality of fin structures which are mutually separated are arranged on the substrate, at least part of the fin structures are positioned in the first area, and first source drain openings are formed in the fin structures of the first area; the first source-drain doping layer is positioned in the first source-drain opening, and in the direction perpendicular to the extending direction of the fin structure, the first source-drain doping layer protrudes relative to the side wall of the fin structure; the dielectric layer is positioned on the substrate of the first region and the surface of the fin structure, a first opening is formed in the dielectric layer, and the first opening exposes the top surface of the first source-drain doping layer; a first electrical interconnect layer located within the first opening; the second openings are positioned in the first electric interconnection layer and between the side wall surfaces of the adjacent first source drain doping layers, the second openings penetrate through the first electric interconnection layer, and the first source drain doping layers positioned on two sides of the second openings are mutually separated; a first isolation structure located within the second opening.
Optionally, the material of the first isolation structure includes silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride.
Optionally, the material of the first electrical interconnect layer comprises a metal material.
Optionally, the substrate further includes a second region, at least a portion of the fin structure is located in the second region, and a second source-drain opening is formed in the fin structure of the second region; the semiconductor structure further includes: and the second source-drain doping layer is positioned in the second source-drain opening.
Optionally, the dielectric layer is further located on the substrate of the second region and the surface of the fin structure, and the first opening further exposes the top surface of the second source-drain doping layer.
Optionally, the first source-drain doped layer has first ions therein, the second source-drain doped layer has second ions therein, and the first ions and the second ions have opposite conductivity types.
Optionally, the first region is a pull-up device region of the sram, and the second region is a pull-down device region of the sram.
Optionally, the method further includes: and the first protective layer is positioned on the side wall surface of the second source drain doping layer, the surface of the fin structure in the first region and the surface of the fin structure in the second region.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a first area, the substrate is provided with a plurality of fin structures which are mutually separated, at least part of the fin structures are positioned in the first area, and the fin structures in the first area are internally provided with first source drain openings; forming an initial first source-drain doping layer in the first source-drain opening; forming dielectric layers on the substrate of the first area and the surface of the fin structure; forming a first opening in the dielectric layer, wherein the first opening exposes the top surface of the initial first source-drain doping layer; forming a first electrical interconnect layer within the first opening; forming a second opening penetrating through the first electrical interconnection layer and the initial first source-drain doping layer to form mutually-discrete first source-drain doping layers in the first source-drain openings on two sides of the second opening, wherein the first source-drain doping layers protrude relative to the side wall of the fin structure in the direction perpendicular to the extending direction of the fin structure; and forming a first isolation structure in the second opening.
Optionally, the method for forming the first opening includes: forming a first graphical layer on the surface of the dielectric layer, wherein the first graphical layer exposes the surface of the dielectric layer on the top surface of the initial first source-drain doping layer; and etching the dielectric layer by taking the first patterning layer as a mask until the top surface of the initial first source-drain doping layer is exposed.
Optionally, the process for etching the dielectric layer includes a dry etching process.
Optionally, the method for forming the second opening includes: forming a second patterned layer on the surface of the dielectric layer and the surface of the first electrical interconnection layer, wherein the second patterned layer exposes the surface of the first electrical interconnection layer between adjacent fin structures in the first region; and etching the first electrical interconnection layer and the initial first source-drain doping layer by taking the second patterning layer as a mask until the second patterning layer penetrates through the initial first source-drain doping layer.
Optionally, the process for etching the first electrical interconnection layer includes a dry etching process; and the process for etching the initial first source-drain doping layer comprises a dry etching process.
Optionally, the substrate further includes a second region, at least a portion of the fin structure is located in the second region, and a second source-drain opening is formed in the fin structure of the second region; the method for forming the semiconductor structure further comprises the following steps: and forming a second source-drain doping layer in the second source-drain opening before forming the initial first source-drain doping layer.
Optionally, the dielectric layer is further formed on the substrate of the second region and the surface of the fin structure, and the first opening further exposes the top surface of the second source-drain doping layer.
Optionally, the method further includes: and before the initial first source-drain doping layer is formed, forming a first protective layer on the side wall surface of the second source-drain doping layer, the surface of the fin structure in the first region and the surface of the fin structure in the second region.
Optionally, the dielectric layer includes: a first dielectric layer formed on the substrate of the first region and the surface of the side wall of the fin portion structure; and a second dielectric layer is formed on the surface of the first dielectric layer, the side wall and the top surface of the fin structure of the first region and the surface of the initial first source drain doping layer.
Optionally, the method for forming the dielectric layer includes: before forming an initial first source-drain doping layer, forming a first dielectric material layer on the substrate of the first region and the surface of the fin structure; etching the first dielectric material layer back until the top surface and part of the side wall surface of the fin part structure of the first area are exposed to form a first dielectric layer; and after the initial first source-drain doping layer is formed, forming a second dielectric layer on the surface of the first dielectric layer, the surface of the fin structure of the first region and the surface of the initial first source-drain doping layer.
Optionally, the method further includes: and before the second dielectric layer is formed, forming a second protective layer on the top surface of the initial first source-drain doping layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the method for forming the semiconductor structure according to the technical scheme of the invention, on one hand, after the initial first source-drain doping layer is formed, the mutually-separated first source-drain doping layers are formed through the second opening, and the first isolation structure is formed in the second opening, so that not only can the adjacent first source-drain doping layers be electrically isolated through the first isolation structure, but also the initial first source-drain doping layers can be less limited when formed, and therefore, in the direction perpendicular to the extending direction of the fin structure, the first source-drain doping layers protrude relative to the side wall of the fin structure, so that the volume of the formed first source-drain doping layers is larger, and further, the method is beneficial to improving the driving current of a transistor device and improving the performance of the semiconductor device. On the other hand, after the first electrical interconnection layer is formed, the second opening penetrating through the first electrical interconnection layer and the initial first source-drain doping layer is formed, and the first isolation structure is formed in the second opening, so that a mask layer for forming the opening penetrating through the first electrical interconnection layer and a mask layer for forming the opening penetrating through the initial first source-drain doping layer are reduced, and meanwhile, the process steps for forming the isolation structure in the opening in the first electrical interconnection layer and the opening in the initial first source-drain doping layer are simplified, and therefore the forming process of the semiconductor structure is simplified. In summary, after the first electrical interconnection layer is formed, the second opening penetrating through the first electrical interconnection layer and the initial first source-drain doping layer is formed, and the first isolation structure is formed in the second opening, so that the performance of the semiconductor device can be improved while the formation process of the semiconductor structure is simplified.
Drawings
FIGS. 1-5 are cross-sectional views of steps in the formation of a semiconductor structure;
fig. 6 to 15 are schematic cross-sectional views of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background, the performance of the semiconductor devices formed by the prior art needs to be improved. The analysis will now be described with reference to specific examples.
It should be noted that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 1 to 5 are schematic cross-sectional views of steps in a process of forming a semiconductor structure.
Referring to fig. 1 and 2, fig. 2 is a schematic cross-sectional view taken along a direction a-a1 of fig. 1, providing a substrate 10, the substrate 10 having a plurality of discrete fin structures 11 thereon; and forming a first dielectric layer 20 on the surface of the substrate 10 and on partial side wall surfaces of the fin structure 11.
The first dielectric layer 20 serves to electrically isolate the substrate 10 from other subsequently formed electrical devices.
Referring to fig. 3 and 4, fig. 3 is a schematic structural diagram based on fig. 2, and fig. 4 is a schematic structural diagram of a cross-section taken along a direction B-B1 in fig. 3, wherein a source/drain opening 12 is formed in the fin structure 11.
Referring to fig. 5 on the basis of fig. 4, a source-drain doping layer 30 is formed in each source-drain opening 12 by using an epitaxial growth process; a dielectric layer 40 is formed on the sidewall surface of each of the source doped layers 30.
The dielectric layer 40 is used to electrically isolate adjacent source drain doped layers 30.
In the above scheme, stress is formed on the transistor through the source-drain doping layer 30, so that the carrier mobility of the transistor is increased, and the driving current of the transistor is increased.
However, in order to electrically isolate adjacent transistor periods, when the source-drain doped layers 30 are formed, the adjacent source-drain doped layers 30 cannot be connected, and therefore, the size of the formed source-drain doped layers 30 is limited, that is, the volume of the formed source-drain doped layers 30 is small, so that the driving current of the transistor is still small, and the operation requirement of the integrated circuit cannot be met.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, in which a second opening penetrating through a first electrical interconnection layer and an initial first source-drain doping layer is formed after the first electrical interconnection layer is formed, and a first isolation structure is formed in the second opening, so that the performance of a semiconductor device can be improved while the formation process of the semiconductor structure is simplified.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 6 to 15 are schematic cross-sectional views of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 6 to 8, fig. 6 is a schematic top view, fig. 7 is a schematic cross-sectional view of fig. 6 along a direction X-X1, fig. 8 is a schematic cross-sectional view of fig. 6 along a direction Y-Y1, a substrate 100 is provided, the substrate 100 includes a first region I, the substrate 100 has a plurality of fin structures 110 separated from each other, and at least a portion of the fin structures 110 are located in the first region I.
The material of the substrate 100 comprises a semiconductor material.
In the present embodiment, the material of the substrate 100 includes silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
In another embodiment, the substrate has a device layer (not shown) therein. The device layer may include device structures, such as PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.
In this embodiment, the substrate 100 further includes a second region II, and at least a portion of the fin structure 110 is located in the second region II, and a second source/drain opening 112 is formed in the fin structure 110 of the second region II.
The second source-drain opening 112 provides a space for forming a second source-drain doped layer later.
In this embodiment, the first region I is a pull-up device region of the sram, and the second region II is a pull-down device region of the sram.
In another embodiment, the substrate does not include the second region.
In this embodiment, before forming the second source/drain opening 112, a first dielectric layer 210 is formed on the substrate 100 of the first region I and the second region II and on the sidewall surface of the fin structure 110.
The first dielectric layer 210 and a subsequently formed second dielectric layer are used together to form a dielectric layer.
The method for forming the first dielectric layer 210 includes: before an initial first source-drain doping layer is formed subsequently, a first dielectric material layer (not shown) is formed on the surfaces of the substrate 100 and the fin structure 110 in the first region I and the second region II; the first dielectric material layer is etched back until the top surfaces and a portion of the sidewall surfaces of the fin structures 110 in the first region I and the second region II are exposed, so as to form a first dielectric layer 210.
In this embodiment, the process of forming the first dielectric material layer includes a deposition process or a spin coating process.
In this embodiment, the process of etching back the first dielectric material layer includes a dry etching process or a wet etching process.
In this embodiment, the material of the first dielectric layer 210 includes one or a combination of silicon oxide and a high K (dielectric constant above 3.9) material.
Referring to fig. 9 on the basis of fig. 8, a second source/drain doping layer 300 is formed in the second source/drain opening 112.
In this embodiment, the second source-drain doping layer 300 has second ions therein.
In this embodiment, the material of the second source-drain doping layer 300 includes silicon, gallium arsenide, or indium gallium arsenide; the second ions are N-type ions and include phosphorus ions, arsenic ions, or antimony ions.
In this embodiment, the process of forming the second source-drain doping layer 300 includes an epitaxial growth process.
In this embodiment, after the second source-drain doping layer 300 is formed, a first protection material layer 400 is formed on the surface of the first dielectric layer 210, the surface of the second source-drain doping layer 300, the surface of the fin structure 110 in the first region I, and the surface of the fin structure 110 in the second region II.
The first protective material layer 400 provides a material for the subsequent formation of the first protective layer, and protects the second source-drain doping layer 300, so that the second source-drain doping layer 300 is less affected by the subsequent formation of the first source-drain doping layer and the first electrical interconnection layer.
In this embodiment, the material of the first protection material layer 400 includes silicon nitride.
In other embodiments, the material of the first protective material layer includes silicon oxide, silicon oxynitride, or silicon oxycarbide.
Referring to fig. 10, after the first protective material layer 400 is formed, a first source/drain opening 111 is formed in the fin structure 110 in the first region I.
The first source-drain opening 111 provides a space for forming an initial first source-drain doped layer subsequently.
In this embodiment, the method for forming the first source/drain opening 111 includes: after forming the first protection material layer 400, forming a third patterned layer 310 on the surface of the first protection material layer 400, where the third patterned layer 310 exposes a portion of the surface of the first protection material layer 400 on the fin structure 110 in the first region I; the first protective material layer 400 and the fin structure 110 in the first region I are etched using the third patterned layer 310 as a mask.
Referring to fig. 11, after the first source-drain opening 111 is formed, an initial first source-drain doping layer 500 is formed in the first source-drain opening 111.
The initial first source drain doping layer 500 provides material for the subsequent formation of the first source drain doping layer.
In this embodiment, the initial first source-drain doping layer 500 has first ions therein, and the conductivity types of the first ions and the second ions are opposite.
Specifically, in this embodiment, the material of the initial first source-drain doping layer 500 includes silicon, germanium or silicon germanium; the first ions are P-type ions including boron ions and BF2-Ions or indium ions.
In other embodiments, the material of the initial first source-drain doping layer includes silicon, gallium arsenide, or indium gallium arsenide; the first ions are N-type ions and comprise phosphorus ions, arsenic ions or antimony ions.
In this embodiment, the process of forming the initial first source-drain doping layer 500 includes an epitaxial growth process.
In this embodiment, after the initial first source-drain doping layer 500 is formed, the third patterning layer 310 is removed.
Referring to fig. 12, a dielectric layer 200 is formed on the surfaces of the substrate 100 and the fin structure 110 in the first region I.
In this embodiment, the dielectric layer 200 is further formed on the surfaces of the substrate 100 and the fin structure 110 in the second region II.
The dielectric layer 200 includes: the first dielectric layer 210; and forming a second dielectric layer 220 on the surface of the first dielectric layer 210, the sidewall and the top surface of the fin structure 110 in the first region I, the sidewall and the top surface of the fin structure 110 in the second region II, the surface of the initial first source-drain doping layer 500 and the surface of the second source-drain doping layer 300.
In this embodiment, the process of forming the second dielectric layer 220 includes a deposition process or a spin-on process.
In this embodiment, the material of the first dielectric layer 210 is the same as the material of the second dielectric layer 220.
In another embodiment, the material of the first dielectric layer 210 is different from the material of the second dielectric layer 220.
In this embodiment, before forming the second dielectric layer 220, a second passivation layer 600 is formed on the top surface of the initial first source/drain doping layer 500.
The second protection layer 600 is used for protecting the initial first source-drain doping layer 500, so as to reduce the influence of the etching process for forming the first opening on the initial first source-drain doping layer 500.
In this embodiment, the process of forming the second protective layer 600 includes a deposition process.
In this embodiment, the material of the second protection layer 600 includes silicon nitride.
In other embodiments, the material of the second protective layer comprises silicon oxide, silicon oxynitride, or silicon oxycarbide.
In another embodiment, the second protective layer is not formed.
Referring to fig. 13, a first opening 710 is formed in the dielectric layer 200, and the first opening 710 exposes the top surface of the initial first source-drain doping layer 500.
The method of forming the first opening 710 includes: forming a first patterned layer (not shown) on the surface of the dielectric layer 200, wherein the first patterned layer exposes the initial first source-drain doping layer 500 and the surface of the dielectric layer 200 on the top surface of the second source-drain doping layer 300; and etching the dielectric layer 200, the initial first protection layer 400 and the second protection layer 600 by using the first patterning layer as a mask until the top surface of the initial first source-drain doping layer 500 is exposed to form the first opening 710, and forming the first protection layer 410 on the side wall surface of the second source-drain doping layer 300, the surface of the fin structure 110 in the first region I and the surface of the fin structure 110 in the second region II.
In this embodiment, the process of etching the dielectric layer 200 includes a dry etching process.
In this embodiment, after the first opening 710 is formed, the first patterned layer is removed before the first electrical interconnect layer 800 is subsequently formed.
Referring to fig. 14, a first electrical interconnect layer 800 is formed within the first opening 710; forming a second opening 720 penetrating through the first electrical interconnection layer 800 and the initial first source-drain doping layer 500 to form mutually discrete first source-drain doping layers 510 in the first source-drain openings 111 on both sides of the second opening 720, wherein the first source-drain doping layers 510 protrude with respect to the sidewall of the fin structure 110 in a direction perpendicular to the extending direction of the fin structure 110.
After the initial first source-drain doping layer 500 is formed, the first source-drain doping layers 510 which are mutually separated are formed through the second opening 720, and a first isolation structure is formed in the second opening 720 subsequently, so that the adjacent first source-drain doping layers 510 can be electrically isolated through the first isolation structure, and meanwhile, the initial first source-drain doping layer 500 can be less limited when being formed, and therefore, in the direction perpendicular to the extending direction of the fin structure 110, the first source-drain doping layers 510 protrude relative to the side wall of the fin structure 110, so that the size of the formed first source-drain doping layers 510 is larger, the driving current of a transistor device is favorably improved, and the performance of the semiconductor device is improved.
Furthermore, after the first electrical interconnection layer 800 is formed, the second opening 720 penetrating through the first electrical interconnection layer 800 and the initial first source-drain doping layer 500 is formed, and the first isolation structure is subsequently formed in the second opening 720, so that the number of mask layers for forming the opening penetrating through the first electrical interconnection layer 800 and the opening penetrating through the initial first source-drain doping layer 500 is reduced, that is, an opening (the second opening 720) penetrating through the first electrical interconnection layer 800 and the initial first source-drain doping layer 500 is formed with one mask layer. Meanwhile, the subsequent process steps of forming the isolation structures in the opening in the first electrical interconnection layer 800 and the opening in the initial first source-drain doping layer 500 are simplified, so that the forming process of the semiconductor structure is simplified. In summary, after the first electrical interconnection layer 800 is formed, the second opening 720 penetrating through the first electrical interconnection layer 800 and the initial first source-drain doping layer 500 is formed, and then the first isolation structure is formed in the second opening 720, so that the performance of the semiconductor device can be improved while the formation process of the semiconductor structure is simplified.
In this embodiment, the method for forming the second opening 720 includes: forming a second patterned layer (not shown) on the surface of the dielectric layer 200 and the surface of the first electrical interconnect layer 800, the second patterned layer exposing the surface of the first electrical interconnect layer 800 between adjacent fin structures 110 in the first region I; and etching the first electrical interconnection layer 800 and the initial first source-drain doping layer 500 by using the second patterning layer as a mask until the second electrical interconnection layer penetrates through the initial first source-drain doping layer 500.
In this embodiment, the process of etching the first electrical interconnect layer 800 includes a dry etching process, and the gas used in the dry etching process includes: cl2、SF6And CH4。
In this embodiment, the process for etching the initial first source-drain doping layer includes a dry etching process, and the gas used in the dry etching process includes Cl2And HBr.
In the present embodiment, the process of forming the first electrical interconnect layer 800 includes a deposition process or an electroplating process.
In this embodiment, the material of the first electrical interconnect layer 800 includes a metal material, such as tungsten or titanium.
In this embodiment, after the second opening 720 is formed, the second patterned layer is removed before the first isolation structure is formed subsequently.
Referring to fig. 15, after forming the second opening 720, a first isolation structure 730 is formed in the second opening 720.
In this embodiment, the method of forming the first isolation structure 730 includes: forming an initial first isolation structure (not shown) within the second opening 720, on the surface of the dielectric layer 200, and on the surface of the first electrical interconnect layer 800; the initial first isolation structure is etched back until the surface of the dielectric layer 200 and the surface of the first electrical interconnect layer 800 are exposed.
In the present embodiment, the process of forming the initial first isolation structure includes a deposition process.
In this embodiment, the process of etching back the initial first isolation structure includes a dry etching process or a wet etching process.
In another embodiment, the initial first isolation structure is not etched back, and the initial first isolation structure is used as the first isolation structure.
In the present embodiment, the material of the first isolation structure 730 includes silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 15, including a substrate 100, where the substrate 100 includes a first region I, the substrate 100 has a plurality of fin structures 110 separated from each other, at least a portion of the fin structures 110 is located in the first region I, and the fin structures 110 in the first region I have first source-drain openings 111 therein; the first source-drain doping layer 510 is located in the first source-drain opening 111, and in a direction perpendicular to the extending direction of the fin structure 110, the first source-drain doping layer 510 protrudes relative to the sidewall of the fin structure 110; the dielectric layer 200 is located on the surfaces of the substrate 100 and the fin structure 110 in the first region I, a first opening 710 is formed in the dielectric layer 200, and the first opening 710 exposes the top surface of the first source drain doping layer 510; a first electrical interconnect layer 800 located within the first opening 710; the second openings 720 are located in the first electrical interconnection layer 800 and between the side wall surfaces of the adjacent first source-drain doping layers 510, the second openings 720 penetrate through the first electrical interconnection layer 800, and the first source-drain doping layers 510 located on two sides of the second openings 720 are mutually separated; a first isolation structure 730 located within the second opening 720.
The material of the substrate 100 comprises a semiconductor material.
In the present embodiment, the material of the substrate 100 includes silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
In another embodiment, the substrate has a device layer (not shown) therein. The device layer may include device structures, such as PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.
In this embodiment, the substrate 100 further includes a second region II, and at least a portion of the fin structure 110 is located in the second region II, and a second source/drain opening 112 is formed in the fin structure 110 of the second region II.
In this embodiment, the semiconductor structure further includes: and a second source-drain doped layer 300 located in the second source-drain opening 112.
In this embodiment, the first region I is a pull-up device region of the sram, and the second region II is a pull-down device region of the sram.
In another embodiment, the second region, the second source/drain opening, and the second source/drain doping layer are not included.
In this embodiment, the first source drain doped layer 510 has first ions therein, the second source drain doped layer 300 has second ions therein, and the conductivity types of the first ions and the second ions are opposite.
Specifically, in this embodiment, the material of the first source-drain doping layer 510 includes silicon, germanium, or silicon germanium; the first ions are P-type ions,the P-type ions include boron ions and BF2-Ions or indium ions. The material of the second source-drain doping layer 300 comprises silicon, gallium arsenide or indium gallium arsenide; the second ions are N-type ions and include phosphorus ions, arsenic ions, or antimony ions.
In other embodiments, the material of the first source-drain doping layer includes silicon, gallium arsenide, or indium gallium arsenide; the first ions are N-type ions and comprise phosphorus ions, arsenic ions or antimony ions.
In this embodiment, the dielectric layer 200 is further located on the surfaces of the substrate 100 and the fin structure 110 in the second region II, and the first opening 710 further exposes the top surface of the second source-drain doping layer 300.
Specifically, in this embodiment, the dielectric layer 200 includes: the first dielectric layers 210 are positioned on the surfaces of the sidewalls of the substrate 100 and the fin structure 110 in the first region I and the second region II; and the second dielectric layers 220 are positioned on the surface of the first dielectric layer 210, the side wall and the top surface of the fin structure 110 in the first region I, the side wall and the top surface of the fin structure 110 in the second region II, the surface of the first source-drain doping layer 510 and the surface of the second source-drain doping layer 300.
In this embodiment, the material of the first dielectric layer 210 includes one or a combination of silicon oxide and a high K (dielectric constant above 3.9) material.
In this embodiment, the material of the first dielectric layer 210 is the same as the material of the second dielectric layer 220.
In another embodiment, the material of the first dielectric layer 210 is different from the material of the second dielectric layer 220.
In this embodiment, the material of the first electrical interconnect layer 800 includes a metal material, such as tungsten or titanium.
In the present embodiment, the material of the first isolation structure 730 includes silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride.
In another embodiment, the first isolation structure is also located on the surface of the dielectric layer 200 and the surface of the first electrical interconnect layer 800.
In this embodiment, the semiconductor structure further includes: and the first protective layer 410 is positioned on the side wall surface of the second source-drain doping layer 300, the surface of the fin structure 110 in the first region I and the surface of the fin structure 110 in the second region II.
In the present embodiment, the material of the first protection layer 410 includes silicon nitride.
In other embodiments, the material of the first protective layer includes silicon oxide, silicon oxynitride, or silicon carbonitride.
In this embodiment, the semiconductor structure further includes: a first gate structure (not shown) on the surface of the fin structure 110 in the first region I, and a second gate structure (not shown) on the surface of the fin structure 110 in the second region II.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A semiconductor structure, comprising:
the substrate comprises a first area, a plurality of fin structures which are mutually separated are arranged on the substrate, at least part of the fin structures are positioned in the first area, and first source drain openings are formed in the fin structures of the first area;
the first source-drain doping layer is positioned in the first source-drain opening, and in the direction perpendicular to the extending direction of the fin structure, the first source-drain doping layer protrudes relative to the side wall of the fin structure;
the dielectric layer is positioned on the substrate of the first region and the surface of the fin structure, a first opening is formed in the dielectric layer, and the first opening exposes the top surface of the first source-drain doping layer;
a first electrical interconnect layer located within the first opening;
the second openings are positioned in the first electric interconnection layer and between the side wall surfaces of the adjacent first source drain doping layers, the second openings penetrate through the first electric interconnection layer, and the first source drain doping layers positioned on two sides of the second openings are mutually separated;
a first isolation structure located within the second opening.
2. The semiconductor structure of claim 1, wherein a material of the first isolation structure comprises silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride.
3. The semiconductor structure of claim 1, wherein a material of the first electrical interconnect layer comprises a metallic material.
4. The semiconductor structure of claim 1, wherein the substrate further comprises a second region, and wherein at least a portion of the fin structure is located in the second region, the fin structure of the second region having a second source drain opening therein; the semiconductor structure further includes: and the second source-drain doping layer is positioned in the second source-drain opening.
5. The semiconductor structure of claim 4, wherein the dielectric layer is further located on the substrate of the second region and the surface of the fin structure, and wherein the first opening further exposes the top surface of the second source-drain doped layer.
6. The semiconductor structure of claim 4, wherein the first source drain doped layer has first ions therein, the second source drain doped layer has second ions therein, and the first ions and the second ions are of opposite conductivity types.
7. The semiconductor structure of claim 4, wherein the first region is a pull-up device region of a static random access memory and the second region is a pull-down device region of the static random access memory.
8. The semiconductor structure of claim 4, further comprising: and the first protective layer is positioned on the side wall surface of the second source drain doping layer, the surface of the fin structure in the first region and the surface of the fin structure in the second region.
9. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first area, the substrate is provided with a plurality of fin structures which are mutually separated, at least part of the fin structures are positioned in the first area, and the fin structures in the first area are internally provided with first source drain openings;
forming an initial first source-drain doping layer in the first source-drain opening;
forming dielectric layers on the substrate of the first area and the surface of the fin structure;
forming a first opening in the dielectric layer, wherein the first opening exposes the top surface of the initial first source-drain doping layer;
forming a first electrical interconnect layer within the first opening;
forming a second opening penetrating through the first electrical interconnection layer and the initial first source-drain doping layer to form mutually-discrete first source-drain doping layers in the first source-drain openings on two sides of the second opening, wherein the first source-drain doping layers protrude relative to the side wall of the fin structure in the direction perpendicular to the extending direction of the fin structure;
and forming a first isolation structure in the second opening.
10. The method of forming a semiconductor structure of claim 9, wherein the method of forming the first opening comprises: forming a first graphical layer on the surface of the dielectric layer, wherein the first graphical layer exposes the surface of the dielectric layer on the top surface of the initial first source-drain doping layer; and etching the dielectric layer by taking the first patterning layer as a mask until the top surface of the initial first source-drain doping layer is exposed.
11. The method of forming a semiconductor structure of claim 10, wherein the process of etching the dielectric layer comprises a dry etching process.
12. The method of forming a semiconductor structure of claim 9, wherein the method of forming the second opening comprises: forming a second patterned layer on the surface of the dielectric layer and the surface of the first electrical interconnection layer, wherein the second patterned layer exposes the surface of the first electrical interconnection layer between adjacent fin structures in the first region; and etching the first electrical interconnection layer and the initial first source-drain doping layer by taking the second patterning layer as a mask until the second patterning layer penetrates through the initial first source-drain doping layer.
13. The method of forming a semiconductor structure of claim 12, wherein the process of etching the first electrical interconnect layer comprises a dry etch process; and the process for etching the initial first source-drain doping layer comprises a dry etching process.
14. The method for forming the semiconductor structure according to claim 9, wherein the substrate further comprises a second region, and at least a portion of the fin structure is located in the second region, and a second source/drain opening is formed in the fin structure of the second region; the method for forming the semiconductor structure further comprises the following steps: and forming a second source-drain doping layer in the second source-drain opening before forming the initial first source-drain doping layer.
15. The method for forming the semiconductor structure according to claim 14, wherein the dielectric layer is further formed on the substrate of the second region and the surface of the fin structure, and the first opening further exposes the top surface of the second source-drain doping layer.
16. The method of forming a semiconductor structure of claim 14, further comprising: and before the initial first source-drain doping layer is formed, forming a first protective layer on the side wall surface of the second source-drain doping layer, the surface of the fin structure in the first region and the surface of the fin structure in the second region.
17. The method of forming a semiconductor structure of claim 9, wherein the dielectric layer comprises: a first dielectric layer formed on the substrate of the first region and the surface of the side wall of the fin portion structure; and a second dielectric layer is formed on the surface of the first dielectric layer, the side wall and the top surface of the fin structure of the first region and the surface of the initial first source drain doping layer.
18. The method of forming a semiconductor structure of claim 17, wherein forming the dielectric layer comprises: before forming an initial first source-drain doping layer, forming a first dielectric material layer on the substrate of the first region and the surface of the fin structure; etching the first dielectric material layer back until the top surface and part of the side wall surface of the fin part structure of the first area are exposed to form a first dielectric layer; and after the initial first source-drain doping layer is formed, forming a second dielectric layer on the surface of the first dielectric layer, the surface of the fin structure of the first region and the surface of the initial first source-drain doping layer.
19. The method of forming a semiconductor structure of claim 18, further comprising: and before the second dielectric layer is formed, forming a second protective layer on the top surface of the initial first source-drain doping layer.
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