CN113972164A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN113972164A
CN113972164A CN202010724368.8A CN202010724368A CN113972164A CN 113972164 A CN113972164 A CN 113972164A CN 202010724368 A CN202010724368 A CN 202010724368A CN 113972164 A CN113972164 A CN 113972164A
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Prior art keywords
forming
source
drain doped
region
doped region
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Chinese (zh)
Inventor
刘盼盼
王彦
张海洋
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202010724368.8A priority Critical patent/CN113972164A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region; forming a first grid structure on the first region, forming first source-drain doped regions in the substrate at two sides of the first grid structure, and forming dielectric structures on the surface of the side wall and the surface of the top of the first grid structure on the substrate; forming a first opening exposing the surface of the first source drain doped region in the medium structure on the first region; forming an initial isolation layer on the sidewall surface and the bottom surface of the first opening; performing first ion implantation on the first source drain doped region; forming a mask layer exposing the first region on the substrate after the first ion implantation; performing second ion implantation on the first source-drain doped region by taking the mask layer as a mask; removing the mask layer after the second ion implantation; and after the mask layer is removed, the initial isolation layer is etched back until the surface of the first source-drain doped region is exposed, and a first isolation layer is formed on the side wall of the first opening. The performance of the semiconductor structure formed by the method is improved.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
The metal interconnection structure is an indispensable structure in a semiconductor device, and is used for realizing interconnection between an active region and an active region, interconnection between a transistor and a transistor, or interconnection between metal wires of different layers to complete signal transmission and control. Therefore, in a semiconductor manufacturing process, the formation of a metal interconnection structure has a great influence on the performance of a semiconductor device and the manufacturing cost of the semiconductor device. In order to increase the density of devices, the size of semiconductor devices in integrated circuits has been continuously reduced, and in order to achieve electrical connection of the respective semiconductor devices, a multi-layer interconnection structure is generally required.
Generally, in the back-end interconnection process of the semiconductor device manufacturing process, the first metal layer (M1) needs to form an electrical connection with the underlying active device structure (including the source drain region and the gate structure region). Therefore, before forming the first metal layer, it is generally necessary to form a Local Interconnect structure (Local Interconnect) of the semiconductor device in advance. The local interconnect structure includes: a zero-level metal layer (M0) electrically connected with the lower source drain region, and a zero-level gate metal layer (M0G) electrically connected with the gate structure.
However, the manufacturing process of the semiconductor structure having the local interconnect structure in the prior art is complicated, and the performance of the formed semiconductor structure is to be further improved.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which is used for improving the performance of the semiconductor structure with a local interconnection structure.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a first region; forming a first grid structure on the first region, forming a first source-drain doped region in the substrate at two sides of the first grid structure, and forming a dielectric structure on the substrate, wherein the dielectric structure is positioned on the surface of the side wall and the surface of the top of the first grid structure; forming a first opening in the medium structure on the first region, wherein the first opening exposes the surface of the first source drain doped region; forming an initial isolation layer on the sidewall surface and the bottom surface of the first opening; performing first ion implantation on the first source drain doped region; after first ion implantation is carried out, a mask layer is formed on the substrate, and the mask layer exposes the first area; performing second ion implantation on the first source drain doped region by taking the mask layer as a mask; after the second ion implantation is carried out, removing the mask layer; and after the mask layer is removed, etching the initial isolation layer until the surface of the first source-drain doped region is exposed, and forming a first isolation layer on the side wall of the first opening.
Optionally, the substrate further comprises a second region; the forming method further includes: and forming a second gate structure on the second region, forming second source-drain doped regions in the substrate at two sides of the second gate structure, and positioning the dielectric structures on the side wall surface and the top surface of the second gate structure.
Optionally, before the performing the first ion implantation, the method further includes: forming a second opening in the medium structure on the second region, wherein the second opening exposes the surface of the second source drain doped region; forming an initial isolation layer on the sidewall surface and the bottom surface of the second opening; the mask layer is also located in the second opening.
Optionally, the method further includes: and the first ion implantation process is also used for carrying out first ion implantation on the second source drain doped region.
Optionally, the first ions of the first ion implantation process include fourth main group ions or inert gas ions.
Optionally, after removing the mask layer, the method further includes: etching back the initial isolation layer on the second region until the surface of the second source-drain doped region is exposed, and forming a second isolation layer on the sidewall of the second opening; after a first isolation layer and a second isolation layer are formed, a first conductive structure is formed in the first opening, the first conductive structure is electrically connected with the first source drain doped region, a second conductive structure is formed in the second opening, and the second conductive structure is electrically connected with the second source drain doped region.
Optionally, the forming method of the mask layer includes: forming an initial mask layer on a substrate; and removing the initial mask layer on the first area to form the mask layer.
Optionally, the material of the first source-drain doped region includes silicon germanium; the material of the second source-drain doped region comprises carbon silicon.
Optionally, the second ions of the second ion implantation process include P-type ions, and the P-type ions include boron ions, boron-fluorine ions, or indium ions.
Optionally, the material of the mask layer includes photoresist.
Optionally, the process for removing the mask layer includes an ashing process, and a gas of the ashing process includes oxygen or a gas containing oxygen.
Optionally, the material of the initial isolation layer comprises a dielectric material, and the dielectric material comprises silicon nitride.
Optionally, the process of forming the initial isolation layer includes an atomic layer deposition process.
Optionally, after removing the mask layer and before forming the first isolation layer, the method further includes: and carrying out surface treatment on the initial isolation layer.
Optionally, the process of performing surface treatment on the initial isolation layer comprises a gas treatment process; the gas of the gas treatment process comprises a mixed gas of nitrogen and hydrogen.
Optionally, the forming method of the first gate structure, the second gate structure, the first source-drain doped region, the second source-drain doped region, and the dielectric structure includes: forming a first dummy gate structure on the first region of the substrate, and forming a second dummy gate structure on the second region of the substrate; forming a first source-drain doped region in the substrate on two sides of the first pseudo gate structure, and forming a second source-drain doped region in the substrate on two sides of the second pseudo gate structure; forming an initial dielectric structure on the substrate, wherein the initial dielectric structure is positioned on the side wall of the first dummy gate structure and the side wall of the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure, forming a first gate opening in the initial dielectric structure on the first region, and forming a second gate opening in the initial dielectric structure on the second region; forming a first gate structure in the first gate opening and forming a second gate structure in the second gate opening; after a first gate structure and a second gate structure are formed, the dielectric structure is located on the side wall surface and the top surface of the first gate structure, and the dielectric structure is located on the side wall surface and the top surface of the second gate structure.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the method for forming the semiconductor structure in the technical scheme, after the initial isolation layer is formed, first ion implantation is carried out on the first source-drain doped region, and then second ion implantation is carried out on the first source-drain doped region. The first ion implantation process enables a certain amount of first ions to be on the surface of the initial isolation layer, and the first ions are not easily affected by the subsequent formation of a mask layer, the second ion implantation process for the first source drain doping area and the removal of the mask layer, so that after the mask layer is removed, the initial isolation layer is modified to have a smaller volume expansion degree, and therefore, when the first opening is filled with a material of a conductive structure subsequently, the filling effect is less affected, and the formed conductive structure is enabled to be in better contact with the first source drain doping area.
Further, after second ion implantation, surface treatment is carried out on the initial isolation layer, the surface treatment can weaken the volume change condition of the initial isolation layer during the process of forming a mask layer, carrying out a second ion implantation process on the first source drain doping area and removing the mask layer, so that the filling effect is less influenced when the material of the conductive structure is filled in the first opening subsequently, and the formed conductive structure is better contacted with the first source drain doping area.
Drawings
FIGS. 1-3 are cross-sectional views illustrating a semiconductor structure forming process according to an embodiment;
fig. 4 to 11 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Detailed Description
As described in the background, the performance of the conventional back-end metal interconnection process and the semiconductor structure formed by the same still need to be improved. The analysis will now be described with reference to specific examples.
Fig. 1 to 3 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 includes a first region I and a second region II; forming a first gate structure 101 on the first region I and a second gate structure 102 on the second region II; forming first source-drain doped regions 103 in the substrate on two sides of the first gate structure 101; forming second source-drain doped regions 104 in the substrate on two sides of the second gate structure 102; forming a dielectric structure 105 on the substrate, wherein the dielectric structure 105 is positioned on the side wall of the first gate structure 101 and the side wall of the second gate structure 102; forming a first opening 106 in the dielectric structure 105 on the first region I, where the first opening 106 exposes the surface of the first source-drain doped region 103; and forming a second opening 107 in the dielectric structure 105 on the second region II, wherein the second opening 107 exposes the surface of the second source-drain doped region 104.
Referring to fig. 2, a first isolation layer 108 is formed on sidewalls of the first opening 106; a second isolation layer 109 is formed on sidewalls of the second opening 107.
Referring to fig. 3, a mask layer 110 is formed on a substrate, wherein the mask layer 110 exposes a first region I; and performing ion implantation on the first source-drain doped region 103 by using the mask layer 110 as a mask.
In the method for forming the semiconductor structure, the first region I is used to form a PMOS device, the second region II is used to form an NMOS device, the first isolation layer 108 is used to increase electrical isolation between a conductive structure formed in the first opening 106 and the first gate structure 101, and the material of the first isolation layer 108 includes a dielectric material, and the dielectric material is typically silicon nitride. After the ion implantation, the ion concentration of the surface of the first source-drain doped region 103 is higher, and when a conductive structure electrically connected with the first source-drain doped region 103 is formed in the first opening 106, the contact resistance between the conductive structure and the first source-drain doped region 103 is reduced.
However, in forming the mask layer 110 exposing the first region I, steps of exposure, development and etching are required, after the ion implantation is performed on the first source-drain doped region 103, the mask layer 110 needs to be removed, so that after the first isolation layer 108 is subjected to the above-mentioned exposure, development, etching, removal and ion implantation processes, the first isolation layer 108 is easily oxidized into the modified isolation layer 111, therefore, the volume of the modified isolation layer 111 is increased, so that the size of the first opening 106 in the modified isolation layer 111 is reduced, and when a metal material is deposited in the first opening 106 to form a conductive structure, the metal material is difficult to fill the surface of the first source drain doped region 103, therefore, the contact area between the formed conductive structure and the first source-drain doped region 103 is small, and the conductive effect between the conductive structure and the first source-drain doped region 103 is further affected.
In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming the semiconductor structure: the first ion implantation is carried out on the first source-drain doped region, and then the second ion implantation is carried out on the first source-drain doped region. The first ion implantation process enables a certain amount of first ions to be on the surface of the initial isolation layer, and the first ions are not easily affected by the subsequent formation of a mask layer, the second ion implantation process for the first source drain doping area and the removal of the mask layer, so that after the mask layer is removed, the initial isolation layer is modified to have a smaller volume expansion degree, and therefore, when the first opening is filled with a material of a conductive structure subsequently, the filling effect is less affected, and the formed conductive structure is enabled to be in better contact with the first source drain doping area.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 11 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 4, a substrate 200 is provided, the substrate 200 including a first region I.
In this embodiment, the substrate 200 further includes a second region II.
The first area I is used for forming PMOS devices subsequently, and the second area II is used for forming NMOS devices subsequently.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
Referring to fig. 5, a first gate structure 201 is formed on the first region I, a first source-drain doped region 203 is formed in the substrate 200 at two sides of the first gate structure 201, and a dielectric structure 205 is formed on the substrate 200, where the dielectric structure 205 is located on a sidewall surface and a top surface of the first gate structure 201.
In this embodiment, a second gate structure 202 is further formed on the second region II, a second source-drain doped region 204 is formed in the substrate 200 at two sides of the second gate structure 202, and the dielectric structure 205 is located on the sidewall surface and the top surface of the second gate structure 202.
In this embodiment, the material of the first source-drain doped region 203 includes silicon germanium; the material of the second source-drain doped region 204 includes carbon silicon.
The forming method of the first gate structure 201, the second gate structure 202, the first source-drain doped region 203, the second source-drain doped region 204 and the dielectric structure 205 comprises the following steps: forming a first dummy gate structure (not shown) on the first region I of the substrate 200, and forming a second dummy gate structure (not shown) on the second region II of the substrate 200; forming a first source-drain doped region 203 in the substrate 200 at two sides of the first dummy gate structure, and forming a second source-drain doped region 204 in the substrate 200 at two sides of the second dummy gate structure; forming an initial dielectric structure (not shown) on the substrate 200, wherein the initial dielectric structure is located on the first dummy gate structure side wall and the second dummy gate structure side wall; removing the first dummy gate structure and the second dummy gate structure, forming a first gate opening (not shown) in the initial dielectric structure on the first region I, and forming a second gate opening (not shown) in the initial dielectric structure on the second region II; forming a first gate structure 201 in the first gate opening, and forming a second gate structure 202 in the second gate opening; after the first gate structure 201 and the second gate structure 202 are formed, the dielectric structure 205 is located on the sidewall surface and the top surface of the first gate structure 201, and the dielectric structure 205 is located on the sidewall surface and the top surface of the second gate structure 202.
The first gate structure 201 includes: a first gate dielectric layer (not shown) and a first gate layer (not shown) on the first gate dielectric layer. In this embodiment, the first gate structure 201 further includes a first work function layer (not shown), and the first work function layer is located between the first gate dielectric layer and the first gate layer.
The material of the first gate dielectric layer comprises a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material comprises aluminum oxide or hafnium oxide; the material of the first gate layer comprises a metal, and the metal comprises tungsten; the material of the first work function layer comprises a P-type work function material, and the P-type work function material comprises titanium nitride or tantalum nitride.
The second gate structure 202 includes: a second gate dielectric layer (not shown) and a second gate layer (not shown) on the second gate dielectric layer. In this embodiment, the second gate structure 202 further includes a second work function layer (not shown), which is located between the second gate dielectric layer and the second gate layer.
The material of the second gate dielectric layer comprises a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material comprises aluminum oxide or hafnium oxide; the material of the second gate layer comprises a metal, and the metal comprises tungsten; the material of the second work function layer comprises an N-type work function material, and the N-type work function material comprises titanium aluminum.
The material of the dielectric structure 205 comprises a dielectric material comprising a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the dielectric structure 205 includes silicon oxide.
Referring to fig. 6, a first opening 206 is formed in the dielectric structure 205 on the first region I, and the first opening 206 exposes the surface of the first source-drain doped region 203.
In this embodiment, a second opening 207 is further formed in the dielectric structure 205 on the second region II while forming the first opening 206, and the second opening 207 exposes the surface of the second source/drain doped region 204.
The method for forming the first opening 206 and the second opening 207 includes: forming a patterning layer (not shown) on the dielectric structure 205, wherein the patterning layer exposes the dielectric structure 205 on the surface of the first source drain doped region 203 and exposes the dielectric structure 205 on the surface of the second source drain doped region 204; and etching the dielectric structure 205 by using the patterned layer as a mask until the surface of the first source-drain doped region 203 and the surface of the second source-drain doped region 204 are exposed, forming a first opening 206 in the dielectric structure 205 on the first region I, and forming a second opening 207 in the dielectric structure 205 on the second region II.
In this embodiment, the process for etching the dielectric structure 205 includes a dry etching process, and the dry etching process can obtain the first opening 206 and the second opening 207 with good sidewall morphology and high dimensional accuracy.
Referring to fig. 7, an initial isolation layer 208 is formed on the sidewall surface and the bottom surface of the first opening 206.
In the present embodiment, the initial isolation layer 208 is also formed on the sidewall surface and the bottom surface of the second opening 207.
The initial spacer layer 208 is used for subsequently forming a first spacer layer at the sidewalls of the first opening 206 and for forming a second spacer layer at the sidewalls of the second opening 207.
The material of the initial isolation layer 208 comprises a dielectric material comprising a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride.
In the present embodiment, the material of the initial isolation layer 208 includes silicon nitride.
The process of forming the initial isolation layer 208 includes an atomic layer deposition process or a chemical vapor deposition process. In the present embodiment, the process of forming the initial isolation layer 208 includes an atomic layer deposition process, which can form the initial isolation layer 208 with a dense structure and a thin thickness.
With reference to fig. 7, after the initial isolation layer 208 is formed, a first ion implantation process is performed on the first source/drain doped region 203.
In this embodiment, the first ion implantation process further performs ion implantation on the second source/drain doped region 204.
The first ion implantation process is used for performing amorphization treatment on the material of the first source-drain doped region 203 and the material of the second source-drain doped region 204, so that metal silicide is easily formed between the first conductive structure and the first source-drain doped region 203 and between the second conductive structure and the second source-drain doped region 204 in the follow-up process, and meanwhile, the quality of the formed metal silicide is good, so that the contact resistance between the first conductive structure and the first source-drain doped region 203 is reduced, the contact resistance between the second conductive structure and the second source-drain doped region 204 is reduced, and the conductive performance is improved.
The first ions of the first ion implantation process include fourth main group ions or inert gas ions.
In this embodiment, the first ions of the first ion implantation process include germanium ions.
First ion implantation is performed on the first source-drain doped region 203, and implanted ions of the first ion implantation process include germanium ions, so that the surface of the initial isolation layer 208 has a certain amount of germanium ions, and the germanium ions are not easily affected by the subsequent formation of a mask layer 209, the second ion implantation process performed on the first source-drain doped region 203, and the removal of the mask layer 209, so that after the mask layer 209 is removed, the initial isolation layer 208 is modified and has a small degree of volume expansion.
Referring to fig. 8, after the first ion implantation is performed, a mask layer 209 is formed on the substrate 200, and the mask layer 209 exposes the first region I.
In this embodiment, the mask layer 209 is also located in the second opening 207.
The forming method of the mask layer 209 includes: forming an initial mask layer (not shown) on the substrate 200; and removing the initial mask layer on the first area I to form the mask layer 209.
In this embodiment, the material of the mask layer 209 includes photoresist; the process of forming the mask layer 209 includes an exposure process and a development process.
With reference to fig. 8, a second ion implantation is performed on the first source/drain doped region 203 by using the mask layer 209 as a mask.
The second ion implantation process increases the ion concentration on the surface of the first source-drain doped region 203, so that the schottky barrier between the subsequently formed first conductive structure and the first source-drain doped region 203 can be reduced, the contact resistance between the first conductive structure and the first source-drain doped region 203 can be reduced, and the performance of the semiconductor structure can be improved.
The second ions of the second ion implantation process comprise P-type ions, and the P-type ions comprise boron ions, boron-fluorine ions or indium ions.
The second ions of the second ion implantation process include P-type ions, and the P-type ions can increase the number of holes in the first source-drain doped region 203, so that the hole mobility of a channel can be increased, and the performance of a device on the first region I can be improved.
Referring to fig. 9, after the second ion implantation, the mask layer 209 is removed.
In this embodiment, the process of removing the mask layer 209 includes an ashing process, and a gas of the ashing process includes oxygen or a gas containing oxygen.
The first ion implantation process enables the surface of the initial isolation layer 208 to have a certain amount of first ions, and the first ions are not susceptible to the subsequent formation of the mask layer 209, the second ion implantation process for the first source/drain doping region 203, and the removal of the mask layer 209, so that after the removal of the mask layer 209, the degree of volume expansion of the initial isolation layer 208 caused by oxidation is small, and therefore when the material of the conductive structure is filled in the first opening 206 in the subsequent process, the filling effect is less affected, and the first conductive structure formed in the first opening 206 is enabled to be in good contact with the first source/drain doping region 203.
With continued reference to fig. 9, after removing the mask layer 209, the method further includes: the initial isolation layer 208 on the first and second regions I and II is surface-treated.
The process of surface-treating the initial separation layer 208 includes a gas treatment process; the gas of the gas treatment process comprises a mixed gas of nitrogen and hydrogen.
The surface treatment can weaken the volume change condition of the initial isolation layer 208 on the first region I during the processes of forming the mask layer 209, performing the second ion implantation process on the first source/drain doped region 203 and removing the mask layer 209, so that the filling effect is less influenced when the material of the conductive structure is filled in the first opening 206 subsequently, and the first conductive structure formed in the first opening is better contacted with the first source/drain doped region 203.
In other embodiments, the process of surface treating the initial isolation layer comprises a wet treatment process.
In other embodiments, the initial isolation layer can be left untreated.
Referring to fig. 10, after the surface treatment is performed on the initial isolation layer 208, the initial isolation layer is etched back until the surfaces of the first source-drain doped region 203 and the second source-drain doped region 204 are exposed, a first isolation layer 210 is formed in the first opening 206, and a second isolation layer 211 is formed in the second opening 207.
The first isolation layer 210 is used to increase electrical isolation between a first conductive structure subsequently formed in the first opening 206 and the first gate structure 201, and the second isolation layer 211 is used to increase electrical isolation between a second conductive structure subsequently formed in the second opening 207 and the second gate structure 202.
Referring to fig. 11, after forming a first isolation layer 210 and a second isolation layer 211, a first conductive structure 212 is formed in the first opening 206, the first conductive structure 212 is electrically connected to the first source/drain doped region 203, a second conductive structure 213 is formed in the second opening 207, and the second conductive structure 213 is electrically connected to the second source/drain doped region 204.
The method for forming the first conductive structure 212 and the second conductive structure 213 comprises the following steps: forming a layer of conductive material (not shown) within the first opening 206, within the second opening 207, and over the dielectric structure 205; the conductive material layer is planarized until the surface of the dielectric structure 205 is exposed, a first conductive structure 212 is formed in the first opening 206, and a second conductive structure 213 is formed in the second opening 207.
The process for forming the conductive material layer includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In this embodiment, the process of forming the conductive material layer includes a chemical vapor deposition process.
Since the first ion implantation is performed on the first source-drain doped region 203 first, the surface of the initial isolation layer 208 has a certain amount of first ions due to the process of the first ion implantation, and the first ions are not easily affected by the formation of the mask layer 209, the second ion implantation process performed on the first source-drain doped region 203, and the removal of the mask layer 209, so that after the mask layer 209 is removed, the degree of volume expansion of the initial isolation layer 208 due to modification is small, and therefore when the first opening 206 is filled with a material of a conductive structure, the filling effect is less affected, and the first conductive structure 212 formed in the first opening 206 is better in contact with the first source-drain doped region 203.
After forming the first conductive structure 212 and the second conductive structure 213, the method further includes: annealing the first conductive structure 212 and the second conductive structure 213, and forming a metal silicide (not shown) between the first conductive structure 212 and the first source-drain doped region 203 and between the second conductive structure 213 and the second source-drain doped region 204, wherein the process for forming the metal silicide is a common technical means in the art and is not described herein again.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (16)

1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising a first region;
forming a first grid structure on the first region, forming a first source-drain doped region in the substrate at two sides of the first grid structure, and forming a dielectric structure on the substrate, wherein the dielectric structure is positioned on the surface of the side wall and the surface of the top of the first grid structure;
forming a first opening in the medium structure on the first region, wherein the first opening exposes the surface of the first source drain doped region;
forming an initial isolation layer on the sidewall surface and the bottom surface of the first opening;
performing first ion implantation on the first source drain doped region;
after first ion implantation is carried out, a mask layer is formed on the substrate, and the mask layer exposes the first area;
performing second ion implantation on the first source drain doped region by taking the mask layer as a mask;
after the second ion implantation is carried out, removing the mask layer;
and after the mask layer is removed, etching the initial isolation layer until the surface of the first source-drain doped region is exposed, and forming a first isolation layer on the side wall of the first opening.
2. The method of forming a semiconductor structure of claim 1, wherein the substrate further comprises a second region; the forming method further includes: and forming a second gate structure on the second region, forming second source-drain doped regions in the substrate at two sides of the second gate structure, and positioning the dielectric structures on the side wall surface and the top surface of the second gate structure.
3. The method of forming a semiconductor structure of claim 2, further comprising, prior to performing the first ion implantation: forming a second opening in the medium structure on the second region, wherein the second opening exposes the surface of the second source drain doped region; forming an initial isolation layer on the sidewall surface and the bottom surface of the second opening; the mask layer is also located in the second opening.
4. The method of forming a semiconductor structure of claim 3, further comprising: and the first ion implantation process is also used for carrying out first ion implantation on the second source drain doped region.
5. The method of claim 4, wherein the first ions of the first ion implantation process comprise fourth main group ions or inert gas ions.
6. The method of forming a semiconductor structure of claim 3, wherein after removing the mask layer, further comprising: etching back the initial isolation layer on the second region until the surface of the second source-drain doped region is exposed, and forming a second isolation layer on the sidewall of the second opening; after a first isolation layer and a second isolation layer are formed, a first conductive structure is formed in the first opening, the first conductive structure is electrically connected with the first source drain doped region, a second conductive structure is formed in the second opening, and the second conductive structure is electrically connected with the second source drain doped region.
7. The method of forming a semiconductor structure of claim 3, wherein the method of forming a mask layer comprises: forming an initial mask layer on a substrate; and removing the initial mask layer on the first area to form the mask layer.
8. The method for forming the semiconductor structure according to claim 2, wherein the material of the first source-drain doped region comprises silicon germanium; the material of the second source-drain doped region comprises carbon silicon.
9. The method of claim 8, wherein the second ions of the second ion implantation process comprise P-type ions, and the P-type ions comprise boron ions, boron-fluorine ions, or indium ions.
10. The method of claim 1, wherein the material of the mask layer comprises a photoresist.
11. The method of claim 10, wherein the process for removing the mask layer comprises an ashing process, and a gas of the ashing process comprises oxygen or a gas containing oxygen.
12. The method of forming a semiconductor structure of claim 1, wherein a material of the initial isolation layer comprises a dielectric material comprising silicon nitride.
13. The method of forming a semiconductor structure of claim 1, wherein the process of forming the initial isolation layer comprises an atomic layer deposition process.
14. The method of forming a semiconductor structure of claim 1, wherein after removing the mask layer and before forming the first isolation layer, further comprising: and carrying out surface treatment on the initial isolation layer.
15. The method of forming a semiconductor structure of claim 14, wherein the process of surface treating the initial isolation layer comprises a gas treatment process; the gas of the gas treatment process comprises a mixed gas of nitrogen and hydrogen.
16. The method for forming the semiconductor structure according to claim 2, wherein the method for forming the first gate structure, the second gate structure, the first source-drain doped region, the second source-drain doped region and the dielectric structure comprises: forming a first dummy gate structure on the first region of the substrate, and forming a second dummy gate structure on the second region of the substrate; forming a first source-drain doped region in the substrate on two sides of the first pseudo gate structure, and forming a second source-drain doped region in the substrate on two sides of the second pseudo gate structure; forming an initial dielectric structure on the substrate, wherein the initial dielectric structure is positioned on the side wall of the first dummy gate structure and the side wall of the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure, forming a first gate opening in the initial dielectric structure on the first region, and forming a second gate opening in the initial dielectric structure on the second region; forming a first gate structure in the first gate opening and forming a second gate structure in the second gate opening; after a first gate structure and a second gate structure are formed, the dielectric structure is located on the side wall surface and the top surface of the first gate structure, and the dielectric structure is located on the side wall surface and the top surface of the second gate structure.
CN202010724368.8A 2020-07-24 2020-07-24 Method for forming semiconductor structure Pending CN113972164A (en)

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CN113972164A true CN113972164A (en) 2022-01-25

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