CN113903811A - Semiconductor structure and method for forming semiconductor structure - Google Patents

Semiconductor structure and method for forming semiconductor structure Download PDF

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Publication number
CN113903811A
CN113903811A CN202010642695.9A CN202010642695A CN113903811A CN 113903811 A CN113903811 A CN 113903811A CN 202010642695 A CN202010642695 A CN 202010642695A CN 113903811 A CN113903811 A CN 113903811A
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forming
layer
sacrificial layer
substrate
semiconductor structure
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陈建
纪世良
王彦
张海洋
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202010642695.9A priority Critical patent/CN113903811A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

A semiconductor structure and a method for forming the same, the structure comprising: a substrate comprising a first region and a second region; a gate structure located on the substrate; source-drain doped regions in the substrate at two sides of the gate structure; the modified layer is positioned between the grid structures on the first region; and the sacrificial layer is positioned on the source-drain doped region between the grid structures on the second region. The performance of the semiconductor structure is improved.

Description

Semiconductor structure and method for forming semiconductor structure
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the development of the semiconductor manufacturing industry, there is a need for improvements in device performance (e.g., increased processing speed, increased storage capacity, etc.), increased battery life, and reduced manufacturing costs. To meet the above requirements, the semiconductor industry is constantly striving to reduce the size of semiconductor devices so that modern integrated circuits can include tens or hundreds of millions of semiconductor structures on a single semiconductor chip.
Typically, a semiconductor structure has conductive lines and conductive plugs therein for forming electrical connections between front end of line (FEOL) process components and back end of line (BEOL) process components to thereby implement electrical functions of the device.
However, as the size of semiconductor devices is continuously reduced, the difficulty of forming conductive layers and conductive plugs with smaller sizes is greater, and the performance of the formed semiconductor structure is also significantly reduced.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of the semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate comprising a first region and a second region; a gate structure located on the substrate; source-drain doped regions in the substrate at two sides of the gate structure; the modified layer is positioned between the grid structures on the first region; and the sacrificial layer is positioned on the source-drain doped region between the grid structures on the second region.
Optionally, the material of the modification layer includes silicon oxide.
Optionally, the material of the sacrificial layer includes a photosensitive material.
Optionally, the photoactive material comprises a crosslinkable organic material comprising silsesquioxane.
Optionally, the height of the sacrificial layer ranges from 10 nm to 50 nm.
Optionally, the method further includes: and the protective layer is positioned on the top of the gate structure.
Optionally, the material of the protective layer comprises a dielectric material.
Optionally, the substrate includes: a substrate; a fin structure on the substrate; and the isolation layer is positioned on the surface of the side wall of the partial fin structure.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate comprising a first region and a second region; forming a gate structure on a substrate, forming source-drain doped regions in the substrate on two sides of the gate structure, and forming an initial sacrificial layer on the substrate, wherein the initial sacrificial layer is positioned on the side wall of the gate structure; modifying the initial sacrificial layer on the first area, forming a modified layer on the first area, and forming a sacrificial layer on the second area; removing the sacrificial layer on the second area, and forming an opening between the grid electrode structures on the second area, wherein the opening exposes the surface of the source-drain doped area; and forming a conductive plug in the opening, wherein the conductive plug is electrically connected with the source drain doped region.
Optionally, the material of the initial sacrificial layer comprises a photosensitive material.
Optionally, the photoactive material comprises a crosslinkable organic material comprising silsesquioxane.
Optionally, the process of modifying the initial sacrificial layer on the first region includes an extreme ultraviolet exposure process or an electron beam exposure process.
Optionally, the process of forming the initial sacrificial layer includes a spin coating process.
Optionally, the material of the modification layer includes silicon oxide.
Optionally, the process of removing the sacrificial layer on the second region includes a wet etching process.
Optionally, the method for forming the initial sacrificial layer, the source-drain doped region, and the gate structure includes: forming a dummy gate structure on a substrate; forming source and drain doped regions in the substrate at two sides of the pseudo gate structure; forming a sacrificial material layer on the side wall of the pseudo gate structure; etching back the sacrificial material layer to form an initial sacrificial layer, wherein the initial sacrificial layer exposes part of the side wall of the pseudo gate structure, and the top surface of the initial sacrificial layer is lower than that of the pseudo gate structure; forming a dielectric layer on the initial sacrificial layer, wherein the dielectric layer is positioned on the side wall of the pseudo gate structure and exposes out of the top of the pseudo gate structure; removing the pseudo gate structure, and forming gate openings in the dielectric layer and the initial sacrificial layer; forming a grid structure material layer in the grid opening and on the dielectric layer; and flattening the grid structure material layer and the dielectric layer until the surface of the initial sacrificial layer is exposed to form the grid structure.
Optionally, after forming a dielectric layer on the initial sacrificial layer and before removing the dummy gate structure, the method further includes: annealing the dielectric layer, wherein the process parameters of the annealing include: the temperature is 200-600 ℃.
Optionally, the process for forming the source/drain doped region includes an epitaxial growth process.
Optionally, the height of the initial sacrificial layer ranges from 10 nm to 50 nm.
Optionally, after forming the gate structure, before modifying the initial sacrificial layer on the first region, the method further includes: a protective layer is formed atop the gate structure, the material of the protective layer comprising a dielectric material.
Optionally, the forming method of the protective layer includes: etching back the grid structure to form a groove in the initial sacrificial layer; and forming the protective layer in the groove.
Optionally, the substrate includes: a substrate; a fin structure on the substrate; and the isolation layer is positioned on the surface of the side wall of the partial fin structure.
Optionally, the material of the conductive plug includes a metal, and the metal includes: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the semiconductor structure in the technical scheme of the invention, the first region is provided with the modification layer, the second region is provided with the sacrificial layer, and the sacrificial layer is easy to remove and clean, so that an opening exposing the surface of the source-drain doped region with a larger area can be formed on the second region, the contact area between the conductive plug and the source-drain doped region formed in the opening subsequently is larger, and the contact resistance between the conductive plug and the source-drain doped region is reduced.
Further, the material of the sacrificial layer comprises a photosensitive material, the photosensitive material comprises a cross-linkable organic material, the cross-linkable organic material comprises silsesquioxane, and the material of the modification layer comprises silicon oxide. The oxygen-silicon sesqui-oxiranes can generate chemical reaction to form silicon oxide under the extreme ultraviolet exposure process or the electron beam exposure process, so that the modified layer on the first area can be reserved as a dielectric layer, meanwhile, the sacrificial layer on the second area is easy to remove, and an opening exposing the surface of the source drain doped area with a large area can be formed in the second area.
According to the forming method of the semiconductor structure in the technical scheme, an initial sacrificial layer is formed on a substrate and is located on the side wall of a grid structure, the initial sacrificial layer on a first area is modified, a modified layer is formed on the first area, a sacrificial layer is formed on a second area, then the sacrificial layer on the second area is removed, an opening exposing the surface of a source-drain doped area is formed between grid structures on the second area, and finally a conductive plug electrically connected with the source-drain doped area is formed in the opening. In the method, the sacrificial layer is easy to remove completely, so that the formed opening exposes the surface of the source-drain doped region with a larger area, the contact area between the conductive plug formed in the opening and the source-drain doped region is larger, and the contact resistance between the conductive plug and the source-drain doped region is reduced; meanwhile, the damage to the side wall of the gate structure is small in the process of forming the opening, so that the performance of the semiconductor structure is improved.
Furthermore, the material of the initial sacrificial layer comprises a photosensitive material, the photosensitive material comprises a crosslinkable organic material, the crosslinkable organic material comprises oxygen silsesquioxane, and the oxygen silsesquioxane can perform chemical reaction under an extreme ultraviolet exposure process or an electron beam exposure process to form silicon oxide, so that a modified layer formed on the first region of the initial sacrificial layer can be reserved as a dielectric layer, and meanwhile, the sacrificial layer on the second region is easy to remove completely, so that an opening exposing the surface of the source drain doped region with a larger area can be formed in the second region.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor structure in one embodiment;
fig. 2 to 9 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Detailed Description
As described in the background, the existing formation processes of the conductive layer and the conductive plug degrade the performance of the formed semiconductor structure. The analysis will now be described with reference to specific examples.
FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment.
Please refer to fig. 1, which includes: a substrate 100; a plurality of gate structures 103 located on the substrate 100; source-drain doped regions 101 located in the substrate 100 on both sides of the gate structure 103; a dielectric layer 102 located on the substrate 100, wherein the dielectric layer 102 is located on a sidewall of the gate structure 103; and the conductive plug 104 is positioned in the dielectric layer 102, and the conductive plug 104 is electrically connected with the source-drain doped region 101.
In the semiconductor structure, the gate structure 103 has a sidewall (not shown). In the process of forming the conductive plug 104, an opening (not shown) exposing the surface of the source/drain doped region 101 needs to be formed in the dielectric layer 102, and as the size of the semiconductor structure becomes smaller, the requirement on the size accuracy of the opening becomes higher; meanwhile, in the process of etching the dielectric layer 102, the sidewall of the gate structure 103 is easily damaged by the etching process, so that the formed opening exposes the sidewall of the gate structure 103, and the subsequently formed conductive plug 104 is easily in contact with the gate structure 103 to generate a short circuit. In order to avoid the short circuit between the conductive plug 104 and the gate structure 103, the formed opening only exposes a portion of the surface of the source/drain doped region 101, and a dielectric layer with a certain thickness is retained on the sidewall of the opening to electrically isolate the conductive plug 104 from the gate structure 103, thereby ensuring that the gate structure 103 is not damaged by the etching process.
However, the opening only exposes a portion of the surface of the source-drain doped region 101, so that the contact area between the conductive plug 104 formed in the opening and the source-drain doped region 101 is small, and the contact resistance between the conductive plug 104 and the source-drain doped region 101 is large, thereby affecting the performance of the semiconductor structure.
In order to solve the problems, the technical scheme of the invention provides a semiconductor structure and a forming method of the semiconductor structure, an initial sacrificial layer is formed on a substrate, the initial sacrificial layer is positioned on the side wall of a grid structure, the initial sacrificial layer on a first area is modified, a modified layer is formed on the first area, a sacrificial layer is formed on a second area, the sacrificial layer on the second area is removed, an opening exposing the surface of a source-drain doped area is formed between grid structures on the second area, and finally a conductive plug electrically connected with the source-drain doped area is formed in the opening. In the method, the sacrificial layer is easy to remove completely, so that the formed opening exposes the surface of the source-drain doped region with a larger area, the contact area between the conductive plug formed in the opening and the source-drain doped region is larger, and the contact resistance between the conductive plug and the source-drain doped region is reduced; meanwhile, the damage to the side wall of the gate structure is small in the process of forming the opening, so that the performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 9 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 2, a substrate 200 is provided, wherein the substrate 200 includes a first region I and a second region II.
In the present embodiment, the substrate 200 is a planar substrate.
In other embodiments, the substrate comprises: a substrate; a fin structure on the substrate; and the isolation layer is positioned on the surface of the side wall of the partial fin structure.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.
Next, a gate structure is formed on the substrate 200, source-drain doped regions are formed in the substrate on both sides of the gate structure, and an initial sacrificial layer is formed on the substrate, where the initial sacrificial layer is located on the sidewall of the gate structure. Fig. 3 to fig. 6 are referred to for a specific process of forming the gate structure, the source-drain doped region, and the initial sacrificial layer.
Referring to fig. 3, a dummy gate structure 201 is formed on a substrate 200.
The dummy gate structure 201 includes a dummy gate dielectric layer (not shown) and a dummy gate layer (not shown) on the dummy gate dielectric layer.
The forming method of the dummy gate structure 201 comprises the following steps: forming a dummy gate dielectric material layer (not shown) on the substrate 200; forming a dummy gate material layer (not shown) on the dummy gate dielectric material layer; forming a patterned mask layer (not shown) on the dummy gate material layer; and etching the pseudo gate material layer and the pseudo gate dielectric material layer by taking the patterned mask layer as a mask until the surface of the substrate is exposed to form the pseudo gate structure 201.
The material of the pseudo gate dielectric layer comprises silicon oxide or low-K (K is less than 3.9) material; the material of the dummy gate layer comprises polysilicon.
In this embodiment, the method further includes: sidewall structures (not shown) on sidewalls of the dummy gate structures 201.
The material of the side wall structure comprises a dielectric material, and the dielectric material comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride and the like. In this embodiment, the material of the sidewall spacer structure includes silicon nitride.
With reference to fig. 3, after forming the sidewall structures, source/drain doped regions 202 are formed in the substrate 200 at two sides of the dummy gate structure 201.
In the present embodiment, the process of forming the source/drain doped region 202 includes an epitaxial growth process.
The source-drain doped region 202 is internally provided with source-drain doped ions, and the type of the source-drain doped ions is N type or P type; the N-type ions comprise phosphorus ions, arsenic ions and the like; the P-type ions include boron ions, indium ions, or the like.
With continued reference to fig. 3, an initial sacrificial layer 203 is formed on the sidewalls of the dummy gate structure 201.
The method for forming the initial sacrificial layer 203 comprises the following steps: forming a sacrificial material layer (not shown) on the sidewalls of the dummy gate structure 201; and etching back the sacrificial material layer to form an initial sacrificial layer 203, wherein the initial sacrificial layer 203 exposes a part of the side wall of the dummy gate structure 201, and the top surface of the initial sacrificial layer 203 is lower than the top surface of the dummy gate structure 201.
The height of the initial sacrificial layer 203 ranges from 10 nm to 50 nm. The height of the initial sacrificial layer 203 defines the height of subsequently formed gate structures.
The material of the initial sacrificial layer 203 comprises a photosensitive material.
In this embodiment, the photoactive material comprises a crosslinkable organic material comprising silsesquioxane.
The material of the initial sacrificial layer 203 comprises a photosensitive material which comprises a cross-linkable organic material, so that a sacrificial layer formed on the second region II in the following process is easy to remove, the formed opening exposes the surface of a source-drain doped region with a large area, the contact area between the conductive plug formed in the opening and the source-drain doped region is large, and the contact resistance between the conductive plug and the source-drain doped region is reduced; meanwhile, the damage to the side wall of the gate structure is small in the process of forming the opening, so that the performance of the semiconductor structure is improved.
The material of the initial sacrificial layer 203 comprises oxygen silsesquioxane, and the oxygen silsesquioxane can generate chemical reaction under an extreme ultraviolet exposure process or an electron beam exposure process to form silicon oxide, so that a modified layer formed on the first region I by the initial sacrificial layer 203 can be reserved as a dielectric layer, and meanwhile, the sacrificial layer on the second region II can be easily and cleanly removed, so that an opening exposing the surface of the source drain doped region 202 with a large area can be formed on the second region II, and the condition that the surface of the source drain doped region is exposed by the formed opening when the dielectric layer is formed on the first region I and the second region II and then removed on the second region I is improved.
In this embodiment, the process of forming the sacrificial material layer includes a spin coating process.
Referring to fig. 4, a dielectric layer 204 is formed on the initial sacrificial layer 203, wherein the dielectric layer 204 is located on the sidewall of the dummy gate structure 201, and the dielectric layer 204 exposes the top of the dummy gate structure 201.
The forming method of the dielectric layer 204 comprises the following steps: forming a dielectric material layer (not shown) on the initial sacrificial layer 203; and flattening the dielectric material layer until the top surface of the dummy gate structure 201 is exposed to form the dielectric layer 204.
The material of the dielectric layer 204 comprises a dielectric material comprising silicon oxide.
The process for forming the dielectric material layer comprises a chemical vapor deposition process or an atomic layer deposition process.
With reference to fig. 4, the dielectric layer 204 is annealed, and the process parameters of the annealing include: the temperature is 200-600 ℃.
The annealing treatment has less influence on the initial sacrificial layer 203.
Referring to fig. 5, after forming the dielectric layer 204, the dummy gate structure 201 is removed, and a gate opening (not shown) is formed in the dielectric layer 204 and the initial sacrificial layer 203; a layer of gate structure material 205 is formed within the gate opening and on the dielectric layer 204.
The process for removing the dummy gate structure 201 includes one or more of a dry etching process and a wet etching process.
The gate structure material layer 205 includes: a layer of gate dielectric material (not shown); a gate material layer (not shown) on the gate dielectric material layer.
In this embodiment, the gate structure material layer 205 further includes a work function material layer (not shown) between the gate dielectric material layer and the gate material layer.
The gate dielectric material layer provides a material layer for the gate dielectric layer; the work function material layer provides a material layer for the work function layer; the gate material layer provides a material layer for the gate layer.
Referring to fig. 6, the gate structure material layer 205 and the dielectric layer 204 are planarized until the surface of the initial sacrificial layer 203 is exposed, so as to form the gate structure 206.
The gate structure 206 includes: a gate dielectric layer (not shown) and a gate layer (not shown) on the gate dielectric layer.
The gate structure 206 further includes a work function layer (not shown) between the gate dielectric layer and the gate layer.
The gate dielectric layer comprises a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material comprises aluminum oxide or hafnium oxide; the material of the gate layer comprises a metal, and the metal comprises tungsten; the material of the work function layer comprises an N-type work function material or a P-type work function material, the N-type work function material comprises titanium aluminum, and the P-type work function material comprises titanium nitride or tantalum nitride and the like.
With continued reference to fig. 6, after the gate structure is formed, a protection layer (not shown) is formed on top of the gate structure 206.
The forming method of the protective layer comprises the following steps: etching back the gate structure 206 to form a groove (not shown) in the initial sacrificial layer 203; and forming the protective layer in the groove.
The material of the protective layer comprises a dielectric material, and the dielectric material comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, silicon oxycarbonitride and the like.
Referring to fig. 7, the initial sacrificial layer 203 on the first region I is modified to form a modified layer 207 on the first region I and a sacrificial layer 208 on the second region II.
The method for performing modification treatment on the initial sacrificial layer 203 on the first region I includes: forming a mask layer 300 on the substrate, wherein the mask layer 300 exposes the surface of the initial sacrificial layer 203 on the first region I; and modifying the initial sacrificial layer 203 on the first region I by using the mask layer 300 as a mask.
The process of modifying the initial sacrificial layer 203 on the first region I includes an extreme ultraviolet exposure process or an electron beam exposure process.
The extreme ultraviolet exposure process enables the oxygen silsesquioxane to generate a chemical reaction to form silicon oxide, so that the modified layer 207 formed on the first region I by the initial sacrificial layer 203 can be reserved as a dielectric layer, and meanwhile, the sacrificial layer 208 on the second region II is easy to remove completely, so that an opening exposing the surface of the source drain doped region 202 with a large area can be formed in the second region II.
The technological parameters of the extreme ultraviolet exposure process comprise: the light intensity cumulative dose range is 20 mj/cm.
The electron beam exposure process enables the silsesquioxane to generate a chemical reaction to form silicon oxide, so that the modified layer 207 formed on the first region I by the initial sacrificial layer 203 can be reserved as a dielectric layer, and meanwhile, the sacrificial layer 208 on the second region II is easy to remove, so that an opening exposing the surface of the source/drain doped region 202 with a large area can be formed in the second region II.
The process parameters of the electron beam exposure process comprise: the electron dose range was 100 microjoules per square centimeter.
In this embodiment, the material of the modification layer 207 includes silicon oxide.
In this embodiment, the material of the mask layer 300 includes photoresist.
In this embodiment, after the modified layer 207 is formed, the mask layer 300 is removed.
The process of removing the mask layer 300 includes an ashing process.
Referring to fig. 8, the sacrificial layer 208 on the second region II is removed, and an opening 209 is formed between the gate structures 206 on the second region II, where the opening 209 exposes the surface of the source/drain doped region 202.
The process of removing the sacrificial layer 208 on the second region II includes one or more of a wet etching process and a dry etching process.
In this embodiment, the process of removing the sacrificial layer 208 on the second region II includes a wet etching process, and an etching solution of the wet etching process includes hydrofluoric acid.
The wet etching process has a large etching selection ratio of the modified layer 207 to the sacrificial layer 208, and can remove the sacrificial layer 208 cleanly, so that an opening 209 exposing the surface of the source-drain doped region 202 with a large area can be obtained, and when a conductive plug is formed in the opening 209 subsequently, the conductive plug has a large contact area with the source-drain doped region 202, so that the contact resistance of the conductive plug and the source-drain doped region 202 is small; meanwhile, in the process of forming the opening 209, the wet etching process has less damage to the sidewall of the gate structure 206, thereby improving the performance of the semiconductor structure.
Referring to fig. 9, a conductive plug 210 is formed in the opening 209, and the conductive plug 210 is electrically connected to the source/drain doped region 202.
The material of the conductive plug 210 includes a metal including: copper, aluminum, tungsten, cobalt, titanium nitride and the like.
The method for forming the semiconductor structure comprises the steps of forming an initial sacrificial layer 203 on a substrate 200, enabling the initial sacrificial layer 203 to be located on the side wall of a gate structure 206, modifying the initial sacrificial layer 203 on a first area I, forming a modified layer 207 on the first area I, forming a sacrificial layer 208 on a second area II, removing the sacrificial layer 208 on the second area II, forming an opening 209 exposing the surface of a source-drain doped region 202 between the gate structures 206 on the second area II, and finally forming a conductive plug electrically connected with the source-drain doped region 202 in the opening. In the method, the sacrificial layer 208 is easily removed, so that the formed opening 209 exposes the surface of the source/drain doped region 202 with a larger area, the contact area between the conductive plug 210 formed in the opening 209 and the source/drain doped region 202 is larger, and the contact resistance between the conductive plug 210 and the source/drain doped region 202 is reduced; meanwhile, the damage to the sidewall of the gate structure 206 is small in the process of forming the opening 209, thereby improving the performance of the semiconductor structure.
Accordingly, an embodiment of the present invention further provides a semiconductor structure, please refer to fig. 7, which includes:
a substrate 200, the substrate 200 comprising a first region I and a second region II;
a gate structure 206 located on the substrate 200;
source-drain doped regions 202 located in the substrate 200 at both sides of the gate structure 206;
a modified layer 207 between the gate structures 206 on the first region I;
and a sacrificial layer 208 located on the source-drain doped region 202 between the gate structures 206 on the second region II.
In this embodiment, the material of the modification layer 207 includes silicon oxide.
In this embodiment, the material of the sacrificial layer 208 includes a photosensitive material.
In this embodiment, the photoactive material comprises a crosslinkable organic material comprising silsesquioxane.
In the present embodiment, the height of the sacrificial layer 208 ranges from 10 nm to 50 nm.
In this embodiment, the gate structure 206 includes: a gate dielectric layer (not shown) and a gate layer (not shown) on the gate dielectric layer.
In this embodiment, the gate structure 206 further includes a work function layer (not shown) between the gate dielectric layer and the gate electrode layer.
In this embodiment, the method further includes: a protective layer (not shown) on top of the gate structure 206.
In this embodiment, the material of the protection layer includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, silicon oxycarbonitride, and combinations thereof.
In this embodiment, the method further includes: and a sidewall structure on the sidewall of the gate structure 206.
In other embodiments, the substrate 200 includes: a substrate; a fin structure on the substrate; and the isolation layer is positioned on the surface of the side wall of the partial fin structure.
In the semiconductor structure, the first region I is provided with the modification layer 207, the second region II is provided with the sacrificial layer 208, and the sacrificial layer 208 is easy to remove, so that an opening exposing a larger area of the surface of the source/drain doped region 202 can be formed on the second region II, and thus the contact area between the conductive plug formed in the opening and the source/drain doped region 202 is larger, and the contact resistance between the conductive plug and the source/drain doped region is reduced.
Further, the material of the sacrificial layer 208 includes a photosensitive material, the photosensitive material includes a cross-linkable organic material, the cross-linkable organic material includes silsesquioxane, and the material of the modification layer 207 includes silicon oxide. The silsesquioxane can perform chemical reaction under an extreme ultraviolet exposure process or an electron beam exposure process to form silicon oxide, so that the modified layer 207 on the first region I can be reserved as a dielectric layer, and meanwhile, the sacrificial layer 208 on the second region II is easy to remove, so that an opening exposing the surface of the source/drain doped region 202 with a large area can be formed in the second region II.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (23)

1. A semiconductor structure, comprising:
a substrate comprising a first region and a second region;
a gate structure located on the substrate;
source-drain doped regions in the substrate at two sides of the gate structure;
the modified layer is positioned between the grid structures on the first region;
and the sacrificial layer is positioned on the source-drain doped region between the grid structures on the second region.
2. The semiconductor structure of claim 1, wherein a material of the modification layer comprises silicon oxide.
3. The semiconductor structure of claim 1, in which a material of the sacrificial layer comprises a photosensitive material.
4. The semiconductor structure of claim 3, wherein the photoactive material comprises a cross-linkable organic material comprising silsesquioxane.
5. The semiconductor structure of claim 1, wherein the sacrificial layer has a height in a range from 10 nanometers to 50 nanometers.
6. The semiconductor structure of claim 1, further comprising: and the protective layer is positioned on the top of the gate structure.
7. The semiconductor structure of claim 6, in which a material of the protective layer comprises a dielectric material.
8. The semiconductor structure of claim 1, wherein the substrate comprises: a substrate; a fin structure on the substrate; and the isolation layer is positioned on the surface of the side wall of the partial fin structure.
9. A method of forming a semiconductor structure, comprising:
providing a substrate comprising a first region and a second region;
forming a gate structure on a substrate, forming source-drain doped regions in the substrate on two sides of the gate structure, and forming an initial sacrificial layer on the substrate, wherein the initial sacrificial layer is positioned on the side wall of the gate structure;
modifying the initial sacrificial layer on the first area, forming a modified layer on the first area, and forming a sacrificial layer on the second area;
removing the sacrificial layer on the second area, and forming an opening between the grid electrode structures on the second area, wherein the opening exposes the surface of the source-drain doped area;
and forming a conductive plug in the opening, wherein the conductive plug is electrically connected with the source drain doped region.
10. The method of forming a semiconductor structure of claim 9, wherein the material of the initial sacrificial layer comprises a photosensitive material.
11. The method of forming a semiconductor structure of claim 10, wherein the photoactive material comprises a cross-linkable organic material comprising silsesquioxane.
12. The method of claim 11, wherein the process of modifying the initial sacrificial layer on the first region comprises an extreme ultraviolet exposure process or an electron beam exposure process.
13. The method of forming a semiconductor structure of claim 11, wherein the process of forming the initial sacrificial layer comprises a spin-on process.
14. The method of forming a semiconductor structure of claim 11, wherein a material of the modification layer comprises silicon oxide.
15. The method of forming a semiconductor structure of claim 9, wherein the process of removing the sacrificial layer over the second region comprises a wet etch process.
16. The method for forming the semiconductor structure according to claim 9, wherein the method for forming the initial sacrificial layer, the source-drain doped region and the gate structure comprises: forming a dummy gate structure on a substrate; forming source and drain doped regions in the substrate at two sides of the pseudo gate structure; forming a sacrificial material layer on the side wall of the pseudo gate structure; etching back the sacrificial material layer to form an initial sacrificial layer, wherein the initial sacrificial layer exposes part of the side wall of the pseudo gate structure, and the top surface of the initial sacrificial layer is lower than that of the pseudo gate structure; forming a dielectric layer on the initial sacrificial layer, wherein the dielectric layer is positioned on the side wall of the pseudo gate structure and exposes out of the top of the pseudo gate structure; removing the pseudo gate structure, and forming gate openings in the dielectric layer and the initial sacrificial layer; forming a grid structure material layer in the grid opening and on the dielectric layer; and flattening the grid structure material layer and the dielectric layer until the surface of the initial sacrificial layer is exposed to form the grid structure.
17. The method of forming a semiconductor structure of claim 16, wherein after forming a dielectric layer on the initial sacrificial layer, prior to removing the dummy gate structure, further comprising: annealing the dielectric layer, wherein the process parameters of the annealing include: the temperature is 200-600 ℃.
18. The method for forming a semiconductor structure of claim 16, wherein the process for forming the source and drain doped regions comprises an epitaxial growth process.
19. The method of forming a semiconductor structure of claim 9, wherein the initial sacrificial layer has a height in a range of 10 nanometers to 50 nanometers.
20. The method of forming a semiconductor structure of claim 9, wherein after forming the gate structure, prior to modifying the initial sacrificial layer over the first region, further comprising: forming a protective layer on the top of the gate structure; the material of the protective layer includes a dielectric material.
21. The method of forming a semiconductor structure of claim 20, wherein the method of forming the protective layer comprises: etching back the grid structure to form a groove in the initial sacrificial layer; and forming the protective layer in the groove.
22. The method of forming a semiconductor structure of claim 9, wherein the substrate comprises: a substrate; a fin structure on the substrate; and the isolation layer is positioned on the surface of the side wall of the partial fin structure.
23. The method of forming a semiconductor structure of claim 9, wherein a material of the conductive plug comprises a metal comprising: one or more combinations of copper, aluminum, tungsten, cobalt, and titanium nitride.
CN202010642695.9A 2020-07-06 2020-07-06 Semiconductor structure and method for forming semiconductor structure Pending CN113903811A (en)

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