CN115148814A - Semiconductor structure and method for forming semiconductor structure - Google Patents
Semiconductor structure and method for forming semiconductor structure Download PDFInfo
- Publication number
- CN115148814A CN115148814A CN202110342247.1A CN202110342247A CN115148814A CN 115148814 A CN115148814 A CN 115148814A CN 202110342247 A CN202110342247 A CN 202110342247A CN 115148814 A CN115148814 A CN 115148814A
- Authority
- CN
- China
- Prior art keywords
- forming
- opening
- layer
- dielectric layer
- semiconductor structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 103
- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 230000008569 process Effects 0.000 claims description 62
- 239000000463 material Substances 0.000 claims description 58
- 230000004888 barrier function Effects 0.000 claims description 57
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 52
- 229910052710 silicon Inorganic materials 0.000 claims description 52
- 239000010703 silicon Substances 0.000 claims description 52
- 238000005530 etching Methods 0.000 claims description 21
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 21
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 21
- 238000002955 isolation Methods 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 239000012495 reaction gas Substances 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 239000001272 nitrous oxide Substances 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 229910000077 silane Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 156
- 239000003989 dielectric material Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 6
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- -1 phosphorus ions Chemical class 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229910001439 antimony ion Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910001449 indium ion Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure and a method of forming the same, the method comprising: providing a substrate; forming a grid structure and a first medium layer on a substrate, wherein the first medium layer is positioned on the top surface and the side wall surface of the grid structure, and source-drain doped regions are arranged in the substrate on two sides of the grid structure; forming a first opening in the first dielectric layer, wherein the first opening exposes part of the surface of the source-drain doped region; forming a conductive structure in the first opening; after the conductive structure is formed, removing the first dielectric layer, forming a second opening between the conductive structure and the grid structure, and forming a third opening at the top of the grid structure, wherein the third opening exposes the top of the second opening; and forming a second dielectric layer on the conductive structure and the grid structure, wherein the second dielectric layer seals the second opening and the third opening to form a closed cavity. The performance of the semiconductor structure formed by the method is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous development of semiconductor technology, the performance of integrated circuits is improved mainly by the continuous reduction of the size of integrated circuit devices to increase the speed thereof. Currently, the semiconductor industry has progressed to nanotechnology process nodes due to demands for high device density, high performance, and low cost, and the fabrication of semiconductor devices is limited by various physical limitations.
With the evolution of semiconductor technology process nodes, the increase of device density brings about many problems, one of which is the interlayer capacitance between the metal gate MG (metal gate) and the Contact hole (Contact or M0) which increases rapidly. Excessive interlayer capacitance can significantly affect the dynamic performance of the device. Currently, a dielectric layer with a low dielectric constant, such as SiCON, siOx, or SiN, is usually used as a spacer between MG and M0 to eliminate this effect.
However, the problem of excessive interlayer capacitance of semiconductor devices still needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of the semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: the substrate comprises a substrate, a fin structure and an isolation layer, wherein the fin structure is positioned on the substrate, the isolation layer is positioned on the side wall of the fin structure, and the top surface of the isolation layer is lower than that of the fin structure; the gate structure crosses the fin part structure, and the source drain doping region is positioned in the fin part structures at two sides of the gate structure; the conductive structure is positioned on the source drain doped region, a second opening is formed between the conductive structure and the grid structure, a third opening is further formed in the top of the grid structure, and the third opening is exposed out of the top of the second opening; a barrier layer on the sidewall of the conductive structure; and the second dielectric layer is positioned on the conductive structure and the grid structure and seals the second opening and the third opening into a closed cavity.
Optionally, the material of the barrier layer includes silicon carbide, silicon oxycarbide, or silicon carbonitride.
Optionally, the thickness range of the barrier layer is: 5 angstroms to 150 angstroms.
Optionally, the method further includes: and the side wall is positioned on the side wall of the grid structure.
Optionally, the material of the barrier layer is the same as that of the sidewall.
Optionally, the material of the barrier layer includes silicon carbide, silicon oxycarbide, or silicon carbonitride.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate; forming a grid structure and a first medium layer on a substrate, wherein the first medium layer is positioned on the top surface and the side wall surface of the grid structure, and source-drain doped regions are arranged in the substrate on two sides of the grid structure; forming a first opening in the first dielectric layer, wherein the first opening exposes part of the surface of the source-drain doped region; forming a conductive structure in the first opening; after the conductive structure is formed, removing the first dielectric layer, forming a second opening between the conductive structure and the grid structure, and forming a third opening at the top of the grid structure, wherein the third opening exposes the top of the second opening; and forming a second dielectric layer on the conductive structure and the grid structure, wherein the second dielectric layer seals the second opening and the third opening to form a closed cavity.
Optionally, before forming the conductive structure in the first opening, the method further includes: and forming a barrier layer on the surface of the side wall of the first opening.
Optionally, the method for forming the barrier layer includes: forming a barrier material layer on the side wall surface and the bottom surface of the first opening; and etching back the barrier material layer until the bottom surface of the first opening is exposed to form the barrier layer.
Optionally, the process of forming the barrier material layer includes an atomic layer deposition process.
Optionally, the thickness range of the barrier layer is: 5 angstroms to 150 angstroms.
Optionally, the etching rate of the first dielectric layer by the process for removing the first dielectric layer is greater than the etching rate of the barrier layer.
Optionally, the material of the barrier layer includes silicon carbide, silicon oxycarbide, or silicon carbonitride.
Optionally, the process for forming the second dielectric layer includes a chemical vapor deposition process; the process parameters of the chemical vapor deposition process comprise: the reaction gas comprises a mixed gas of silane, nitrogen, oxygen and nitrous oxide; the gas flow range is 10 standard milliliters per minute to 30000 standard milliliters per minute; the pressure intensity is 0.5 to 20 torr; the power range is 100 watts to 2000 watts. Optionally, the number of the first openings is multiple, and the sidewalls of the first openings expose the first dielectric layer.
Optionally, the process for removing the first dielectric layer includes a wet etching process, and an etching solution of the wet etching process includes hydrofluoric acid.
Optionally, the gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the gate dielectric layer is made of hafnium oxide or aluminum oxide, and the gate electrode layer is made of metal tungsten.
Optionally, the method further includes: and the side wall is positioned on the side wall of the grid structure.
Optionally, the etching rate of the first dielectric layer by the process for removing the first dielectric layer is greater than the etching rate of the side wall.
Optionally, the material of the sidewall includes silicon carbide, silicon oxycarbide, or silicon carbonitride.
Optionally, before forming the first opening in the first dielectric layer, the method further includes: a first capping layer is formed on top of the gate structure.
Optionally, after the forming of the conductive structure and before the removing of the first dielectric layer, the method further includes: a second capping layer is formed on top of the conductive structure.
Optionally, the substrate includes a base, a fin structure located on the base, and an isolation layer located on a sidewall of the fin structure, where a top surface of the isolation layer is lower than a top surface of the fin structure.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the forming method of the semiconductor structure, the first opening is formed in the first dielectric layer, part of the surface of the source-drain doped region is exposed out of the first opening, the conductive structure is formed in the first opening, the first dielectric layer is removed, the second opening is formed between the conductive structure and the grid structure, the third opening is formed in the top of the grid structure, the third opening is exposed out of the top of the second opening, and finally the second dielectric layer is formed on the conductive structure and the grid structure, and the second dielectric layer seals the second opening and the third opening to form the closed cavity. The sealed cavity has a smaller dielectric constant, and is located between the conductive structure and the grid structure, so that capacitance between the conductive structure and the grid structure is reduced, mutual interference between the conductive structure and the grid structure can be reduced, and performance of the semiconductor structure is improved.
Further, before forming the conductive structure in the first opening, a barrier layer is also formed on the surface of the side wall of the first opening. On one hand, the size of the conductive structure can be adjusted through the thickness of the barrier layer, and a larger process window is provided; on the other hand, the etching rate of the first dielectric layer by the process for removing the first dielectric layer is greater than that of the barrier layer, so that the barrier layer can protect the conductive structure and prevent the conductive structure from being damaged by the removing process in the process of removing the first dielectric layer.
Furthermore, the side wall of the grid structure is also provided with a side wall, and the material of the side wall is the same as that of the barrier layer. The etching rate of the first dielectric layer by the process for removing the first dielectric layer is greater than that of the side wall, so that the side wall can protect the grid structure and the damage of the grid structure caused by the removing process in the process of removing the first dielectric layer is avoided.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor structure in one embodiment;
fig. 2 to 7 are schematic cross-sectional views of semiconductor structures according to embodiments of the present invention.
Detailed Description
As described in the background, the problem of the overlarge interlayer capacitance of the conventional semiconductor device still needs to be improved. The analysis will now be described with reference to specific examples.
FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment.
Please refer to fig. 1, which includes: a substrate 100; a gate structure 102 located on the substrate 100; a source-drain doped region 101 located in the substrate 100 at two sides of the gate structure 102; a dielectric layer 103 located on the substrate 100, wherein the dielectric layer 103 is located on the top and the sidewall of the gate structure 102; and the conductive plug 104 is positioned in the dielectric layer 103, and the conductive plug 104 is positioned on the source-drain doped region 101.
In the semiconductor structure, the gate structure 102 is a metal gate. As the size of the semiconductor structure is smaller and smaller, the distance between the conductive plug 104 and the gate structure 102 is smaller and smaller, so that the interlayer capacitance between the conductive plug 104 and the gate structure 102 is larger and larger, on one hand, the mutual interference between the conductive plug 104 and the gate structure 102 is serious, and on the other hand, the interlayer capacitance is larger, which affects the working efficiency of the semiconductor structure, and further affects the performance of the semiconductor structure.
In order to solve the problems, the technical scheme of the invention provides a semiconductor structure and a forming method of the semiconductor structure. The sealed cavity has a smaller dielectric constant, and is located between the conductive structure and the grid structure, so that capacitance between the conductive structure and the grid structure is reduced, mutual interference between the conductive structure and the grid structure can be reduced, and performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, embodiments accompanying figures are described in detail below.
Fig. 2 to 7 are schematic cross-sectional views of semiconductor structures according to embodiments of the present invention.
Referring to fig. 2, a substrate 200 is provided.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-element semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material formed by III-V group elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
In this embodiment, the substrate includes a base (not shown) and a plurality of fin structures (not shown) on the base.
In other embodiments, the substrate is a planar substrate.
With reference to fig. 2, a gate structure 202 and a first dielectric layer 201 are formed on a substrate 200, the first dielectric layer 201 is located on the top surface and the sidewall surface of the gate structure 202, and a source/drain doped region 203 is formed in the substrate 200 on both sides of the gate structure 202.
The gate structure 202 includes a gate dielectric layer (not shown) and a gate layer (not shown) over the gate dielectric layer.
In this embodiment, the material of the gate dielectric layer includes a high-dielectric-constant material, the dielectric constant of the high-dielectric-constant material is greater than 3.9, and the high-dielectric-constant material includes hafnium oxide or aluminum oxide; the material of the gate layer comprises a metal comprising tungsten.
In other embodiments, the material of the gate dielectric layer comprises silicon oxide or a low-K (K less than 3.9) material; the material of the gate layer comprises polysilicon.
In this embodiment, the gate structure 202 further includes a work function layer (not labeled), which is located between the gate dielectric layer and the gate electrode layer; the material of the work function layer comprises an N-type work function material or a P-type work function material, the N-type work function material comprises titanium aluminum, and the P-type work function material comprises titanium nitride or tantalum nitride.
In this embodiment, the method further includes: spacers 204 are formed on sidewalls of the gate structure 202.
The material of the sidewall 204 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon oxycarbonitride.
In this embodiment, the material of the sidewall spacers 204 includes silicon carbide, silicon oxycarbide, or silicon carbonitride. The silicon carbide, silicon oxycarbide, or silicon carbonitride material has a lower dielectric constant, resulting in less parasitic capacitance between the gate structures 202. Meanwhile, the side walls 204 can protect the gate structure 202, and damage to the gate structure 202 in the subsequent process of removing the first dielectric layer 201 is avoided.
In this embodiment, the method further includes: a first cap layer 205 is formed on top of the gate structure 202.
The first covering layer 205 is used for protecting the top of the gate structure 202, so as to prevent the gate structure 202 from being damaged by the etching process when the first dielectric layer 201 is etched subsequently.
The material of the first cap layer 205 comprises a dielectric material comprising one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride.
In this embodiment, the material of the first capping layer 205 includes silicon nitride.
The material of the first dielectric layer 201 includes a dielectric material including one or a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the first dielectric layer 201 includes silicon oxide.
Doped ions are arranged in the source drain doped region 203, and the type of the doped ions is N type or P type; the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.
Referring to fig. 3, a first opening 206 is formed in the first dielectric layer 201, and the first opening 206 exposes a portion of the surface of the source/drain doped region 203.
In this embodiment, the number of the first openings 206 is multiple, and the sidewalls of the first openings 206 expose the first dielectric layer 201.
The method for forming the first opening 206 includes: forming a patterning layer (not shown) on the first dielectric layer 201, wherein the patterning layer exposes a part of the surface of the first dielectric layer 201 on the source-drain doped region 203; and etching the first dielectric layer 201 by using the patterning layer as a mask until the surface of the source-drain doped region 203 is exposed, so as to form the first opening 206.
The process for etching the first dielectric layer 201 includes a dry etching process, and the dry etching process can form the first opening 206 with a good sidewall profile.
Referring to fig. 4, a barrier layer 207 is formed on the sidewall surface of the first opening 206.
A barrier layer 207 is formed on the sidewall surface of the first opening 206. In one aspect, the size of the conductive structure can be adjusted by the thickness of the barrier layer 207, with a larger process window; on the other hand, the barrier layer 207 can protect the conductive structure, and damage to the conductive structure caused by the removal process in the process of removing the first dielectric layer 201 is avoided.
The method of forming the barrier layer 207 includes: forming a barrier material layer (not shown) on the sidewall surface and the bottom surface of the first opening 206; the barrier material layer is etched back until the bottom surface of the first opening 206 is exposed, forming the barrier layer 207.
The process of forming the barrier material layer includes an atomic layer deposition process. The atomic layer deposition process can form a film layer with a compact structure and a thin thickness.
In this embodiment, the thickness range of the barrier layer 207 is: 5 angstroms to 150 angstroms. If the thickness of the barrier layer 207 is too thin, the protection effect on the conductive structure is poor; if the barrier layer 207 thickness is too thick, the size of the conductive structures formed may be affected.
The material of the barrier layer 207 comprises a dielectric material comprising one or a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride.
In this embodiment, the material of the barrier layer 207 includes silicon carbide, silicon oxycarbide, or silicon carbonitride. In one aspect, the silicon carbide, silicon oxycarbide, or silicon carbonitride material has a lower dielectric constant, thereby resulting in less parasitic capacitance between the gate structures 202. On the other hand, the barrier layer 207 can protect a subsequently formed conductive structure, and damage to the conductive structure in a subsequent process of removing the first dielectric layer 201 is avoided.
In other embodiments, a barrier layer can be formed free of the first sidewall.
Referring to fig. 5, a conductive structure 208 is formed within the first opening 206.
In this embodiment, the conductive structure 208 is located on the barrier layer 207.
The conductive structure 208 the forming method comprises the following steps: forming a layer of conductive material (not shown) within the first opening 206 and on the first dielectric layer 201; and flattening the conductive material layer until the surface of the first dielectric layer 201 is exposed to form the conductive structure 208.
The conductive structure 208 includes a seed layer (not shown) and a conductive layer (not shown) on the seed layer.
The material of the seed layer comprises metal nitride, and the material of the conductive layer comprises metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
Please refer to fig. 5, which further includes: a second capping layer 209 is formed on top of the conductive structure 208.
The second covering layer 209 is used for protecting the top surface of the conductive structure 208, and avoiding the conductive structure 208 from being damaged by the etching process in the subsequent process of removing the first dielectric layer 201.
The material of the second cap layer 209 comprises a dielectric material comprising one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbonitride, and silicon oxycarbonitride.
In the present embodiment, the material of the second capping layer 209 includes silicon nitride.
Referring to fig. 6, the first dielectric layer 201 is removed, a second opening 210 is formed between the conductive structure 208 and the gate structure 202, a third opening 211 is formed at the top of the gate structure, the third opening 211 exposes the top of the second opening 210, and the second opening 210 exposes the sidewall surfaces of the sidewall spacers 204 and the blocking layer 207.
The etching rate of the process for removing the first dielectric layer 201 on the first dielectric layer 201 is greater than that on the side wall 204, and the etching rate of the process for removing the first dielectric layer 201 on the first dielectric layer 201 is greater than that on the barrier layer 207. So that the process of removing the first dielectric layer 201 has less damage to the gate structure 202 and the conductive structure 208.
In this embodiment, the process for removing the first dielectric layer 201 includes a wet etching process, and an etching solution of the wet etching process includes hydrofluoric acid. The etching rate of the wet etching process to the first dielectric layer 201 is greater than the etching rate to the side wall 204, and the etching rate of the wet etching process to the first dielectric layer 201 is greater than the etching rate to the barrier layer 207.
Referring to fig. 7, a second dielectric layer 212 is formed on the conductive structure 208 and the gate structure 202, and the second dielectric layer 212 closes the second opening 210 and the third opening 211 to form a closed cavity 213.
The forming method of the second dielectric layer 212 comprises the following steps: forming a layer of dielectric material (not shown) within second opening 210, within third opening 211, over conductive structure 208, and over gate structure 202; and planarizing the dielectric material layer to form the second dielectric layer 212.
The material of the second dielectric layer 212 includes a dielectric material including one or a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the second dielectric layer 212 includes silicon oxide.
The process for forming the dielectric material layer comprises a chemical vapor deposition process, an atomic layer deposition process or a heat treatment process. In this embodiment, the process of forming the dielectric material layer includes a chemical vapor deposition process, the process parameters of the chemical vapor deposition process comprise: the reaction gas comprises a mixed gas of silane, nitrogen, oxygen and nitrous oxide; the gas flow range is 10 standard milliliters per minute to 30000 standard milliliters per minute; the pressure intensity range is 0.5 to 20 torr; the power range is 100 watts to 2000 watts. The reaction gas of the chemical vapor deposition process can be preferentially deposited on the top of the second opening 210, so that the second opening 210 and the third opening 211 can be closed into the sealed cavity 213.
To this end, a sealed cavity 213 is formed between the conductive structure 208 and the gate structure 202, and the sealed cavity 213 has a smaller dielectric constant, so that the capacitance between the conductive structure 208 and the gate structure 202 is reduced, thereby reducing the mutual interference between the conductive structure 208 and the gate structure 202 and improving the performance of the semiconductor structure.
Accordingly, an embodiment of the present invention further provides a semiconductor structure, please refer to fig. 7, which includes:
the substrate 200 comprises a base, a fin structure located on the base, and an isolation layer located on the side wall of the fin structure, wherein the top surface of the isolation layer is lower than that of the fin structure;
a gate structure 202 and a source-drain doped region 203 which are located on the substrate 200, wherein the gate structure 202 crosses the fin structure, and the source-drain doped region 203 is located in the fin structure at two sides of the gate structure 202;
a conductive structure 208 located on the source-drain doped region 203, wherein a second opening is formed between the conductive structure 208 and the gate structure 202, and a third opening is further formed in the top of the gate structure 202, and the third opening exposes the top of the second opening;
and a second dielectric layer 211 positioned on the conductive structure 208 and on the gate structure 202, wherein the second dielectric layer 211 seals the second opening and the third opening into a closed cavity 212.
In this embodiment, the material of the barrier layer 207 includes silicon carbide, silicon oxycarbide, or silicon carbonitride.
In this embodiment, the thickness range of the barrier layer 207 is: 5 angstroms to 150 angstroms.
In this embodiment, the method further includes: and a sidewall 204 located on a sidewall of the gate structure 202.
In this embodiment, the material of the barrier layer 207 is the same as the material of the sidewall 204.
In this embodiment, the material of the barrier layer 207 includes silicon carbide, silicon oxycarbide, or silicon carbonitride.
A sealed cavity 213 is formed between the conductive structure 208 and the gate structure 202, and the sealed cavity 213 has a smaller dielectric constant, so that the capacitance between the conductive structure 208 and the gate structure 202 is reduced, thereby reducing the mutual interference between the conductive structure 208 and the gate structure 202, and improving the performance of the semiconductor structure.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (23)
1. A semiconductor structure, comprising:
the substrate comprises a substrate, a fin structure and an isolation layer, wherein the fin structure is positioned on the substrate, the isolation layer is positioned on the side wall of the fin structure, and the top surface of the isolation layer is lower than that of the fin structure;
the gate structure crosses the fin part structure, and the source drain doping region is positioned in the fin part structures at two sides of the gate structure;
the conductive structure is positioned on the source drain doped region, a second opening is formed between the conductive structure and the grid structure, a third opening is further formed in the top of the grid structure, and the third opening is exposed out of the top of the second opening;
the barrier layer is positioned on the side wall of the conductive structure;
and the second dielectric layer is positioned on the conductive structure and the grid structure, and closes the second opening and the third opening to form a closed cavity.
2. The semiconductor structure of claim 1, wherein a material of the barrier layer comprises silicon carbide, silicon oxycarbide, or silicon carbonitride.
3. The semiconductor structure of claim 1, wherein the barrier layer has a thickness in a range of: 5 angstroms to 150 angstroms.
4. The semiconductor structure of claim 1, further comprising: and the side wall is positioned on the side wall of the grid structure.
5. The semiconductor structure of claim 4, wherein a material of the barrier layer is the same as a material of the sidewall spacer.
6. The semiconductor structure of claim 5, wherein a material of the barrier layer comprises silicon carbide, silicon oxycarbide, or silicon carbonitride.
7. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a grid structure and a first medium layer on a substrate, wherein the first medium layer is positioned on the top surface and the side wall surface of the grid structure, and source-drain doped regions are arranged in the substrate on two sides of the grid structure;
forming a first opening in the first dielectric layer, wherein the first opening exposes part of the surface of the source-drain doped region;
forming a conductive structure in the first opening;
after the conductive structure is formed, removing the first dielectric layer, forming a second opening between the conductive structure and the grid structure, and forming a third opening at the top of the grid structure, wherein the third opening exposes the top of the second opening;
and forming a second dielectric layer on the conductive structure and the grid structure, wherein the second dielectric layer seals the second opening and the third opening to form a closed cavity.
8. The method of forming a semiconductor structure of claim 7, further comprising, prior to forming a conductive structure within the first opening: and forming a barrier layer on the surface of the side wall of the first opening.
9. The method of forming a semiconductor structure of claim 8, wherein the method of forming the barrier layer comprises: forming a barrier material layer on the side wall surface and the bottom surface of the first opening; and etching back the barrier material layer until the bottom surface of the first opening is exposed to form the barrier layer.
10. The method of forming a semiconductor structure of claim 9, wherein the process of forming the barrier material layer comprises an atomic layer deposition process.
11. The method of forming a semiconductor structure of claim 8, wherein the barrier layer has a thickness in a range of: 5 angstroms to 150 angstroms.
12. The method of forming a semiconductor structure of claim 8, wherein the process of removing the first dielectric layer has an etch rate for the first dielectric layer that is greater than an etch rate for the barrier layer.
13. The method of forming a semiconductor structure of claim 12, wherein a material of the barrier layer comprises silicon carbide, silicon oxycarbide, or silicon carbonitride.
14. The method of claim 7, wherein the process of forming the second dielectric layer comprises a chemical vapor deposition process; the process parameters of the chemical vapor deposition process comprise: the reaction gas comprises a mixed gas of silane, nitrogen, oxygen and nitrous oxide; the gas flow range is 10 standard milliliters per minute to 30000 standard milliliters per minute; the pressure intensity is 0.5 to 20 torr; the power range is 100W-2000W.
15. The method of claim 7, wherein the number of the first openings is multiple, and sidewalls of the first openings expose the first dielectric layer.
16. The method of claim 7, wherein the process of removing the first dielectric layer comprises a wet etching process, and an etching solution of the wet etching process comprises hydrofluoric acid.
17. The method of forming a semiconductor structure of claim 7, wherein the gate structure comprises a gate dielectric layer and a gate layer over the gate dielectric layer; the gate dielectric layer is made of hafnium oxide or aluminum oxide, and the gate electrode layer is made of metal tungsten.
18. The method of forming a semiconductor structure of claim 7, further comprising: and the side wall is positioned on the side wall of the grid structure.
19. The method for forming a semiconductor structure of claim 18, wherein the process for removing the first dielectric layer has an etch rate for the first dielectric layer that is greater than an etch rate for the sidewalls.
20. The method of forming a semiconductor structure according to claim 19, wherein the material of the sidewall spacers comprises silicon carbide, silicon oxycarbide, or silicon carbonitride.
21. The method of forming a semiconductor structure of claim 7, further comprising, prior to forming the first opening in the first dielectric layer: a first capping layer is formed on top of the gate structure.
22. The method of forming a semiconductor structure of claim 7, wherein after forming a conductive structure and before removing the first dielectric layer, further comprising: a second capping layer is formed on top of the conductive structure.
23. The method of forming a semiconductor structure of claim 7, wherein the substrate comprises a base, a fin structure on the base, and an isolation layer on sidewalls of the fin structure, a top surface of the isolation layer being lower than a top surface of the fin structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110342247.1A CN115148814A (en) | 2021-03-30 | 2021-03-30 | Semiconductor structure and method for forming semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110342247.1A CN115148814A (en) | 2021-03-30 | 2021-03-30 | Semiconductor structure and method for forming semiconductor structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115148814A true CN115148814A (en) | 2022-10-04 |
Family
ID=83404434
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110342247.1A Pending CN115148814A (en) | 2021-03-30 | 2021-03-30 | Semiconductor structure and method for forming semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115148814A (en) |
-
2021
- 2021-03-30 CN CN202110342247.1A patent/CN115148814A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112563266A (en) | Semiconductor device with a plurality of semiconductor chips | |
| US20210249533A1 (en) | Semiconductor device and fabrication method thereof | |
| CN113555285A (en) | Method for forming semiconductor structure | |
| CN113903810B (en) | Semiconductor structure and forming method thereof | |
| US20220359649A1 (en) | Increasing device density and reducing cross-talk spacer structures | |
| CN109545734B (en) | Semiconductor structure and forming method thereof | |
| US20240021728A1 (en) | Semiconductor structure and fabrication method thereof | |
| CN113903808B (en) | Semiconductor structure and forming method thereof | |
| WO2021190295A1 (en) | Semiconductor structure and forming method therefor | |
| CN115148814A (en) | Semiconductor structure and method for forming semiconductor structure | |
| CN113363321A (en) | Semiconductor structure and forming method thereof | |
| CN113690313A (en) | Semiconductor structure and method for forming semiconductor structure | |
| CN107591331B (en) | Semiconductor structure and forming method thereof | |
| US20230093835A1 (en) | Semiconductor structure and fabrication method thereof | |
| CN112992679B (en) | Semiconductor structure and forming method thereof | |
| US11855167B2 (en) | Structure and formation method of semiconductor device with nanosheet structure | |
| CN115513286A (en) | Semiconductor structure and method for forming semiconductor structure | |
| CN109994548B (en) | Semiconductor structure and forming method thereof | |
| US20230352593A1 (en) | Semiconductor device and methods of formation | |
| CN114496906A (en) | Semiconductor structure and method for forming semiconductor structure | |
| CN114864690A (en) | Semiconductor structure and forming method thereof | |
| CN113690139A (en) | Semiconductor structure and method for forming semiconductor structure | |
| CN114496981A (en) | Semiconductor structure and method for forming semiconductor structure | |
| CN115036370A (en) | Semiconductor structure and forming method thereof | |
| CN114267593A (en) | Method for forming semiconductor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |