CN113707555A - Semiconductor structure and method for forming semiconductor structure - Google Patents

Semiconductor structure and method for forming semiconductor structure Download PDF

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Publication number
CN113707555A
CN113707555A CN202010441163.9A CN202010441163A CN113707555A CN 113707555 A CN113707555 A CN 113707555A CN 202010441163 A CN202010441163 A CN 202010441163A CN 113707555 A CN113707555 A CN 113707555A
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Prior art keywords
layer
forming
semiconductor structure
gate layer
initial
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Chinese (zh)
Inventor
纪世良
王胜
张海洋
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202010441163.9A priority Critical patent/CN113707555A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a method for forming the same, the structure comprising: a substrate; the dummy gate layer is positioned on the substrate and comprises an effective area and an isolation area between the effective area, and the material of the effective area is different from that of the isolation area; and the dielectric layer is positioned on the side wall of the dummy gate layer and exposes out of the top surface of the dummy gate layer. The performance of the semiconductor structure is improved.

Description

Semiconductor structure and method for forming semiconductor structure
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
Integrated circuit technology continues to develop according to moore's law, feature sizes continue to shrink, integration levels continue to improve, and functions become stronger and stronger. With the continuous reduction of the feature size of the device, if the conventional polysilicon gate is still used, the polysilicon depletion effect becomes more serious, and the polysilicon resistance is increased. To overcome the above difficulties and to integrate with high-k gate dielectric materials, the industry has begun to adopt metal gate technology.
However, the metal gate has a complicated structure, so that the cutting process of the metal gate is difficult to control accurately, thereby affecting the performance of the metal gate.
Therefore, improvement of the performance of the metal gate is required.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of the semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate; the dummy gate layer is positioned on the substrate and comprises an effective area and an isolation area positioned between the effective areas, and the material of the effective area is different from that of the isolation area; and the dielectric layer is positioned on the side wall of the dummy gate layer and exposes out of the top surface of the dummy gate layer.
Optionally, the material of the isolation region is obtained by modifying the material of the active region.
Optionally, the material of the dummy gate layer active region includes a semiconductor material, and the semiconductor material includes silicon.
Optionally, the material of the dummy gate layer isolation region includes silicon containing dopant ions, and the dopant ions include carbon ions, fluorine ions, boron ions, or nitrogen ions.
Optionally, the substrate includes a base and a plurality of fin structures located on the base, and the fin structures are arranged in parallel along a direction parallel to the surface of the substrate; the dummy gate layer spans across the fin structure.
Optionally, the isolation region is located between adjacent fin structures.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate; forming an initial dummy gate layer on a substrate, the initial dummy gate layer including active areas and an initial isolation area between the active areas; forming a dielectric layer on the substrate, wherein the dielectric layer is positioned on the side wall of the initial pseudo gate layer and exposes out of the top surface of the initial pseudo gate layer; and modifying the initial isolation region of the initial pseudo gate layer to form an isolation region and a pseudo gate layer.
Optionally, the process of the modification treatment includes an ion implantation process, and implanted ions of the ion implantation process include carbon ions, fluorine ions, boron ions, or nitrogen ions.
Optionally, the material of the initial dummy gate layer comprises a semiconductor material, and the semiconductor material comprises silicon.
Optionally, after forming the dummy gate layer, the method further includes: removing the effective area of the dummy gate layer, and forming a first opening in the dielectric layer; and forming a gate structure in the first opening.
Optionally, after the forming the gate structure, the method further includes: removing the isolation region and forming a second opening in the dielectric layer; and forming an isolation structure in the second opening.
Optionally, the process for removing the isolation region includes one or more of a dry etching process and a wet etching process.
Optionally, the method for forming the first opening includes: removing part of the effective area of the dummy gate layer to form an intermediate structure; and removing the intermediate structure, and forming a first opening in the dielectric layer.
Optionally, the process of removing part of the active region of the dummy gate layer includes a dry etching process.
Optionally, the process of removing the intermediate structure includes a wet etching process.
Optionally, before the modifying treatment is performed on the initial isolation region, the method further includes: and forming a transition layer on the surface of the dielectric layer and the surface of the initial dummy gate layer.
Optionally, the material of the transition layer includes a dielectric material, and the dielectric material includes silicon oxide.
Optionally, the thickness range of the transition layer is: 1nm to 10 nm.
Optionally, the gate structure includes a gate dielectric layer and a gate layer located on the surface of the gate dielectric layer.
Optionally, the gate structure further includes: the work function structure is positioned on the surface of the gate dielectric layer; the gate layer is located on a surface of the work function structure.
Optionally, the dielectric constant of the gate dielectric layer material is greater than 3.9, and the gate dielectric layer material includes hafnium oxide or aluminum oxide; the material of the gate layer comprises a metal, and the metal comprises tungsten; the material of the work function structure comprises one or a combination of titanium aluminum, tantalum nitride and titanium nitride.
Optionally, the substrate includes a base and a plurality of fin structures located on the base, and the fin structures are arranged in parallel along a direction parallel to the surface of the substrate; the initial dummy gate layer spans across the fin structure.
Optionally, the isolation region is located between adjacent fin structures.
Optionally, the method for forming the isolation region includes: forming a mask structure on the surface of the dielectric layer and the surface of the initial dummy gate layer, wherein the mask structure exposes the top surface of the initial isolation region; and modifying the initial isolation region by taking the mask structure as a mask to form the isolation region.
Optionally, the mask structure includes: a hard mask layer; a pad layer on the hard mask layer; a photoresist layer on the pad layer.
Optionally, the material of the hard mask layer includes a dielectric material, and the dielectric material includes silicon nitride.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the semiconductor structure, the substrate is provided with the pseudo gate layer, the pseudo gate layer comprises the effective region and the isolation region between the effective regions, the materials of the effective regions are different from those of the isolation region, and therefore the materials of the isolation region and the effective regions have a large etching selection ratio. Therefore, the effective area of the pseudo gate layer can be removed first subsequently, the gate structure is formed at the position of the effective area, then the isolation area of the pseudo gate layer is removed, and the isolation structure with high position accuracy is formed at the position of the isolation area. Thereby improving the performance of the semiconductor structure.
According to the forming method of the semiconductor structure, the initial isolation region is modified to form the isolation region, so that the material of the isolation region and the material of the effective region have a large etching selection ratio, the effective region of the pseudo gate layer can be removed first, the gate structure is formed at the position of the effective region, the isolation region of the pseudo gate layer is removed, and the isolation structure is formed at the position of the isolation region. The isolation structure formed by the method is high in position accuracy, and the situation that the voltage of the grid structure drifts due to the fact that the position of the isolation structure deviates is avoided, so that the performance of the semiconductor structure is improved.
Further, the material of the initial dummy gate layer comprises silicon, and the modification process comprises an ion implantation process, wherein the ion implantation process can change the structure of the material of the initial isolation region, so that the materials of the isolation region and the active region have a larger etching selection ratio.
Furthermore, transition layers are formed on the surface of the dielectric layer and the surface of the initial pseudo gate layer, the transition layers are made of silicon oxide, the transition layers can play a transition role between the surface of the top of the initial pseudo gate layer and the hard mask layer of the mask structure, and the problem that when the hard mask layer is in direct contact with the top of the initial pseudo gate layer, due to the fact that the difference of the structure density of the materials is large, the interface is not matched, and the graph position of the mask structure is affected is avoided.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor structure in one embodiment;
fig. 2 to 10 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Detailed Description
As described in the background, improvements in the performance of metal gates are needed. The analysis will now be described with reference to specific examples.
FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment.
Referring to fig. 1, the semiconductor structure includes: a substrate 100, wherein the substrate 100 includes an active region (not shown) and an isolation region (not shown); a fin structure 101 on an active area of the substrate 100; an isolation layer 102 on the substrate 100, wherein the isolation layer 102 is located on a partial sidewall surface of the fin structure 101; a gate structure 104 located on the active region of the substrate 100, wherein the gate structure 104 crosses the fin structure 101; a dielectric layer 103 located on the substrate 100, wherein the dielectric layer 103 is located on a sidewall of the gate structure 104; an isolation structure 105 is disposed on the isolation region of the substrate 100, wherein the isolation structure 105 is adjacent to the gate structure 104.
In the semiconductor structure, the method for forming the isolation structure 105 includes: forming an initial gate structure (not shown) on the substrate 100; removing the initial gate structure on the isolation region to form a gate structure 104, and forming an opening (not shown) in the dielectric layer 103; isolation structures 105 are formed within the openings. The initial gate structure comprises a gate dielectric layer, a work function structure positioned on the surface of the gate dielectric layer and a gate layer positioned on the surface of the work function structure, wherein the material of the gate dielectric layer comprises a high-K (more than 3.9) material, the material of the gate layer comprises metal, the work function structure comprises one or more work function layers, and the material of the work function layer comprises the combination of one or more work function materials.
Therefore, when removing part of the initial gate structure, a dry etching process is usually adopted to remove part of the initial gate structure, and the initial gate structure has a more complex film structure, so that the process for removing the initial gate structure is more complex, and the parameters of the etching process need to be continuously adjusted.
However, the accuracy of the dry etching process under each process condition has a certain deviation range, so that the position of the formed opening cannot be precisely located on the isolation region, and the position of the formed isolation structure 105 is shifted. The position of the isolation structure 105 is shifted, so that the position of the isolation structure 105 is closer to the position of the fin structure 101 on the active region on one side, and the position of the isolation structure 105 is farther from the position of the fin structure 101 on the active region on the other side, so that the stress of the isolation structure 105 on the gate structures 104 on two sides is uneven, the voltage of the gate structures on two sides of the isolation structure 105 drifts, and the performance of the semiconductor structure is affected.
In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming a semiconductor structure, in which an isolation region is formed by modifying an initial isolation region, so that a material of the isolation region has a relatively high etching selectivity with respect to a material of an active region, and thus the active region of a dummy gate layer can be removed first, a gate structure is formed at a position of the active region, and then the isolation region of the dummy gate layer is removed, and an isolation structure is formed at a position of the isolation region. The isolation structure formed by the method is high in position accuracy, and the situation that the voltage of the grid structure drifts due to the fact that the position of the isolation structure deviates is avoided, so that the performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 10 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 2, a substrate is provided.
In this embodiment, the substrate includes a base 200 and a plurality of fin structures 201 on the base 200, and the plurality of fin structures 201 are arranged in parallel along a direction parallel to a surface of the substrate.
In this embodiment, the material of the substrate 200 is monocrystalline silicon; the fin structure 201 is made of monocrystalline silicon.
In other embodiments, the substrate may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, or silicon-on-insulator; the fin structure may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, or silicon-on-insulator.
In this embodiment, the substrate further has an isolation layer 202, the isolation layer 202 is located on a portion of the sidewall of the fin structure 201, and a top surface of the isolation layer 202 is lower than a top surface of the fin structure 201.
The material of the isolation layer 202 comprises a dielectric material comprising a combination of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbide nitride. In the present embodiment, the material of the isolation layer 202 includes silicon oxide.
In other embodiments, the substrate comprises a planar substrate.
Referring to fig. 3, an initial dummy gate layer is formed on a substrate, the initial dummy gate layer including active regions 203 and initial isolation regions 204 located between the active regions 203, the initial dummy gate layer spanning the fin structures 201, the initial isolation regions 204 located between adjacent fin structures 201.
The active region 203 is used for forming an active gate structure at the position of the active region after the subsequent removal, and the initial isolation region 204 is used for forming an isolation structure at the position of the initial isolation region 204 subsequently, so as to realize the electrical isolation of the active region.
The material of the initial dummy gate layer comprises a semiconductor material comprising silicon, silicon carbide, silicon germanium, a multi-element semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
In this embodiment, the material of the initial dummy gate layer includes silicon.
In this embodiment, the method further includes: a gate dielectric layer (not shown) is formed on the substrate between the initial dummy gate layer and the substrate.
The material of the gate dielectric layer comprises a low-K (less than or equal to 3.9) material, and the low-K material comprises silicon oxide.
With continued reference to fig. 3, a dielectric layer 205 is formed on the substrate, wherein the dielectric layer 205 is located on the sidewalls of the initial dummy gate layer, and the dielectric layer 205 exposes the top surface of the initial dummy gate layer.
The forming method of the dielectric layer 205 comprises the following steps: forming a dielectric material layer (not shown) on the substrate, the dielectric material layer covering the initial dummy gate layer; and planarizing the dielectric material layer until the top surface of the initial dummy gate layer is exposed to form the dielectric layer 205.
The material of the dielectric layer 205 comprises a dielectric material comprising one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbonitride. In this embodiment, the material of the dielectric layer 205 includes silicon oxide.
Referring to fig. 4, a transition layer 206 is formed on the surface of the dielectric layer 205 and the surface of the initial dummy gate layer.
The transition layer 206 can play a role in transition between the top surface of the initial pseudo gate layer and a hard mask layer of a subsequently formed mask structure, and the problem that when the hard mask layer is in direct contact with the top of the initial pseudo gate layer, due to the fact that the difference of structural density of materials is large, an interface is not matched, and the graph position of the mask structure is affected is avoided.
The material of the transition layer 206 comprises a dielectric material comprising a combination of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbide nitride. The process of forming the transition layer 206 includes a chemical vapor deposition process, an atomic layer deposition process, or a thermal treatment process.
In the present embodiment, the dielectric material includes silicon oxide, and the process of forming the transition layer 206 includes an atomic layer deposition process, which can form the transition layer 206 with a dense structure and a thin thickness.
In this embodiment, the thickness range of the transition layer 206 is: 1nm to 10 nm.
The transition layer 206 with the thickness range does not have an insignificant transition effect on the hard mask layer and the top surface of the initial dummy gate layer due to being too thin, and does not affect the effect of the modification process when the isolation region 204 is subsequently modified due to being too thick.
In other embodiments, the transition layer can be not formed.
Next, an isolation region 210 is formed by modifying the initial isolation region 204 of the initial dummy gate layer, so as to form a dummy gate layer.
Referring to fig. 5, a mask structure is formed on the surface of the dielectric layer 205 and the surface of the initial dummy gate layer, and the mask structure exposes the top surface of the initial isolation region 204.
In this embodiment, the mask structure exposes the top surface of the transition layer 205.
The mask structure includes: a hard mask layer 207; a pad layer 208 on the hard mask layer 207; a photoresist layer 209 is located over the pad layer 208.
The hard mask layer 207 comprises a dielectric material, and the dielectric material comprises silicon nitride; the material of the liner layer 208 comprises an organic material comprising amorphous carbon.
Referring to fig. 6, the initial isolation region 204 is modified by using the mask structure as a mask to form an isolation region 210.
The modification treatment process comprises an ion implantation process, wherein implanted ions of the ion implantation process comprise carbon ions, fluorine ions, boron ions or nitrogen ions.
The material of the initial pseudo gate layer comprises silicon, the process of the modification treatment comprises an ion implantation process, the ion implantation process can change the structure of the material of the initial isolation region 204, so that the formed isolation region 210 and the material of the effective region 203 have a large etching selection ratio, the effective region 203 of the pseudo gate layer can be removed firstly, a gate structure is formed at the position of the effective region 203, then the isolation region 210 of the pseudo gate layer is removed, an isolation structure is formed at the position of the isolation region 210, the position accuracy of the formed isolation structure is high, the situation that the voltage of the gate structure drifts due to the position offset of the isolation structure is avoided, and the performance of the semiconductor structure is improved.
Referring to fig. 7, after the isolation regions 210 are formed, the mask structure is removed.
In the present embodiment, the process of removing the photoresist layer 209 includes an ashing process; the process of removing the liner layer 208 includes a dry etching process; the process for removing the hard mask layer 207 includes one or more of a dry etching process and a wet etching process.
With continued reference to fig. 7, after removing the mask structure, the transition layer 206 is removed.
The process of removing the transition layer 206 includes a chemical mechanical polishing process, a dry etching process, or a wet etching process.
Referring to fig. 8, the active region 203 of the dummy gate layer is removed, and a first opening 211 is formed in the dielectric layer 205.
The method for forming the first opening 211 includes: removing part of the active region 203 of the dummy gate layer to form an intermediate structure (not shown); the intermediate structure is removed and a first opening 211 is formed in the dielectric layer 205.
In this embodiment, the process of removing part of the active region 203 of the dummy gate layer includes a dry etching process; the process for removing the intermediate structure comprises a wet etching process. Firstly, a dry etching process is adopted to remove part of the effective region 203 to form an intermediate structure, and a wet etching process is adopted to remove the intermediate structure, so that the effective region 203 of the pseudo gate structure can be completely removed, and the condition that the performance of a subsequently formed gate structure is influenced due to the incomplete removal of the effective region 203 is avoided.
In other embodiments, one or more of a dry etching process and a wet etching process can be used to remove the active region of the dummy gate layer at a time.
Referring to fig. 9, a gate structure is formed in the first opening 211.
The gate structure includes a gate dielectric layer (not shown) and a gate layer 212 on the surface of the gate dielectric layer.
The gate structure further includes: a work function structure (not shown) located on the surface of the gate dielectric layer; the gate layer 212 is located on the surface of the work function structure.
The dielectric constant of the material of the gate dielectric layer is greater than 3.9, and the material of the gate dielectric layer comprises hafnium oxide or aluminum oxide; the material of the gate layer 212 comprises a metal, which comprises tungsten; the material of the work function structure comprises one or a combination of titanium aluminum, tantalum nitride and titanium nitride.
Referring to fig. 10, the isolation region 210 is removed, and a second opening (not shown) is formed in the dielectric layer 205; an isolation structure 213 is formed within the second opening.
The process of removing the isolation region 210 includes one or more of a dry etching process and a wet etching process.
The method for forming the isolation structure 213 comprises the following steps: forming a layer of isolation material (not shown) within the second opening and over the gate structure; the isolation material layer is planarized until the top surface of the gate structure is exposed, and an isolation structure 213 is formed in the second opening.
The material of the isolation structure 213 comprises a dielectric material comprising a combination of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbide nitride. The process for forming the isolating material layer comprises a chemical vapor deposition process, an atomic layer deposition process or a heat treatment process.
In the present embodiment, the material of the isolation structure 213 includes silicon nitride; the process of forming the layer of barrier material comprises a chemical vapor deposition process.
In the method for forming the semiconductor structure, the isolation region 210 is formed by modifying the initial isolation region 204, so that the material of the isolation region 210 has a larger etching selectivity with the material of the active region 203, and thus the active region 203 of the dummy gate layer can be removed first, a gate structure is formed at the position of the active region 203, and then the isolation region 210 of the dummy gate layer is removed, and the isolation structure 213 is formed at the position of the isolation region 210. The isolation structure 213 formed by the method has high position accuracy, and the situation that the voltage of the gate structure drifts due to the position offset of the isolation structure 213 is avoided, so that the performance of the semiconductor structure is improved.
Accordingly, an embodiment of the present invention further provides a semiconductor structure, please refer to fig. 7, which includes:
a substrate;
a dummy gate layer on the substrate, the dummy gate layer including an active region 203 and an isolation region 210 between the active region 203, the active region 203 being made of a material different from that of the isolation region 210;
and the dielectric layer 205 is positioned on the substrate, the dielectric layer 205 is positioned on the side wall of the dummy gate layer, and the dielectric layer 205 exposes the top surface of the dummy gate layer.
In this embodiment, the material of the isolation region 210 is obtained by modifying the material of the active region 203.
In this embodiment, the material of the dummy gate layer active region 203 includes a semiconductor material, and the semiconductor material includes silicon.
In the present embodiment, the material of the dummy gate layer isolation region 210 includes silicon containing dopant ions, which include carbon ions, fluorine ions, boron ions, or nitrogen ions.
In this embodiment, the substrate includes a base 200 and a plurality of fin structures 201 located on the base 200, and the plurality of fin structures 201 are arranged in parallel along a direction parallel to a surface of the substrate; the dummy gate layer spans the fin structure 210.
In the present embodiment, the isolation regions 210 are located between adjacent fin structures 201.
The semiconductor structure is provided with a pseudo gate layer on a substrate, the pseudo gate layer comprises an effective region 203 and an isolation region 210 between the effective region 203, the material of the effective region 203 is different from that of the isolation region 210, and therefore the material of the isolation region 210 and the material of the effective region 203 have a larger etching selection ratio. Therefore, the effective region 203 of the dummy gate layer can be removed first, a gate structure is formed at the position of the effective region 203, the isolation region 210 of the dummy gate layer is removed, and an isolation structure with high position accuracy is formed at the position of the isolation region 210. Thereby improving the performance of the semiconductor structure.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (26)

1. A semiconductor structure, comprising:
a substrate;
the dummy gate layer is positioned on the substrate and comprises an effective area and an isolation area positioned between the effective areas, and the material of the effective area is different from that of the isolation area;
and the dielectric layer is positioned on the side wall of the dummy gate layer and exposes out of the top surface of the dummy gate layer.
2. The semiconductor structure of claim 1, wherein the material of the isolation region is obtained by a material modification treatment of the active region.
3. The semiconductor structure of claim 2, wherein a material of the dummy gate layer active region comprises a semiconductor material comprising silicon.
4. The semiconductor structure of claim 2, wherein a material of the dummy gate layer isolation region comprises silicon containing dopant ions comprising carbon ions, fluorine ions, boron ions, or nitrogen ions.
5. The semiconductor structure of claim 1, wherein the substrate comprises a base and a plurality of fin structures on the base, the plurality of fin structures being arranged in parallel along a direction parallel to a surface of the substrate; the dummy gate layer spans across the fin structure.
6. The semiconductor structure of claim 5, wherein the isolation region is located between adjacent fin structures.
7. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming an initial dummy gate layer on a substrate, the initial dummy gate layer including active areas and an initial isolation area between the active areas;
forming a dielectric layer on the substrate, wherein the dielectric layer is positioned on the side wall of the initial pseudo gate layer and exposes out of the top surface of the initial pseudo gate layer;
and modifying the initial isolation region of the initial pseudo gate layer to form an isolation region and a pseudo gate layer.
8. The method of claim 7, wherein the modifying process comprises an ion implantation process, wherein the ions implanted by the ion implantation process comprise carbon ions, fluorine ions, boron ions, or nitrogen ions.
9. The method of forming a semiconductor structure of claim 8, wherein the material of the initial dummy gate layer comprises a semiconductor material comprising silicon.
10. The method of forming a semiconductor structure of claim 7, further comprising, after forming the dummy gate layer: removing the effective area of the dummy gate layer, and forming a first opening in the dielectric layer; and forming a gate structure in the first opening.
11. The method of forming a semiconductor structure of claim 10, further comprising, after forming the gate structure: removing the isolation region and forming a second opening in the dielectric layer; and forming an isolation structure in the second opening.
12. The method of claim 11, wherein the process of removing the isolation region comprises a combination of one or more of a dry etch process and a wet etch process.
13. The method of forming a semiconductor structure of claim 10, wherein the method of forming the first opening comprises: removing part of the effective area of the dummy gate layer to form an intermediate structure; and removing the intermediate structure, and forming a first opening in the dielectric layer.
14. The method of claim 13, wherein the process of removing a portion of the active region of the dummy gate layer comprises a dry etch process.
15. The method of forming a semiconductor structure of claim 13, wherein the process of removing the intermediate structure comprises a wet etch process.
16. The method of forming a semiconductor structure of claim 7, further comprising, prior to modifying the initial isolation region: and forming a transition layer on the surface of the dielectric layer and the surface of the initial dummy gate layer.
17. The method of forming a semiconductor structure of claim 16, wherein the material of the transition layer comprises a dielectric material comprising silicon oxide.
18. The method of forming a semiconductor structure of claim 16, wherein the transition layer has a thickness in a range of: 1nm to 10 nm.
19. The method of forming a semiconductor structure of claim 7, wherein the gate structure comprises a gate dielectric layer and a gate layer on a surface of the gate dielectric layer.
20. The method of forming a semiconductor structure of claim 19, wherein the gate structure further comprises: the work function structure is positioned on the surface of the gate dielectric layer; the gate layer is located on a surface of the work function structure.
21. The method for forming a semiconductor structure according to claim 19, wherein the material of the gate dielectric layer has a dielectric constant greater than 3.9, and the material of the gate dielectric layer comprises hafnium oxide or aluminum oxide; the material of the gate layer comprises a metal, and the metal comprises tungsten; the material of the work function structure comprises one or a combination of titanium aluminum, tantalum nitride and titanium nitride.
22. The method of claim 7, wherein the substrate comprises a base and a plurality of fin structures on the base, the plurality of fin structures being arranged in parallel along a direction parallel to a surface of the substrate; the initial dummy gate layer spans across the fin structure.
23. The method of forming a semiconductor structure of claim 22, wherein the isolation region is located between adjacent fin structures.
24. The method of forming a semiconductor structure of claim 7, wherein the method of forming isolation regions comprises: forming a mask structure on the surface of the dielectric layer and the surface of the initial dummy gate layer, wherein the mask structure exposes the top surface of the initial isolation region; and modifying the initial isolation region by taking the mask structure as a mask to form the isolation region.
25. The method of forming a semiconductor structure of claim 24, wherein the masking structure comprises: a hard mask layer; a pad layer on the hard mask layer; a photoresist layer on the pad layer.
26. The method of forming a semiconductor structure of claim 25, wherein the material of the hard mask layer comprises a dielectric material comprising silicon nitride.
CN202010441163.9A 2020-05-22 2020-05-22 Semiconductor structure and method for forming semiconductor structure Pending CN113707555A (en)

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