CN103107073A - Formation method of metal grid electrode - Google Patents
Formation method of metal grid electrode Download PDFInfo
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- CN103107073A CN103107073A CN2011103579578A CN201110357957A CN103107073A CN 103107073 A CN103107073 A CN 103107073A CN 2011103579578 A CN2011103579578 A CN 2011103579578A CN 201110357957 A CN201110357957 A CN 201110357957A CN 103107073 A CN103107073 A CN 103107073A
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Abstract
Disclosed is a formation method of a metal grid electrode. The formation method of the metal grid electrode comprises that the formation method of the metal grid electrode is provided with a semi-conductor substrate. The semi-conductor substrate comprises a first transistor area and a second transistor area. A replacing grid electrode structure is formed on the semi-conductor substrate. The replacing grid electrode structure is arranged in the first transistor area and the second transistor area at the same time. Ion implantation is carried out in the replacing grid electrode structure of the first transistor area. Tetramethylammonium hydroxide liquor is used for eliminating the replacing grid electrode structure of the second transistor area. The ion implantation is not carried out in the second transistor area. A second groove is formed. A second metal grid electrode is formed in the second groove. The replacing grid electrode structure of the first transistor area is eliminated. The ion implantation is carried out in the first transistor area. A first groove is formed. A first metal grid electrode is formed in the first groove. Due to the fact that the replacing grid electrode structure is etched selectively by the tetramethylammonium hydroxide liquor, a perpendicular groove side wall can be achieved by taking advantage of injecting the ion, thus technological requirements can be met by the follow-up formed metal grid electrode.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of formation method of metal gates.
Background technology
Development along with ic manufacturing technology, the characteristic size of MOS transistor is also more and more less, in order to reduce the parasitic capacitance of MOS transistor grid, improve device speed, the gate stack structure of high K gate dielectric layer and metal gates is introduced in MOS transistor.For fear of the impact on other structures of transistor of the metal material of metal gates, the gate stack structure of described metal gates and high K gate dielectric layer adopts " rear grid (gate last) " technique to make usually.
Publication number is that the american documentation literature of US2002/0064964A1 discloses the method that a kind of use " rear grid " technique forms metal gates, comprise: Semiconductor substrate is provided, is formed with the alternative gate structure on described Semiconductor substrate and is positioned at the interlayer dielectric layer that covers described alternative gate structure on described Semiconductor substrate; As stop-layer, described interlayer dielectric layer is carried out chemical mechanical milling tech (CMP) with described alternative gate structure; Form groove after removing described alternative gate structure; Fill metal by the PVD method in described groove, to form metal gate electrode layer; To exposing interlayer dielectric layer, form metal gates with chemical mechanical milling method abrasive metal gate electrode layer.Because metal gates is made after the source-drain area injection is completed again, this makes the quantity of subsequent technique be reduced, and has avoided metal material to be unsuitable for carrying out the problem of high-temperature process.
At present static random access memory (Static Random Access Memory, SRAM) in memory cell, the grid of nmos pass transistor grid common and a PMOS is electrically connected, please refer to Fig. 1, circuit diagram for the SRAM memory cell of prior art, described SRAM memory cell has four NMOS transistors 11,12,13,14 and two PMOS transistors 15,16, the grid of the grid of wherein said nmos pass transistor 11 and PMOS transistor 15 is electrically connected to, and the grid of described nmos pass transistor 12 and PMOS transistor 16 is electrically connected to.In the prior art, the transistorized grid of nmos pass transistor in described SRAM memory cell and PMOS is electrically connected to and need to forms conductive plunger in described gate surface, and utilizes described conductive plunger to be connected with metal interconnecting layer and realize that described nmos pass transistor and the transistorized grid of PMOS are electrically connected to.
But along with improving constantly of SRAM integrated level, grid structure is more and more less, also more and more difficult at described grid structure surface formation conductive plunger, therefore proposed afterwards nmos pass transistor and PMOS transistor are shared same grid structure, can effectively improve the SRAM integrated level, reduce process complexity.Please refer to Fig. 2, the structural representation for nmos pass transistor in the SRAM memory cell of prior art and PMOS transistor common grid comprises: have nmos pass transistor district 01 and PMOS transistor area 02 on Semiconductor substrate; Described common grid 21 is across the border of described nmos pass transistor district 01 and PMOS transistor area 02, and the part of described common grid 21 is positioned at nmos pass transistor district 01, and another part of described common grid 21 is positioned at PMOS transistor area 02; In nmos pass transistor district 01, the both sides of described common grid 21 are formed with N-type source/drain region 22; In PMOS transistor area 02, the both sides of described common grid 21 are formed with P type source/drain region 23.
But along with the SRAM integrated level is more and more higher, the characteristic size of MOS transistor is also more and more less, and the transistorized common grid of nmos pass transistor and PMOS also needs to adopt metal gates to reduce the parasitic capacitance of MOS transistor grid, improves device speed.But because nmos pass transistor is different with the transistorized work function of PMOS, therefore material and the technique of the metal gates of nmos pass transistor and the transistorized metal gates of PMOS are all different, need to form respectively, this makes nmos pass transistor and the transistorized metal gates of PMOS be difficult to reach technological requirement.
Summary of the invention
The problem that the present invention solves is to provide the formation method of the metal gates that a kind of nmos pass transistor and the transistorized metal gates of PMOS link together, and makes the metal gates of final formation can satisfy technological requirement.
For addressing the above problem, technical solution of the present invention provides a kind of formation method of metal gates, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises the first transistor district and transistor seconds district;
Form the alternative gate structure on described Semiconductor substrate, described alternative gate structure is positioned at described first crystal area under control and transistor seconds district simultaneously;
Alternative gate structure to the first crystal area under control is carried out Implantation;
Utilize tetramethyl ammonium hydroxide solution to remove not by the alternative gate structure in the transistor seconds district of Implantation, form the second groove, and form the second metal gates in described the second groove;
Remove by the alternative gate structure in the first crystal area under control of Implantation, form the first groove, and form the first metal gates in described the first groove.
Optionally, described Implantation vertically is injected in the alternative gate structure in first crystal area under control, makes the zone of described alternative gate structure intermediate ion injection with not vertical with semiconductor substrate surface by the border in the zone of Implantation.
Optionally, the degree of depth of described Implantation is equal to or greater than the thickness of described alternative gate structure.
Optionally, the foreign ion of described Implantation be boron, indium, nitrogen, phosphorus, arsenic, antimony, carbon, fluorine, chlorine, helium, argon wherein one or more.
Optionally, be formed with gate dielectric layer between described alternative gate structure and Semiconductor substrate, described gate dielectric layer is silicon oxide layer or high K dielectric layer.
Optionally, also comprise, form the barrier layer between described gate dielectric layer and alternative gate structure.
Optionally, the material on described barrier layer is wherein a kind of of TiN, TaN or both laminated construction.
Optionally, after the alternative gate structure of removing respectively described first crystal area under control and transistor seconds district, described barrier layer still covers the surface of the gate dielectric layer of described correspondence.
Optionally, the material of described alternative gate structure is polysilicon.
Optionally, described method of removing the alternative gate structure in first crystal area under control comprises wet etching or dry etching.
Optionally, the described wet etching solution of removing the alternative gate structure in first crystal area under control is KOH solution.
Optionally, the described dry etching of removing the alternative gate structure in first crystal area under control is the coefficient dry etch process of physics and chemistry mechanism.
Optionally, when described the first metal gates and the second metal gates are single coating, the material of described the first metal gates and the second metal gates be Al, Cu, Ag, Au, Pt, Ni wherein one or more.
Optionally, when described the first metal gates and the second metal gates were the multiple-level stack structure, described the first metal gates and the second metal gates comprised functional layer and are positioned at the metal gate electrode layer on functional layer surface.
Optionally, described functional layer is the barrier layer.
Optionally, described functional layer comprises: be positioned at the gate dielectric layer surface described barrier layer, be positioned at the supplementary functions layer of described barrier layer surface.
Optionally, the material of described functional layer be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more.
Optionally, the material of described metal gate electrode layer be Al, Cu, Ag, Au, Pt, Ni wherein one or more.
Optionally, described first crystal area under control is the PMOS transistor area, and described transistor seconds district is the nmos pass transistor district.
Optionally, described first crystal area under control is the nmos pass transistor district, and described transistor seconds district is the PMOS transistor area.
Compared with prior art, the present invention has the following advantages:
in the forming process of the metal gates of the embodiment of the present invention, alternative gate structure to the first crystal area under control is carried out Implantation, and with the tetramethyl ammonium hydroxide solution etching not by the alternative gate structure of Implantation, because tetramethyl ammonium hydroxide solution can only etching have the fixedly silicon in crystal orientation, when Implantation in the alternative gate structure in first crystal area under control, the crystal orientation of the alternative gate structure in described first crystal area under control is destroyed by Implantation, make tetramethyl ammonium hydroxide solution can not the etching first crystal alternative gate structure in area under control, can only the etching transistor seconds alternative gate structure in district, and utilize Implantation can realize at an easy rate vertical trenched side-wall, make the metal gates of follow-up formation described trench fill can be expired, the metal gates bottom can not form hole, thereby can not affect device performance and yield.
Further; form the barrier layer between described alternative gate structure and gate dielectric layer; described barrier layer can stop that the ion that is injected in the alternative gate structure continues to be injected into the gate dielectric layer surface; and it is surperficial that described barrier layer covers described gate dielectric layer; make described gate dielectric layer can not contact with the plasma of follow-up dry etching or the etching solution of wet etching; avoid described etching solution and plasma to the destruction of gate dielectric layer, further protected gate dielectric layer.
Further, the material on described barrier layer is wherein a kind of of TiN, TaN or both laminated construction.Owing to also needing to form wherein a kind of of TiN, TaN or both laminated construction in the metal gates of follow-up formation, utilize wherein a kind of of described TiN, TaN or both laminated construction can avoid also needing to continue to remove the barrier layer as the barrier layer after removing the alternative gate structure, because the technique of removing the barrier layer also may be damaged gate dielectric layer, save processing step, avoided simultaneously gate dielectric layer to sustain damage.
Further, when etching is removed the alternative gate structure in described first crystal area under control, can directly utilize wet etching or select the coefficient dry etch process of physics and chemistry mechanism to carry out etching to the alternative gate structure in described first crystal area under control, do not need to form the steps such as photoresist layer, exposure imaging, save processing step, improved the technique integrated level.
Description of drawings
Fig. 1 is the circuit diagram of the SRAM memory cell of prior art;
Fig. 2 is the structural representation of nmos pass transistor and PMOS transistor common grid in the SRAM memory cell of prior art;
Fig. 3 is the schematic flow sheet of formation method of the metal gates of the embodiment of the present invention;
Fig. 4 to Figure 14 is the structural representation of forming process of the metal gates of the embodiment of the present invention.
Embodiment
In existing SRAM memory cell, the grid of nmos pass transistor grid common and a PMOS is electrically connected.In order to improve the device integrated level, and avoid at grid structure surface formation conductive plunger, in layout design, usually a nmos pass transistor and a PMOS transistor are shared same grid structure, please refer to Fig. 2, described common grid 21 is across the border of described nmos pass transistor district 01 and PMOS transistor area 02, and the part of described common grid 21 is positioned at nmos pass transistor district 01, and another part of described common grid 21 is positioned at PMOS transistor area 02; In nmos pass transistor district 01, the both sides of described common grid 21 are formed with N-type source/drain region 22; In PMOS transistor area 02, the both sides of described common grid 21 are formed with P type source/drain region 23.
But along with the SRAM integrated level is more and more higher, the transistorized common grid of the nmos pass transistor in SRAM and PMOS also needs to adopt metal gates to reduce the parasitic capacitance of MOS transistor grid, improves device speed.But because nmos pass transistor is different with the transistorized work function of PMOS, thus the material of the metal gates of nmos pass transistor and the transistorized metal gates of PMOS and technique all different, need to form respectively.Namely first utilize dry etch process to remove the common grid part in nmos pass transistor district 01, form the metal gates that is applicable to nmos pass transistor in the groove that etching forms; Then remove the common grid part of PMOS transistor area, form in the groove that etching forms and be applicable to the transistorized metal gates of PMOS.But because the dry etching majority is result by physical bombardment and chemical etching immixture, and utilize the chemical etching can be because the sidewall that the reason such as crystal orientation makes described groove is not vertical with the Semiconductor substrate plane, when the reacting gas of dry etching contains the atoms such as carbon, hydrogen, described trenched side-wall also can form polymer, makes the inclination that becomes of the sidewall of groove.And in order to remove the alternative gate electrode fully, usually need to be with alternative gate electrode over etching, the inclination that also easily the sidewall of groove become of described over etching, and can be to the gate dielectric layer injury.For tilting, one of them opening of groove that the groove that described nmos pass transistor district 01 forms and PMOS transistor area 02 form is up big and down small when the sidewall of described groove, and another opening is up-small and down-big.When described opening when being up-small and down-big, utilize metal sputtering technique to be difficult to channel bottom acute angle zone is filled fully full, make to produce hole in metal gates, affect the yield of device.
For this reason, the inventor has proposed a kind of formation method of metal gates through research, comprising: Semiconductor substrate is provided, and described Semiconductor substrate comprises the first transistor district and transistor seconds district; Form the alternative gate structure on described Semiconductor substrate, described alternative gate structure is positioned at described first crystal area under control and transistor seconds district simultaneously; Alternative gate structure to the first crystal area under control is carried out Implantation; Utilize tetramethyl ammonium hydroxide solution to remove not by the alternative gate structure in the transistor seconds district of Implantation, form the second groove, and form the second metal gates in described the second groove; Remove by the alternative gate structure in the first crystal area under control of Implantation, form the first groove, and form the first metal gates in described the first groove.because tetramethyl ammonium hydroxide solution can only etching have the fixedly silicon in crystal orientation, when Implantation in the alternative gate structure in first crystal area under control, the crystal orientation of the alternative gate structure in described first crystal area under control is destroyed by Implantation, make tetramethyl ammonium hydroxide solution can not the etching first crystal alternative gate structure in area under control, can only the etching transistor seconds alternative gate structure in district, and utilize Implantation can realize at an easy rate vertical trenched side-wall, make the metal gates of follow-up formation described trench fill can be expired, the metal gates bottom can not form hole, thereby can not affect device performance and yield.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
Please refer to Fig. 3, the schematic flow sheet for the formation method of the metal gates of the embodiment of the present invention specifically comprises:
Step S101 provides Semiconductor substrate, and described Semiconductor substrate comprises the first transistor district and transistor seconds district;
Step S102 forms the alternative gate structure on described Semiconductor substrate, described alternative gate structure is positioned at described first crystal area under control and transistor seconds district simultaneously;
Step S103 carries out Implantation to the alternative gate structure in first crystal area under control;
Step S104 utilizes tetramethyl ammonium hydroxide solution to remove not by the alternative gate structure in the transistor seconds district of Implantation, forms the second groove, and form the second metal gates in described the second groove;
Step S105 removes by the alternative gate structure in the first crystal area under control of Implantation, forms the first groove, and form the first metal gates in described the first groove.
Fig. 4 is the structural representation of overlooking the visual angle that the embodiment of the present invention is used to form the Semiconductor substrate 100 of SRAM memory cell, and Fig. 5 is the cross-sectional view of the Semiconductor substrate 100 of the hatching AA ' direction in Fig. 4.Due to described hatching AA ' cutting be the semiconductor structure that is positioned at first crystal area under control I, so Fig. 5 is the cross-sectional view of the Semiconductor substrate 100 that forms the first transistor.The forming process of described transistor seconds is identical with the forming process of the first transistor, and the cross-section structure of the Semiconductor substrate of described transistor seconds can obtain with reference to figure 4 and Fig. 5 in the lump.
In the lump with reference to figure 4 and Fig. 5, Semiconductor substrate 100 is provided, described Semiconductor substrate comprises the first transistor district I and transistor seconds district II, utilize ion implantation technology to form the first well region 110 in described first crystal area under control I, utilize ion implantation technology to form the second well region 120 in described transistor seconds district II, and form fleet plough groove isolation structure 130 around described the first well region 110 and the second well region 120.
Described first crystal area under control I is adjacent with transistor seconds district II, makes the second metal gates in the transistor seconds of the first metal gates in the first transistor of described first crystal area under control I of follow-up formation and transistor seconds district II be connected to each other.In the present embodiment, described first crystal area under control I and transistor seconds district II are band shape and are spaced, and each first crystal area under control I and transistor seconds district II include several transistors.
In the present embodiment, described first crystal area under control I is the PMOS transistor area, and described transistor seconds district II is the nmos pass transistor district.In other embodiments, described first crystal area under control I is the nmos pass transistor district, and described transistor seconds district II is the PMOS transistor area.
Described Semiconductor substrate 100 is wherein a kind of of silicon substrate, silicon-on-insulator substrate, silicon-Germanium substrate.In the present embodiment, because the transistor to be formed in described first crystal area under control I is the PMOS transistor, the foreign ion that described the first well region 110 injects is the N-type foreign ion, because the transistor to be formed in described transistor seconds district II is nmos pass transistor, the foreign ion that described the second well region 120 injects is the p type impurity ion.
Fig. 6 is nmos pass transistor and the transistorized structural representation of overlooking the visual angle of PMOS of the shared alternative gate structure of having of the embodiment of the present invention, and Fig. 7 is the cross-sectional view of the MOS transistor of the hatching AA ' direction in Fig. 6.Due to described hatching AA ' cutting be the semiconductor structure that is positioned at first crystal area under control I, so Fig. 7 is the cross-sectional view of the first transistor.The forming process of described transistor seconds is identical with the forming process of the first transistor, and the cross-section structure of described transistor seconds can obtain with reference to figure 6 and Fig. 7 in the lump.
In the lump with reference to figure 6 and Fig. 7, at described Semiconductor substrate 100 surface formation gate dielectric layers 140, in described gate dielectric layer 140 surface formation alternative gate structures 150, form side wall (not shown) around described gate dielectric layer 140, alternative gate structure 150, in described the first well region 110, the second well region 120 and the both sides that are positioned at described alternative gate structure 150 form respectively the first source/drain region 170, the second source/drain region 180.Concrete technology comprises: utilize chemical vapor deposition method at described Semiconductor substrate 100 surface formation gate dielectric materials (not shown), at described gate dielectric material surface formation polysilicon layer (not shown), at described polysilicon layer surface formation photoresist layer (not shown), described photoresist layer is carried out the figure that exposure imaging forms the alternative gate structural correspondence; Photoresist layer after the described exposure carries out dry etching as mask to described polysilicon layer, gate dielectric material, until expose Semiconductor substrate 100, forms alternative gate structure 150 and the gate dielectric layer 140 of strip; At described Semiconductor substrate 100, alternative gate structure 150 surface formation silicon oxide layer, silicon nitride layer or laminated construction (not shown) both, and described silicon oxide layer, silicon nitride layer or laminated construction are both carried out without mask etching, until expose Semiconductor substrate 100, form the side wall (not shown) in described alternative gate structure 150, gate dielectric layer 140 sidewall surfaces; Described the first well region 110, the second well region 120 to the both sides that are positioned at described alternative gate structure 150 carry out respectively Implantation, form the first source/drain region 170 and the second source/drain region 180.
Wherein, described gate dielectric layer 140 is silicon oxide layer or high K dielectric layer, in order to reduce the parasitic capacitance of MOS transistor grid, improves device speed, and the gate dielectric layer of the embodiment of the present invention is the high K dielectric layer.The material of described alternative gate structure 150 is polysilicon.
The alternative gate structure 150 of described strip and gate dielectric layer 140 both be positioned at the first well region 110 surfaces of first crystal area under control I, be positioned at again the second well region 120 surfaces of transistor seconds district II, make the grid of last formation the first transistor be electrically connected to the grid of transistor seconds.Due to described the first transistor and the shared grid structure of transistor seconds, make the grid structure of the first transistor and transistor seconds directly be electrically connected to, do not need to be electrically connected to by metal interconnecting layer, can avoid at described grid structure surface formation conductive plunger, reduce technology difficulty and process complexity, improved the integrated level of device.In the present embodiment, transistor in described first crystal area under control I is the PMOS transistor, the foreign ion that described the first source/drain region is injected is the p type impurity ion, transistor in described transistor seconds district II is nmos pass transistor, and the foreign ion that described the second source/drain region is injected is the N-type foreign ion.
In other embodiments, between described gate dielectric layer and alternative gate structure, also be formed with the barrier layer.Due in subsequent technique, foreign ion need to be injected in the alternative gate structure, the injection degree of depth of described foreign ion is suitable with the thickness of alternative gate structure, but described foreign ion still might be injected in gate dielectric layer, and the ion that is easy to be injected into due to the lattice structure of gate dielectric layer destroys, make the puncture voltage of gate dielectric layer, transistorized threshold voltage change, affect device performance.Therefore be formed with the barrier layer between described gate dielectric layer and alternative gate structure; described barrier layer can stop that the ion that is injected in the alternative gate structure continues to be injected into the gate dielectric layer surface; and after etching away described alternative gate structure; it is surperficial that described barrier layer still covers described gate dielectric layer; make described gate dielectric layer can not contact with the plasma of follow-up dry etching or the etching solution of wet etching; avoid described etching solution and plasma to the destruction of gate dielectric layer, further protected gate dielectric layer.
In the present embodiment, the material on described barrier layer is wherein a kind of of TiN, TaN or both laminated construction.Owing to also needing to form wherein a kind of of TiN, TaN or both laminated construction in the metal gates of follow-up formation, utilize wherein a kind of of described TiN, TaN or both laminated construction can avoid also needing to continue to remove the barrier layer as the barrier layer after removing the alternative gate structure, because the technique of removing the barrier layer also may be damaged gate dielectric layer, save processing step, avoided simultaneously gate dielectric layer to sustain damage.
Fig. 8 is nmos pass transistor and the transistorized structural representation of overlooking the visual angle of PMOS that the surface of the embodiment of the present invention is formed with interlayer dielectric layer 190, and Fig. 9 is the cross-sectional view of the MOS transistor of the hatching AA ' direction in Fig. 8.
With reference to figure 8 and Fig. 9, at described Semiconductor substrate 100 and alternative gate structure 150 surface formation interlayer dielectric layers 190, described interlayer dielectric layer 190 is carried out chemico-mechanical polishing, until expose described alternative gate structure 150 in the lump.
The material of described interlayer dielectric layer 190 is silica, tetraethoxysilane or low-K dielectric.The technique that forms described interlayer dielectric layer 190 is chemical vapour deposition (CVD).
Figure 10 to Figure 14 is the cross-sectional view of forming process of the metal gates of the hatching BB ' direction in Fig. 8.
Please refer to Figure 10, at described interlayer dielectric layer 190 and alternative gate structure 150 surface formation photoresist layers, described photoresist layer is carried out exposure imaging, expose the surface of interlayer dielectric layer 190 corresponding to first crystal area under control I and alternative gate structure 150, and take the exposure after photoresist layer 200 as mask, area under control I carries out Implantation to described first crystal.
In the present embodiment, the zone of described Implantation not only comprises the surface of the alternative gate structure 150 of first crystal area under control I, also comprises the surface of the interlayer dielectric layer 190 that the first transistor and part fleet plough groove isolation structure are corresponding.In other embodiments, the zone of described Implantation only comprises the surface of the alternative gate structure in first crystal area under control.
Because the material of alternative gate structure is polysilicon, after described alternative gate structure is by Implantation, the ion that the crystal orientation of described polysilicon is injected into destroys, make later use Tetramethylammonium hydroxide (TMAH) solution can not etch away the destroyed polysilicon in crystal orientation, and described TMAH solution can will not fall through the etching polysilicon of Implantation, thereby optionally wet etching falls the alternative gate structure in transistor seconds district.For the alternative gate structure that makes the first crystal area under control fully can be by TMAH solution institute etching, the ion that the crystal orientation of the alternative gate structure in described first crystal area under control need to all be injected into destroys, therefore, the degree of depth of the ion of described injection equals the thickness of alternative gate structure at least.When being formed with the barrier layer between described gate dielectric layer and alternative gate structure, the degree of depth of the ion of described injection can be a bit larger tham the thickness of alternative gate structure, can destroy the crystal orientation of the alternative gate structure in first crystal area under control fully with the ion that guarantee to inject.
In order more effectively to destroy the crystal orientation of alternative gate structure, improve the etching selection ratio of the alternative gate structure of the alternative gate structure of ion not and ion, can make the destroyed ground, crystal orientation of alternative gate structure in first crystal area under control more thorough by selecting the higher larger ion of Implantation Energy, diameter.In embodiments of the present invention, the foreign ion of described Implantation be boron, indium, nitrogen, phosphorus, arsenic, antimony, carbon, fluorine, chlorine, helium, argon wherein one or more, because above-mentioned foreign ion is all doping ion commonly used in semiconductor technology, can reduce production costs, improve the versatility of raw material.
form the acute angle zone for fear of the bottom of the groove of follow-up formation, make the metal gates of final formation have hole, affect device performance and even may cause component failure, the direction of described Implantation is vertical with the alternative gate body structure surface, make the zone of described alternative gate structure intermediate ion injection with not vertical with semiconductor substrate surface by the border in the zone of Implantation, the first groove of follow-up formation and the second channel bottom can not form the acute angle zone, and by improving the Implantation Energy of ion, the injection direction that makes described ion can not change in being injected into the lattice structure of polysilicon the time, the sidewall of groove that has guaranteed final formation is vertical with the plane of Semiconductor substrate.
With reference to Figure 10 and Figure 11, remove photoresist layer 200 in the lump, utilize Tetramethylammonium hydroxide (TMAH) solution to remove not by the alternative gate structure 150 of the transistor seconds district II of Implantation, form the second groove 221.
Described technique of removing photoresist layer 200 is cineration technics.
Due to TMAH solution metal ion not, and utilize the etch rate of TMAH solution etch silicon very fast, etching selection is higher, can not carry out etching to silica, silicon nitride, is a kind of comparatively desirable solution that is used for the wet etching silicon materials.Because polycrystalline silicon material is shortrange order, described TMAH solution also can carry out etching along the crystal orientation of the continuous variation of alternative gate structure.But inventor's discovery, after the crystal orientation of silicon materials was destroyed, the speed of TMAH solution etch silicon can significantly reduce.In foreign ion is injected into the alternative gate structure, regularly arranged lattice structure in described alternative gate structure is destroyed, make the crystal orientation of described alternative gate structure destroyed, TMAH solution can not carry out along the crystal orientation of silicon etching, and TMAH solution etching is injected with speed ratio etching little one to three order of magnitude of speed of the alternative gate structure of implanting impurity ion not of the alternative gate structure of foreign ion.In the present embodiment, because the crystal orientation of the alternative gate structure in first crystal area under control is destroyed, the crystal orientation of the alternative gate structure in transistor seconds district does not have destroyed, when the TMAH solution spraying when described alternative gate body structure surface or alternative gate structure are immersed in TMAH solution, the alternative gate structure in described transistor seconds district can be etched away completely, and the alternative gate structure in first crystal area under control almost is not etched, thereby forms the second groove 221 in the position of the former alternative gate structure in transistor seconds district.
In the lump with reference to Figure 11 and Figure 12, at described the second interior formation the second metal gates 222 of groove 221.
Described the second metal gates 222 can be single coating or multiple-level stack structure.
When described the second metal gates 222 is single coating, the material of described the second metal gates 222 be Al, Cu, Ag, Au, Pt, Ni wherein one or more.
When described the second metal gates 222 is the multiple-level stack structure, described the second metal gates 222 comprises: be positioned at the second groove 221 bottoms and sidewall functional layer 223, be positioned at the metal gate electrode layer 224 on described functional layer 223 surfaces, and described functional layer 223 and metal gate electrode layer 224 are filled full described the second grooves 221.
Take described the second metal gates 222 as the multiple-level stack structure as example, the concrete grammar that forms described the second metal gates 222 comprises: at alternative gate structure 150 and the second groove 221 bottoms and sidewall formation functional layer and the metal gate electrode layer of described interlayer dielectric layer 190, first crystal area under control I, described functional layer and metal gate electrode layer are filled full described the second groove 221; Described functional layer and metal gate electrode layer are carried out chemico-mechanical polishing, until functional layer and the metal gate electrode layer on described interlayer dielectric layer 190 surfaces are etched away fully, the functional layer 223 and the metal gate electrode layer 224 that are positioned at the second groove 221 bottoms and sidewall form the second metal gates 222.
The material of described functional layer 223 be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more, the material of described metal gate electrode layer 224 be Al, Cu, Ag, Au, Pt, Ni wherein one or more.Described functional layer 223 not only can be used as the diffusion impervious layer of metal gate electrode layer 224, is used for the diffusion of the material of barrier metal gate electrode layer 224, the work function that can also regulate grid structure by changing functional layer material and manufacture craft.The work function that material by adjusting described nmos pass transistor and the transistorized functional layer of PMOS and manufacture craft can change described nmos pass transistor and the transistorized grid structure of PMOS.in the present embodiment, the transistor of described the second metal gates 222 correspondences is nmos pass transistor, the technique that forms described the second metal gates comprises: utilize atom layer deposition process (Atomic Layer Deposition, ALD) at described gate dielectric layer 140 surface formation TiN films, utilize atom layer deposition process to form the TaN film in the utilization of described TiN film surface, utilize physical gas-phase deposition (Physical Vapor Deposition at described TaN film surface, PVD) form the TiAl film, utilize atom layer deposition process again to form the TiN film at described TiAl film surface, form physical gas-phase deposition in described TiN film surface utilization and form the Ti film, adopt physical gas-phase deposition to form the Al metal level at described Ti film surface.Described TiN film, TaN film, TiAl film, Ti film consist of functional layer 223, and described A1 metal level consists of metal gate electrode layer 224.The thickness range of described A1 metal level is
in one embodiment, when described functional layer is TiN, during the barrier layer of wherein a kind of of TaN or both laminated construction, can directly adopt the barrier layer as functional layer, after the alternative gate structure of removing described transistor seconds district II, keep the barrier layer, with the functional layer of described barrier layer as transistor seconds, directly form metal gate electrode layer at described barrier layer surface, the barrier layer that forms in step before directly adopting in described embodiment is as functional layer, do not need extra deposition-etch technique, saved processing step, avoided simultaneously gate dielectric layer to sustain damage.
In another embodiment, described functional layer can also be the multiple-level stack structure, comprising: be positioned at the gate dielectric layer surface the barrier layer, be positioned at the supplementary functions layer of described barrier layer surface.Described supplementary functions layer can adopt deposition, etching technics additionally to form, the material of described supplementary functions layer be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more, the present embodiment additionally forms the supplementary functions layer again at the barrier layer surface that forms before, thereby the damage that the etching technics before can repairing causes described barrier layer, the work function of avoiding only adopting the barrier layer to regulate grid structure as functional layer is regulated the too narrow defective of window.
With reference to Figure 12 and Figure 13, remove by the alternative gate structure 150 of the first crystal area under control I of Implantation in the lump, form the first groove 211.
The method of removing the alternative gate structure 150 of described first crystal area under control I comprises wherein a kind of of wet etching or dry etching.In the present embodiment, the technique of removing the alternative gate structure 150 of described first crystal area under control I is wet etching, and etching solution is KOH solution.Described KOH solution only can carry out etching to polysilicon, and because whether Implantation being arranged, polysilicon do not affect etch rate, final only the alternative gate structure 150 of first crystal area under control I can be removed, form the first groove 211 in the position of the alternative gate structure that originally is formed with the first crystal area under control.Owing to utilizing KOH solution only to understand etching alternative gate structure, do not need to form the steps such as photoresist layer, exposure imaging, saved processing step, improved the technique integrated level.
in other embodiments, when adopting dry etch process to carry out etching to the alternative gate structure in described first crystal area under control, when selecting the coefficient dry etch process of physics and chemistry mechanism, can not adopt the photoresist mask, directly the alternative gate structure in first crystal area under control is carried out, form the first through hole, because the scope of the etching selection ratio of the coefficient dry etching of physics and chemistry mechanism is 5: 1～100: 1, therefore, when removing the alternative gate structure in described first crystal area under control fully, only have the interlayer dielectric layer of very little thickness to be etched away, do not affect the performance of the semiconductor device of last formation, and the alternative gate structure of utilizing described etching technics to remove the first crystal area under control does not need to form photoresist layer, the steps such as exposure imaging, saved processing step, improved the technique integrated level.
In other embodiments, can also be at described interlayer dielectric layer, the second patterned photoresist layer of metal gates surface formation, described photoresist layer exposes the alternative gate structure in first crystal area under control, and the alternative gate structure in described first crystal area under control is carried out dry etching, forms the first groove.
In the lump with reference to Figure 13 and Figure 14, at described the first interior formation the first metal gates 212 of groove 211.
Described the first metal gates 212 can be single coating or multiple-level stack structure.
When described the first metal gates 212 is single coating, the material of described the first metal gates 212 be Al, Cu, Ag, Au, Pt, Ni wherein one or more.
When described the first metal gates 212 is the multiple-level stack structure, described the first metal gates 212 comprises: be positioned at the bottom of the first groove 211 and sidewall functional layer 213, be positioned at the metal gate electrode layer 214 on described functional layer 213 surfaces, and described functional layer 213 and metal gate electrode layer 214 are filled full described the first grooves 211.
Take described the first metal gates 212 as the multiple-level stack structure as example, the concrete grammar that forms described the first metal gates 212 comprises: form functional layer and metal gate electrode layer in described interlayer dielectric layer 190, the second metal gates 212 and the first groove 211 bottoms and sidewall, described functional layer and metal gate electrode layer are filled full described the first groove 211; Described functional layer and metal gate electrode layer are carried out chemico-mechanical polishing, until functional layer and the metal gate electrode layer on described interlayer dielectric layer 190 surfaces are etched away fully, are positioned at the bottom of the first groove 211 and functional layer 213 and the metal gate electrode layer 214 of sidewall and form the first metal gates 212.
The material of described functional layer 213 be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more, the material of described metal gate electrode layer 214 be Al, Cu, Ag, Au, Pt, Ni wherein one or more.Described functional layer 213 not only can be used as the diffusion impervious layer of metal gate electrode layer 214, is used for the diffusion of the material of barrier metal gate electrode layer 214, the work function that can also regulate grid structure by changing functional layer material and manufacture craft.The work function that material by adjusting described nmos pass transistor and the transistorized functional layer of PMOS and manufacture craft can change described nmos pass transistor and the transistorized grid structure of PMOS.in the present embodiment, the transistor of described the first metal gates 212 correspondences is the PMOS transistor, the technique that forms described the first metal gates 212 comprises: utilize atom layer deposition process at described gate dielectric layer 140 surface formation TiN films, utilize atom layer deposition process to form the TaN film in the utilization of described TiN film surface, utilize atom layer deposition process again to form the TiN film at described TaN film surface, utilize atom layer deposition process again to form the TaN film in the utilization of described TiN film surface, form physical gas-phase deposition in described TaN film surface utilization and form the Ti film, adopt physical gas-phase deposition to form the Al metal level at described Ti film surface.Described TiN film, TaN film, TiAl film, Ti film consist of functional layer 213, and described Al metal level consists of metal gate electrode layer 214.The thickness range of described Al metal level is
Because functional layer is also conducted electricity, the first metal gates and the second metal gates are electrically connected to by functional layer, and need not pass through conductive plunger, metal interconnecting layer electrical connection, can effectively improve the SRAM integrated level, reduce process complexity.
In one embodiment, when described functional layer is the barrier layer of wherein a kind of of TiN, TaN or both laminated construction, can directly adopt the barrier layer as functional layer, after the alternative gate structure of removing described first crystal area under control I, keep the barrier layer, with the functional layer of described barrier layer as the first transistor, directly form metal gate electrode layer at described barrier layer surface, the barrier layer that forms in step before directly adopting in the present embodiment is as functional layer, do not need extra deposition-etch technique, save processing step, avoided simultaneously gate dielectric layer to sustain damage.
In another embodiment, described functional layer can also be the multiple-level stack structure, comprising: be positioned at the gate dielectric layer surface the barrier layer, be positioned at the supplementary functions layer of described barrier layer surface.Described supplementary functions layer can adopt deposition, etching technics additionally to form, the material of described supplementary functions layer be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more, the present embodiment additionally forms the supplementary functions layer again at the barrier layer surface that forms before, thereby the damage that the etching technics before can repairing causes described barrier layer, the work function of avoiding only adopting the barrier layer to regulate grid structure as functional layer is regulated the too narrow defective of window.
Because the sidewall of the second groove of the first groove of the first metal gates and the second metal gates is vertical with the Semiconductor substrate plane, utilize atom layer deposition process or metal level deposited by physical vapour deposition (PVD) can fill full the first groove and the second groove fully, make between the first metal gates of final generation and the second metal gates and do not form hole, can not affect device performance and the yield of final generation.
to sum up, in the forming process of the metal gates of the embodiment of the present invention, alternative gate structure to the first crystal area under control is carried out Implantation, and with the tetramethyl ammonium hydroxide solution etching not by the alternative gate structure of Implantation, because tetramethyl ammonium hydroxide solution can only etching have the fixedly silicon in crystal orientation, when Implantation in the alternative gate structure in first crystal area under control, the crystal orientation of the alternative gate structure in described first crystal area under control is destroyed by Implantation, make tetramethyl ammonium hydroxide solution can not the etching first crystal alternative gate structure in area under control, can only the etching transistor seconds alternative gate structure in district, and utilize Implantation can realize at an easy rate vertical trenched side-wall, make the metal gates of follow-up formation described trench fill can be expired, the metal gates bottom can not form hole, thereby can not affect device performance and yield.
Further; form the barrier layer between described alternative gate structure and gate dielectric layer; described barrier layer can stop that the ion that is injected in the alternative gate structure continues to be injected into the gate dielectric layer surface; and it is surperficial that described barrier layer covers described gate dielectric layer; make described gate dielectric layer can not contact with the plasma of follow-up dry etching or the etching solution of wet etching; avoid described etching solution and plasma to the destruction of gate dielectric layer, further protected gate dielectric layer.
Further, the material on described barrier layer is wherein a kind of of TiN, TaN or both laminated construction.Owing to also needing to form wherein a kind of of TiN, TaN or both laminated construction in the metal gates of follow-up formation, utilize wherein a kind of of described TiN, TaN or both laminated construction can avoid also needing to continue to remove the barrier layer as the barrier layer after removing the alternative gate structure, do not need extra deposition-etch technique, save processing step, avoided simultaneously gate dielectric layer to sustain damage.
Further, when etching is removed the alternative gate structure in described first crystal area under control, can directly utilize wet etching or select the coefficient dry etch process of physics and chemistry mechanism to carry out etching to the alternative gate structure in described first crystal area under control, do not need to form the steps such as photoresist layer, exposure imaging, save processing step, improved the technique integrated level.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (20)
1. the formation method of a metal gates, is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises the first transistor district and transistor seconds district;
Form the alternative gate structure on described Semiconductor substrate, described alternative gate structure is positioned at described first crystal area under control and transistor seconds district simultaneously;
Alternative gate structure to the first crystal area under control is carried out Implantation;
Utilize tetramethyl ammonium hydroxide solution to remove not by the alternative gate structure in the transistor seconds district of Implantation, form the second groove, and form the second metal gates in described the second groove;
Remove by the alternative gate structure in the first crystal area under control of Implantation, form the first groove, and form the first metal gates in described the first groove.
2. the formation method of metal gates as claimed in claim 1, it is characterized in that, described Implantation vertically is injected in the alternative gate structure in first crystal area under control, makes the zone of described alternative gate structure intermediate ion injection with not vertical with semiconductor substrate surface by the border in the zone of Implantation.
3. the formation method of metal gates as claimed in claim 1, is characterized in that, the degree of depth of described Implantation is equal to or greater than the thickness of described alternative gate structure.
4. the formation method of metal gates as claimed in claim 1, is characterized in that, the foreign ion of described Implantation be boron, indium, nitrogen, phosphorus, arsenic, antimony, carbon, fluorine, chlorine, helium, argon wherein one or more.
5. the formation method of metal gates as claimed in claim 1, is characterized in that, is formed with gate dielectric layer between described alternative gate structure and Semiconductor substrate, and described gate dielectric layer is silicon oxide layer or high K dielectric layer.
6. the formation method of metal gates as claimed in claim 5, is characterized in that, also comprises, forms the barrier layer between described gate dielectric layer and alternative gate structure.
7. the formation method of metal gates as claimed in claim 6, is characterized in that, the material on described barrier layer is wherein a kind of of TiN, TaN or both laminated construction.
8. the formation method of metal gates as claimed in claim 6, is characterized in that, after the alternative gate structure of removing respectively described first crystal area under control and transistor seconds district, described barrier layer still covers the surface of the gate dielectric layer of described correspondence.
9. the formation method of metal gates as claimed in claim 1, is characterized in that, the material of described alternative gate structure is polysilicon.
10. the formation method of metal gates as claimed in claim 1, is characterized in that, described method of removing the alternative gate structure in first crystal area under control comprises wet etching or dry etching.
11. the formation method of metal gates as claimed in claim 10 is characterized in that, the described wet etching solution of removing the alternative gate structure in first crystal area under control is KOH solution.
12. the formation method of metal gates as claimed in claim 10 is characterized in that, the described dry etching of removing the alternative gate structure in first crystal area under control is the coefficient dry etch process of physics and chemistry mechanism.
13. the formation method of metal gates as claimed in claim 1, it is characterized in that, when described the first metal gates and the second metal gates are single coating, the material of described the first metal gates and the second metal gates be Al, Cu, Ag, Au, Pt, Ni wherein one or more.
14. the formation method as claim 1 or 6 described metal gates, it is characterized in that, when described the first metal gates and the second metal gates were the multiple-level stack structure, described the first metal gates and the second metal gates comprised functional layer and are positioned at the metal gate electrode layer on functional layer surface.
15. the formation method of metal gates as claimed in claim 14 is characterized in that, described functional layer is the barrier layer.
16. the formation method of metal gates as claimed in claim 14 is characterized in that, described functional layer comprises: be positioned at the gate dielectric layer surface described barrier layer, be positioned at the supplementary functions layer of described barrier layer surface.
17. the formation method of metal gates as claimed in claim 14 is characterized in that, the material of described functional layer be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more.
18. the formation method of metal gates as claimed in claim 14 is characterized in that, the material of described metal gate electrode layer be Al, Cu, Ag, Au, Pt, Ni wherein one or more.
19. the formation method of metal gates as claimed in claim 1 is characterized in that, described first crystal area under control is the PMOS transistor area, and described transistor seconds district is the nmos pass transistor district.
20. the formation method of metal gates as claimed in claim 1 is characterized in that, described first crystal area under control is the nmos pass transistor district, and described transistor seconds district is the PMOS transistor area.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104347418A (en) * | 2013-08-05 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of MOS (Metal Oxide Semiconductor) transistor |
| CN104795395A (en) * | 2014-01-20 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Static random access memory and forming method thereof |
| CN109285811A (en) * | 2017-07-20 | 2019-01-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109860037A (en) * | 2019-01-18 | 2019-06-07 | 长江存储科技有限责任公司 | The forming method of the array common source of 3D nand memory |
| CN113707555A (en) * | 2020-05-22 | 2021-11-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method for forming semiconductor structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097382A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| US20110156154A1 (en) * | 2009-12-30 | 2011-06-30 | Jan Hoentschel | High-k metal gate electrode structures formed at different process stages of a semiconductor device |
-
2011
- 2011-11-11 CN CN201110357957.8A patent/CN103107073B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097382A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| US20110156154A1 (en) * | 2009-12-30 | 2011-06-30 | Jan Hoentschel | High-k metal gate electrode structures formed at different process stages of a semiconductor device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104347418A (en) * | 2013-08-05 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of MOS (Metal Oxide Semiconductor) transistor |
| CN104347418B (en) * | 2013-08-05 | 2019-11-01 | 中芯国际集成电路制造(上海)有限公司 | The forming method of MOS transistor |
| CN104795395A (en) * | 2014-01-20 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Static random access memory and forming method thereof |
| CN104795395B (en) * | 2014-01-20 | 2018-08-10 | 中芯国际集成电路制造(上海)有限公司 | Static RAM and forming method thereof |
| CN109285811A (en) * | 2017-07-20 | 2019-01-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109285811B (en) * | 2017-07-20 | 2021-06-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109860037A (en) * | 2019-01-18 | 2019-06-07 | 长江存储科技有限责任公司 | The forming method of the array common source of 3D nand memory |
| CN113707555A (en) * | 2020-05-22 | 2021-11-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method for forming semiconductor structure |
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