JP2013004675A - Semiconductor storage device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device and a manufacturing method of the semiconductor storage device, which inhibit variation in impurity density of a well diffusion layer caused by formation of STI (Shallow Trench Isolation) and inhibits a dose loss of the well diffusion layer.SOLUTION: A semiconductor storage device comprises: a semiconductor substrate; a plurality of memory cells formed on the semiconductor substrate in a memory cell region; a plurality of semiconductor elements controlling the plurality of memory cells and formed in a peripheral circuit region; and an element isolation region isolating the plurality of memory cells from each other or isolating the plurality of semiconductor elements from each other. An impurity density of an active area where the semiconductor elements are formed in the peripheral circuit region lowers, in a horizontal direction with respect to a surface of the semiconductor substrate, from a lateral face of the element isolation region toward an inner portion of the active area.

Description

  Embodiments described herein relate generally to a semiconductor memory device and a method for manufacturing the same.

  A semiconductor memory device such as a NAND type EEPROM includes a memory cell array and a peripheral circuit for driving the memory cell array. A well diffusion layer is formed in the region of the memory cell array and the peripheral circuit. Furthermore, STI (Shallow Trench Isolation) is formed in the well diffusion layer in order to isolate adjacent memory cells in the memory cell array or to isolate semiconductor elements in the peripheral circuit.

  Conventionally, the formation of STI has been performed after the formation of the well diffusion layer. However, if the STI is formed after the well diffusion layer is formed, a part of the impurities in the well diffusion layer is removed during the formation of the STI, resulting in a dose loss. Therefore, it is necessary to set the impurity concentration of the well diffusion layer high in advance. Another problem is that the impurity concentration of the well diffusion layer changes before and after the formation of STI.

JP 2007-208152 A

  Provided are a semiconductor memory device and a method for manufacturing the same, in which a change in impurity concentration of a well diffusion layer due to the formation of STI is suppressed and a dose loss of the well diffusion layer is suppressed.

  The semiconductor memory device according to the present embodiment includes a semiconductor substrate. In the memory cell region, a plurality of memory cells are formed on a semiconductor substrate. A plurality of semiconductor elements that control the plurality of memory elements are formed in the peripheral circuit region. The element isolation region separates a plurality of memory cells or separates a plurality of semiconductor elements. The impurity concentration of the active area in which the semiconductor element is formed in the peripheral circuit region decreases from the side surface of the element isolation region toward the inside of the active area in the horizontal direction with respect to the surface of the semiconductor substrate.

FIG. 2 is a plan view of a NAND type EEPROM according to the present embodiment. Sectional drawing along the AA line of FIG. 1 (A), and sectional drawing along the BB line of FIG. 1 (B). The figure which shows the density | concentration distribution of the well diffusion layer. Sectional drawing which shows the manufacturing method of the semiconductor memory device by this embodiment. FIG. 5 is a cross-sectional view illustrating the method for manufacturing the semiconductor memory device following FIG. 4. FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor memory device, following FIG. 5. FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor memory device, following FIG. 6.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

  FIG. 1A and FIG. 1B are plan views of the NAND type EEPROM according to the present embodiment. 1A shows a partial plan view of the memory cell region, and FIG. 1B shows a plan view of one transistor formed in the peripheral circuit region.

  In the memory cell region, element isolation regions STI (Shallow Trench Isolation) and active areas AA are alternately formed in a stripe shape. In the memory cell region, each width of the element isolation region STI and the active area AA is formed very narrow by a lithography technique or a sidewall processing technique, and is, for example, F (Feature size).

  In the memory cell region, a plurality of memory cells MC are formed on the active area AA and are two-dimensionally arranged in a matrix. The control gate CG (word line WL) extends in a direction perpendicular to the extending direction of the element isolation region STI and the active area AA. The memory cells MC are provided corresponding to the intersections of the active area AA and the control gate CG, respectively. The plurality of memory cells MC are connected in series in the extending direction of the active area AA, and constitute a NAND string.

  The bit line BL is provided above the control gate CG so as to correspond to each active area AA, and extends in the same direction as the active area AA. In the drawing, the bit line BL is not shown for convenience.

  On the other hand, a plurality of semiconductor elements are formed in the peripheral circuit region in order to control the memory cell region. FIG. 1B shows one transistor formed on the active area AA for convenience. In many cases, the active area AA in the peripheral circuit area is formed wider than the active area AA in the memory cell area.

  An IPD (Inter Poly-Si Dielectric) etching region EI is a region that electrically connects the material of the control gate and the material of the floating gate. Due to the IPD etching region EI, the material of the control gate and the material of the floating gate function as the same gate electrode G in the transistors in the peripheral circuit region.

  FIG. 2A is a cross-sectional view taken along the line AA in FIG. FIG. 2B is a cross-sectional view taken along line BB in FIG.

  As shown in FIG. 2A, the NAND-type EEPROM according to the present embodiment includes a plurality of memory cells MC formed on a silicon substrate 10 as a semiconductor substrate. The element isolation region STI is provided between the active areas AA and electrically isolates a plurality of memory cells MC.

  In each active area AA, a well diffusion layer 20 is formed. The well diffusion layer 20 is provided over the entire active area AA and the bottom of the element isolation region STI.

  In the memory cell region, the impurity concentration of the well diffusion layer 20 in the active area AA increases from the surface of the active area AA toward the bottom of the element isolation region STI. As a result, it is possible to suppress the charge from passing between adjacent memory cells MC. In other words, data disturbance between adjacent memory cells MC is suppressed.

  Further, the width Waa of the active area AA in the extending direction of the word line WL is narrowed from the bottom of the active area AA toward the surface. That is, the active area AA has a taper from the bottom to the surface of the active area AA in the cross section in the extending direction of the word line WL. The width Waa may be rephrased as a width between a plurality of adjacent element isolation regions STI. The element isolation region STI is narrowed from the surface to the bottom surface of the element isolation region STI. That is, the element isolation region STI has a taper from the surface to the bottom surface of the element isolation region STI in the cross section in the extending direction of the word line WL. Thereby, after forming the trench in the element isolation region STI, impurities can be ion-implanted into the inclined side surface of the active area AA. Thereby, the well diffusion layer 20 can be formed in the memory cell region.

  A tunnel insulating film 30 is formed on the active area AA. The tunnel insulating film 30 is formed using, for example, a silicon oxide film. A floating gate FG is provided on the tunnel insulating film 30. The floating gate FG is formed using, for example, polysilicon.

  An IPD film 40 is provided on the upper surface and part of the side surface of the floating gate FG. The IPD film 40 is formed using, for example, a silicon oxide film or a high-k film having a dielectric constant higher than that of the silicon oxide film.

  A control gate CG (word line WL) is provided on the IPD film 40. The control gate CG is formed using a low-resistance material such as polysilicon, silicide, or metal. Further, the control gate CG is buried between a plurality of adjacent floating gates FG in order to increase the coupling capacitance between the control gate CG and the floating gate FG.

  On the floating gate FG, an interlayer insulating film, a wiring, a bit line, etc. (not shown) are further formed.

  In the peripheral circuit region, the tunnel insulating film 30 functions as a gate insulating film of the transistor Tr. The material of the control gate CG and the material of the floating gate FG are electrically connected in the IPD etching region EI. Thereby, the control gate CG and the floating gate FG function as the gate electrode G of the transistor Tr in the peripheral circuit region. The IPD film 40 is removed in the IPD etching region EI.

  In the peripheral circuit region, the well diffusion layer 20 is formed on the side portion of the active area AA and the bottom portion of the element isolation region STI, but is not formed on the entire active area AA. The width of the active area AA in the peripheral circuit area is larger than the width of the active area AA in the memory cell area. Therefore, when an impurity is ion-implanted from the side surface of the active area AA through the trench of the element isolation region STI, the impurity is diffused in the side portion of the active area AA in the peripheral circuit region, but not diffused in its entirety. In the active area AA in the peripheral circuit region, a well diffusion layer can be formed separately from the well diffusion layer 20 in the memory cell region.

  FIG. 3A and FIG. 3B are diagrams showing the concentration distribution of the well diffusion layer 20. In FIG. 3A, the inclination angle of the side surface of the active area AA is 89 degrees with the surface of the silicon substrate 10 as a reference (0 degree). In FIG. 3B, the inclination angle of the side surface of the active area AA is 88 degrees with the surface of the silicon substrate 10 as a reference (0 degree). The devices shown in FIGS. 3A and 3B only differ in the inclination angle of the side surface of the active area AA, and the other configurations may be the same.

  In the NAND type EEPROM used in this specific example, the width Waa1 of the active area AA of the memory cell region on the surface of the silicon substrate 10 is about 30 nm, and the width Wsti1 of the element isolation region STI is about 20 nm. The depth of the trench TR in the element isolation region STI was about 270 nm. Note that the depth of the trench TR is the depth of the trench when the impurity of the well diffusion layer 20 is ion-implanted. Therefore, the depth of trench TR includes the thicknesses of tunnel insulating film (gate insulating film) 30, floating gate FG, and mask material 110.

  The width Waa2 of the active area AA in the peripheral circuit region on the surface of the silicon substrate 10 was about 120 nm, and the width Wsti2 of the element isolation region STI was about 100 nm. The depth of the trench in the element isolation region STI was about 270 nm as described above. Further, the impurities in the well diffusion layer 20 are implanted from a direction substantially perpendicular to the surface of the silicon substrate 10.

As shown in FIG. 3A, when the inclination angle of the side surface of the active area AA is 89 degrees, the impurities in the well diffusion layer 20 are not sufficiently implanted into the active area AA in the memory cell region, and the bottom of the trench TR Is injected at a high concentration. For example, in FIG. 3A, the impurity concentration at the bottom of the trench TR is about 10 ¹⁸ cm ⁻³ , but is about 10 ¹⁵ cm ⁻³ to 10 ¹⁶ cm ⁻³ in the active area AA. This is because the slope of the side surface of the active area AA is steep.

On the other hand, as shown in FIG. 3B, when the inclination angle of the side surface of the active area AA is 88 degrees, the impurity of the well diffusion layer 20 is sufficiently implanted into the active area AA of the memory cell region. I understand that. High concentration is also injected into the bottom of the trench TR. For example, in FIG.3 (B), it is about 10 < ¹⁷ > cm ^{< -3} > ^-10 < ¹⁸ > cm ^{< -3} > in active area AA. The impurity concentration at the bottom of the trench TR is about 10 ¹⁸ cm ⁻³ . That is, in order to form the well diffusion layer 20 having a sufficient impurity concentration in the active area AA of the memory cell region, it is preferable that the inclination angle of the side surface of the active area AA is 88 degrees or less (0 degrees or more).

In this case, as shown in FIG. 3B, in the peripheral circuit region, the impurity concentration of the active area AA is from the inner surface of the trench TR of the element isolation region STI in the horizontal direction D1 with respect to the surface of the silicon substrate 10. It gradually decreases toward the inside of the active area AA. That is, in the peripheral circuit region, the impurity concentration of the active area AA in the vicinity of the inner surface of the trench TR is as high as about 10 ¹⁷ cm ⁻³ or more. The impurity concentration gradually decreases from the inner side surface of the trench TR toward the inside of the active area AA in the direction D1, and the impurity concentration at the center of the active area AA is about 10 ¹⁵ cm ⁻³ . In the memory cell region, the impurity concentration of active area AA gradually increases toward the bottom of trench TR with respect to the surface of silicon substrate 10.

  Thus, by making the inclination of the side surface of the active area AA with respect to the surface of the silicon substrate 10 equal to or less than 88 degrees, the well diffusion layer 20 having a sufficient impurity concentration in the active area AA of the memory cell region having the fine memory cells MC. Can be selectively formed. On the other hand, no well diffusion layer is formed in the relatively large active area AA in the peripheral circuit region.

  According to this embodiment, since the trench TR of the element isolation region STI has a taper, impurities can be implanted through the trench TR, thereby forming the well diffusion layer 20. Accordingly, dose loss is unlikely to occur when the element isolation region STI is formed.

  The width Waa2 of the active area AA in the peripheral circuit region is wider than the width Waa1 of the active area AA in the memory cell region. Therefore, the well diffusion layer 20 is formed in the entire active area AA in the memory cell region Rmc, but is not formed as a well in the active area AA in the peripheral circuit region. Therefore, the well diffusion layer 20 can be selectively formed in the memory cell region Rmc with a necessary impurity concentration.

  4 to 7 are sectional views showing the method for manufacturing the semiconductor memory device according to the present embodiment. 4 to 7, Rmc represents a cross section of the memory cell region, and Rpp represents a cross section of the peripheral circuit region.

  First, a P-type silicon substrate 10 is prepared, and an N-type well diffusion layer (not shown) is formed in the peripheral circuit region Rpp as necessary. At this time, the N-type well diffusion layer is formed using a lithography technique and an impurity implantation technique.

  Next, a tunnel insulating film 30 as a first insulating film is formed on the silicon substrate 10 using a thermal oxidation method or a CVD (Chemical Vapor Deposition) method. The tunnel insulating film 30 may be, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

  Subsequently, the material of the floating gate FG as the first conductor film is deposited on the tunnel insulating film 30 by using LPCVD (Low Pressure-CVD) method. As a material of the floating gate FG, for example, doped polysilicon containing impurities such as phosphorus, arsenic, or boron is used. Next, a mask material 110 is deposited on the floating gate FG by using the CDV method. Thereby, the structure shown in FIG. 4 is obtained. The mask material 110 is formed using, for example, a silicon oxide film or a silicon nitride film.

  Next, the mask material 110 is processed into a plane pattern of the floating gate FG of the memory cell MC and a plane pattern of the gate electrode of the transistor Tr by using a lithography technique and RIE (Reactive Ion Etching) method. That is, the mask material 110 is processed so as to separate the memory cells MC or remove the mask material 110 in the element isolation region STI that separates elements in the peripheral circuit region.

  Further, using the mask material 110 as a mask, the material of the floating gate FG, the tunnel insulating film 30 and the silicon substrate 10 are etched by the RIE method. As a result, a trench TR is formed as shown in FIG. At this time, the inner side surface of trench TR (side surface of active area AA) has an inclination of 0 degree or more and 88 degrees or less with respect to the surface of silicon substrate 10. Thereby, trench TR is formed to have a taper.

  Next, using the mask material 110 as a mask as it is, a P-type impurity (for example, boron) is ion-implanted into the silicon substrate 10 in order to form the well diffusion layer 20. At this time, the impurities are implanted in a direction substantially perpendicular to the surface of the silicon substrate 10 (0 degree ion implantation). Impurities are implanted into the bottom of trench TR through trench TR. At the same time, since the trench TR has a taper, impurities are also injected from the inner side surface (side surface of the active area AA) of the trench TR. Then, by heat-treating the silicon substrate 10, impurities are diffused in the active area AA and the impurities are activated. Thereby, the well diffusion layer 20 is obtained as shown in FIG.

  Here, in the memory cell region Rmc, the well diffusion layer 20 is formed in the entire relatively small active area AA. On the other hand, in the peripheral circuit region Rpp, impurities are implanted into the side portion of the relatively wide active area AA, and the impurities are not diffused to the inside.

  Next, after removing the mask material 110, an element isolation insulating film 120 is embedded in the trench TR. The element isolation insulating film 120 is, for example, a silicon oxide film. The element isolation region STI is formed by etching back the element isolation insulating film 120. At this time, the element isolation insulating film 120 is etched until the upper surface and the upper portion of the side surface of the floating gate FG are exposed.

  Next, an IPD film 40 as a second insulating film is deposited on the upper surface and side surfaces of the floating gate FG by using a CVD method or the like. Next, the IPD film 40 in the IPD etching region EI is removed using a lithography technique and an RIE method. Thereby, the material of the control gate CG can be electrically connected to the material of the floating gate FG in the peripheral circuit region.

  Next, a material for the control gate CG (word line WL) as the second conductor film is deposited on the IPD film 40 using LPCVD or the like. Thereby, the structure shown in FIG. 7 is obtained.

  Using the lithography technique and the RIE method, the material of the control gate CG and the material of the IPD film 40 are processed into a pattern of the word line WL. Thereby, the control gate CG (word line WL) and the IPD film 40 are formed.

  After that, by forming an interlayer insulating film, wiring, bit line, etc., the NAND type EEPROM according to the present embodiment is completed.

  According to the present embodiment, the well diffusion layer 20 is formed after the trench TR of the element isolation region STI is formed. Accordingly, dose loss is unlikely to occur when the element isolation region STI is formed. Therefore, the impurity concentration to be implanted in the ion implantation process when forming the well diffusion layer 20 may be lower than the conventional one. This improves the throughput of the ion implantation process.

  Further, the ion implantation for forming the well diffusion layer 20 is performed using the mask material 110 used for forming the trench TR as it is as a mask. Therefore, a lithography process for forming the well diffusion layer 20 is not required, and the manufacturing process is shortened compared with the conventional process. As a result, the manufacturing cost of the semiconductor memory device can be reduced.

  The width Waa2 of the active area AA in the peripheral circuit region is wider than the width Waa1 of the active area AA in the memory cell region Rmc. Therefore, the well diffusion layer 20 is formed in the entire memory cell region Rmc and the active area AA, but not in the active area AA in the peripheral circuit region. Therefore, the well diffusion layer 20 can be selectively formed in the memory cell region Rmc with a necessary impurity concentration. On the other hand, a well diffusion layer may be formed in the active area AA in the peripheral circuit region as necessary before forming the trench TR.

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate, 20 ... Well diffusion layer, 30 ... Tunnel insulating film, 40 ... IPD film, AA ... Active area, STI ... Element isolation region, FG ... Floating Gate, CG ... Control gate, MC ... Memory cell, Tr ... Transistor, TR ... Trench

Claims (7)

A semiconductor substrate;
A memory cell region including a plurality of memory cells formed on the semiconductor substrate;
A peripheral circuit region including a plurality of semiconductor elements for controlling the plurality of memory elements;
An element isolation region for isolating a plurality of the memory cells, or isolating a plurality of the semiconductor elements,
The impurity concentration of the active area in which the semiconductor element is formed in the peripheral circuit region is decreased from the side surface of the element isolation region toward the inside of the active area in the horizontal direction with respect to the surface of the semiconductor substrate. A semiconductor memory device.   2. The impurity concentration of an active area in which the memory cell is formed in the memory cell region increases from the surface of the semiconductor substrate toward the bottom of the element isolation region. Semiconductor memory device.   3. The semiconductor memory device according to claim 1, wherein the active areas of the memory cell region and the peripheral circuit region have a taper.   The semiconductor memory device according to claim 3, wherein an inclination of a side surface of the active area with respect to a surface of the semiconductor substrate is 88 ° or less. A method for manufacturing a semiconductor memory device, comprising: a memory cell region including a plurality of memory cells; and a peripheral circuit region including a plurality of semiconductor elements that control the plurality of memory elements,
Forming at least a first insulating film and a first conductor film on a semiconductor substrate;
Depositing a mask material over the first conductor film;
The mask material is processed so as to separate the memory cells or to remove the mask material in an element isolation region that separates the semiconductor elements,
Using the mask material as a mask, the first conductor film, the first insulating film, and the semiconductor substrate are etched to form an element isolation trench so that an inner surface has an inclination,
Introducing impurities into the semiconductor substrate to inject impurities into the inner surface of the trench through the trench using the mask material as a mask to form a well diffusion layer,
A method for manufacturing a semiconductor memory device, comprising: isolating elements by embedding an isolation insulating film in the trench.   The method of manufacturing a semiconductor memory device according to claim 5, wherein an inclination of an inner side surface of the trench with respect to a surface of the semiconductor substrate is 88 ° or less.   7. The method of manufacturing a semiconductor memory device according to claim 5, wherein in forming the well diffusion layer, impurities are implanted in a direction substantially perpendicular to the surface of the semiconductor substrate.