JP2007067362A - Method for manufacturing non-volatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a non-volatile semiconductor memory device capable of forming an embedded bit line structure by a simple method in a non-volatile semiconductor memory device using a charge trap layer as a memory device. <P>SOLUTION: A p-type well 4, an isolation diffusion layer 2, the charge trap layer 5, and a bit line processing film 8 are sequentially formed on a semiconductor substrate, the film 8 is processed with a bit line formation mask, a bit line diffusion layer 1 is self-aligned by an ion implantation process with these as masks, an embedded insulating film 7 is entirely deposited, the formed portion is flattened by a CMP process, the film 8 is removed, a word line electrode 3 is entirely deposited, and the electrode 3 is processed. This allows the height of a material at the time of word line processing to be decreased because the material that is processed at the time of word line formation can be a single-layer polysilicon film only, and also allows a manufacturing process to be simple because an embedded bit line structure can be formed of a single-layer polysilicon. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device using a non-conductive charge trap layer as a memory element.

  In recent years, with higher integration and lower cost of nonvolatile semiconductor memory devices, MONOS memory technology has been proposed in which a non-conductive charge trap layer (such as SiN) is used as a memory element to locally trap charges.

  In the MONOS memory according to the prior art, since charges are accumulated in the entire non-conductive charge trap layer in the gate region, only one bit of data can be stored in one memory cell. However, if a local trap type MONOS memory technology that traps charges locally in a non-conductive charge trap layer (SiN or the like) is used, data of 2 bits can be stored in one memory cell. This is advantageous for reducing the cost and cost. That is, the local trap type MONOS memory can accumulate charges independently on the source side and the drain side of the trap film (SiN). For this reason, 1 bit can be stored depending on whether or not there is a charge on the source side, and 1 bit can be stored depending on whether or not there is a charge on the drain side.

  Many local trap type MONOS memories often use a buried bit line structure in order to reduce the cell size, and various manufacturing methods have been proposed.

  Hereinafter, a method of manufacturing a nonvolatile semiconductor memory device having a buried bit line structure according to the prior art will be described with reference to the drawings (for example, see Patent Document 1).

  First, the memory cell array structure will be described with reference to FIGS. 1, 2, and 14 to 17.

  FIG. 1 is a circuit diagram showing an electrical connection structure of a memory cell array. As shown in FIG. 1, word lines (WL0 to WL3) are arranged in the row direction, and bit lines (BL0 to BL4) are arranged in the column direction. Actually, it is composed of a large number of word lines and bit lines, but for simplicity, a circuit diagram for 16 cells is shown here.

  The word line electrically connects the gate electrodes of the memory cells arranged in the row direction, and the bit line electrically connects the source / drain diffusion layers of the memory cells arranged in the column direction. . Further, the source / drain diffusion layers of memory cells adjacent in the row direction are electrically short-circuited. Thereby, dense memory cell arrangement is possible.

  FIG. 2 is a plan view of the memory cell array described in FIG. As shown in FIG. 2, a word line electrode 3 is arranged in the row direction, and a bit line diffusion layer 1 is arranged in the column direction, which respectively constitute a word line and a bit line. An isolation diffusion layer 2 is disposed between adjacent bit line diffusion layers 1 to electrically isolate adjacent bit line diffusion layers 1. As will be described with reference to a cross-sectional view, the bit line diffusion layer 1 and the isolation diffusion layer 2 are buried under the word line electrode 3 and extend in the column direction, and have a so-called buried bit line structure.

  In FIG. 2, cut sections of the cross-sectional views described in FIGS. 14 to 17 are indicated by symbols A, B, C, and D.

  14 is a cross-sectional view taken along the line AA in FIG. As shown in FIG. 14, bit line diffusion layers 1 and isolation diffusion layers 2 are alternately formed on a P-type well 4 formed on a semiconductor substrate, and a charge trap layer 5 is formed on the bit line diffusion layers 1 and charge trap layers. Lower gate electrodes 6 and buried insulating films 7 are alternately formed on the upper portion of the layer 5, and the word line electrodes 3 are disposed on the upper portions thereof. As will be described in detail later, the bit line diffusion layer 1 is formed in a self-aligned manner between the adjacent lower gate electrodes 6. In addition, the charge trap layer 5 usually has a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film.

  15 is a cross-sectional view taken along the line BB in FIG. As shown in FIG. 15, bit line diffusion layers 1 and isolation diffusion layers 2 are alternately formed on a P-type well 4, and a charge trap layer 5 is formed thereon. Actually, a metal interlayer insulating film is formed on the upper portion, but the illustration is omitted here.

  16 is a cross-sectional view taken along the line CC of FIG. As shown in FIG. 16, the separation diffusion layer 2 is formed on the P-type well 4, the charge trap layer 5 is formed thereon, and the lower gate electrode 6 formed in a stack gate shape on the charge trap layer 5. And the word line electrode 3 are arranged. In practice, a metal interlayer insulating film is formed between and above the stack gates, but the illustration is omitted here.

  17 is a cross-sectional view taken along the line DD of FIG. As shown in FIG. 17, the bit line diffusion layer 1 is formed on the P-type well 4, the charge trap layer 5 is formed on the bit line diffusion layer 1, and the buried insulating film 7 is formed on the charge trap layer 5. The word line electrode 3 is disposed on the side.

  Next, referring to FIGS. 18A and 18B to FIGS. 22A and 22B (cross-sectional views taken along the lines AA and CC in FIG. 2), a semiconductor memory device having a buried bit line structure. The manufacturing method will be described.

  First, as shown in FIGS. 18A and 18B, a P-type well 4, an isolation diffusion layer 2, a charge trap layer 5, a lower gate electrode 6, and a bit line processed film 8 are sequentially formed on a semiconductor substrate. . Here, the P-type well 4 is formed by boron implantation, the isolation diffusion layer 2 is formed by boron implantation shallower than the P-type well 4, and the charge trap layer 5 is formed of a silicon oxide film having a thickness of about 7 nm from the bottom. The silicon nitride film is formed of a 10 nm silicon oxide film, the lower gate electrode 6 is formed of a polysilicon film of about 100 nm, and the bit line processing film 8 is formed of a silicon oxide film of about 10 nm and a silicon nitride film of about 100 nm. It is formed.

  Next, as shown in FIGS. 19A and 19B, in the AA sectional view, the bit line processing film 8 and the lower gate electrode 6 are processed by the bit line formation mask, and these are further masked. The bit line diffusion layer 1 is formed by ion implantation in a self-aligning manner. Here, the bit line processed film 8 and the lower gate electrode 6 are normally processed at a pitch of the minimum processing rule. The bit line diffusion layer 1 is formed by arsenic implantation. Here, the bit line processed film 8 is used as a hard mask for forming the lower gate electrode 6.

  Next, as shown in FIGS. 20A and 20B, a buried insulating film 7 is deposited on the entire surface and flattened by a CMP method. Here, a silicon oxide film is usually used for the buried insulating film 7.

  Next, as shown in FIGS. 21A and 21B, the bit line processed film 8 is removed, and the word line electrode 3 is deposited on the entire surface. Here, the word line electrode 3 is formed of a polysilicon film of about 100 nm.

  Next, as shown in FIGS. 22A and 22B, the word line electrode 3 and the lower gate electrode 6 are processed into a stacked gate using a word line formation mask. Here, the word line formation mask is usually processed at a pitch of the minimum processing rule.

As described above, in the prior art, a buried bit line structure is realized by using a two-layer polysilicon film and a buried oxide film formed by CMP.
JP 2000-31436 A

  However, in the above prior art, since the lower gate electrode 6 is formed, the height of the material to be processed becomes high, and it is difficult to miniaturize in consideration of the processing accuracy. Furthermore, the manufacturing process is complicated and the manufacturing cost is increased.

  The present invention has been made in view of the above-described problems, and can be applied to miniaturization of a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device can be manufactured by a simpler process. The aim is to realize the method.

  In order to achieve the above object, the method for manufacturing a nonvolatile semiconductor memory device according to the present invention uses a single-layer film made of, for example, a silicon nitride film as a material to be processed when forming a bit line, and forms a word line. The material to be processed is only a single layer film made of, for example, a polysilicon film.

  Specifically, the method for manufacturing a nonvolatile semiconductor memory device of the present invention includes a first step of forming a charge trap layer on a semiconductor substrate, and a second step of forming a bit line processed film on the charge trap layer. A third step of selectively etching away the bit line processed film to form an opening for forming the bit line; a fourth step of introducing impurities for forming the bit line into the semiconductor substrate from the opening; A fifth step of exposing the upper portion of the bit line processed film after embedding the insulating film in the opening, a sixth step of removing the bit line processed film, a region from which the bit line processed film is removed, and the insulating film; A seventh step of forming a gate electrode formation film thereon, and an eighth step of selectively removing the gate electrode formation film by etching to form a word line;

  According to this method, the height of the gate electrode can be reduced, and a simple manufacturing method can be realized.

  In the above-described method for manufacturing a nonvolatile semiconductor memory device of the present invention, the charge trap layer is preferably composed of three layers of a silicon oxide film, a silicon nitride film, and a silicon oxide film.

  According to this method, a MONOS type memory can be formed.

  In the method for manufacturing a nonvolatile semiconductor memory device of the present invention, the charge trap layer may be composed of a silicon oxide film containing minute silicon grains.

  According to this method, a nanocrystal memory can be formed.

  In the method for manufacturing a nonvolatile semiconductor memory device of the present invention, the bit line processed film is made of, for example, a single layer silicon nitride film.

  According to this method, it is possible to manufacture with a general material for semiconductor manufacturing.

  In the method for manufacturing the nonvolatile semiconductor memory device of the present invention, the gate electrode formation film is made of, for example, a single layer polysilicon film.

  According to this method, it is possible to manufacture with a general material for semiconductor manufacturing.

  In the method for manufacturing a nonvolatile semiconductor memory device of the present invention, it is preferable that an oxidation step is provided between the third step and the fifth step.

  According to this method, a protective oxide film thickness at the time of impurity implantation can be secured.

  In the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, it is preferable that an oxidation step is provided between the sixth step and the seventh step.

  According to this method, the film characteristics of the charge trap layer can be improved.

  In the method for manufacturing a nonvolatile semiconductor memory device of the present invention, it is preferable that an impurity is introduced into the semiconductor substrate between the sixth step and the seventh step.

  According to this method, diffusion of impurities can be suppressed and a finer memory can be formed.

  According to this method, the heat treatment after ion implantation can be reduced, the distribution in the depth direction of ions (impurities) for controlling the threshold voltage can be suppressed, the short channel effect can be enhanced, and miniaturization can be achieved. Is advantageous.

  In the method for manufacturing a nonvolatile semiconductor memory device of the present invention, the second step includes a step of further forming a hard mask film on the bit line processed film, and the third step includes a hard mask film and It is preferable to selectively etch away the bit line processed film to form an opening for forming a bit line.

  According to this method, a film thickness necessary for preventing implanted ions from penetrating into the charge trap layer is ensured by the hard mask film and the bit line processed film, and the height of the buried insulating film is set by the bit line processed film 8. Therefore, the optimum film thickness can be set for each.

  In the method for manufacturing a nonvolatile semiconductor memory device of the present invention, for example, the hard mask film is made of a silicon oxide film.

  According to this method, it is possible to manufacture with a general material for semiconductor manufacturing.

  According to the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, since the material to be processed when forming the bit line can be only a single layer film, the height of the material at the time of bit line processing can be reduced. In addition, since the material to be processed when forming the word line can be only a single layer film, the height of the material at the time of word line processing can be reduced, and therefore processing can be performed with high accuracy.

  Furthermore, since a buried bit line structure can be formed with a single-layer bit line processed film, the manufacturing process is simplified, accurate processing is possible, and instability of electrical connection as in the prior art does not occur.

(First embodiment)
A method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention will be described below with reference to the drawings.

  First, the memory cell array structure will be described with reference to FIGS.

  Since FIG. 1 and FIG. 2 are the same as the prior art, description thereof is omitted.

  FIG. 3 is a cross-sectional view taken along the line AA of FIG. As shown in the figure, bit line diffusion layers 1 and isolation diffusion layers 2 are alternately formed on a P-type well 4, a charge trap layer 5 is formed thereon, and a buried insulating film is formed above the charge trap layer 5. 7 is formed in a slit shape, and the word line electrode 3 is disposed between and above the slit 7. Although the manufacturing method will be described later, the bit line diffusion layer 1 is formed in a self-aligned manner directly under the buried insulating film 7. In addition, the charge trap layer 5 normally has a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film, but may be a silicon oxide film containing minute silicon grains.

  4 is a cross-sectional view taken along line BB in FIG. As shown in the figure, bit line diffusion layers 1 and isolation diffusion layers 2 are alternately formed on a P-type well 4, and a charge trap layer 5 is formed thereon. Actually, a metal interlayer insulating film is formed on the upper portion, but the illustration is omitted here.

  5 is a cross-sectional view taken along the line CC of FIG. As shown in the figure, an isolation diffusion layer 2 is formed on a P-type well 4, a charge trap layer 5 is formed thereon, and a word line electrode 3 is disposed on the charge trap layer 5. Actually, a metal interlayer insulating film is formed between and above the word line electrodes 3, but the illustration is omitted here.

  6 is a cross-sectional view taken along the line DD of FIG. As shown in the figure, a bit line diffusion layer 1 is formed on a P-type well 4, a charge trap layer 5 is formed thereon, a buried insulating film 7 is formed on the charge trap layer 5, and a word insulating layer 7 is formed thereon. A line electrode 3 is arranged.

  Next, with reference to FIGS. 7A and 7B to FIGS. 12A and 12B (cross-sectional views taken along the lines AA and CC in FIG. 2), a method for manufacturing a buried bit line structure will be described. explain.

  First, as shown in FIGS. 7A and 7B, a P-type well 4, an isolation diffusion layer 2, a charge trap layer 5, and a bit line processed film 8 are sequentially formed on a semiconductor substrate. Here, the P-type well 4 is formed by boron implantation, the isolation diffusion layer 2 is formed by boron implantation shallower than the P-type well 4, and the charge trap layer 5 is a silicon oxide film of about 7 nm from the bottom, about 10 nm. The silicon nitride film is formed from a silicon oxide film of about 10 nm, and the bit line processed film 8 is formed of a silicon nitride film of about 100 nm.

  The implantation for forming the isolation diffusion layer 2 also serves as the threshold voltage control implantation for the memory cell, but the threshold voltage control implantation for the memory cell is performed in the third embodiment of the present invention. As described in the embodiment, it is possible to inject in a separate step. Further, the isolation diffusion layer 2 may be injected only between the word line electrodes 3 after the word line electrodes 3 are processed.

  Next, as shown in FIGS. 8A and 8B, in the AA sectional view, the bit line processing film 8 is processed with the bit line formation mask, and the processed bit line processing film 8 is used as a mask. The bit line diffusion layer 1 is formed by ion implantation in a self-aligning manner. Here, the bit line processed film 8 is normally processed at a pitch of the minimum processing rule. The bit line diffusion layer 1 is formed by arsenic implantation. Here, unlike the prior art, since the lower gate electrode 6 is not provided in the lower layer of the bit line processed film 8 and the charge trap layer 5 is directly formed, the height of the processed bit line processed film 8 is Low compared to technology.

  It is important that the thickness of the bit line processed film 8 is set so that the implanted ions do not penetrate into the charge trap layer 5.

  When the bit line processed film 8 is processed, all of the ONO film (silicon oxide film-silicon nitride film-silicon oxide film) formed as the charge trap layer 5 may be left, or conversely, all of the ONO film may be removed. Alternatively, some of these layers may be left. That is, the charge trap layer 5 may exist between adjacent memory cells, or may be removed until the bit line diffusion layer is exposed. This is because the (buried) insulating film region on the bit line diffusion layer has a stacked structure of a charge trap layer and a buried insulating film formed thereon or a single-layer structure of the buried insulating film. This is because the insulating film for separating adjacent memory cells is the same.

  Next, as shown in FIGS. 9A and 9B, a buried insulating film 7 is deposited on the entire surface and planarized by CMP. Here, a silicon oxide film is used for the buried insulating film 7.

  Next, as shown in FIGS. 10A and 10B, the bit line processed film 8 is removed.

  Next, as shown in FIGS. 11A and 11B, the word line electrode 3 is deposited on the entire surface. Here, the word line electrode 3 is formed of a polysilicon film of about 100 to 200 nm.

  Next, as shown in FIG. 12, the word line electrode 3 is processed using a word line formation mask. Here, the word line electrode 3 is normally processed at a pitch of the minimum processing rule.

  As described above, according to the present embodiment, the film processed with the bit line formation mask is only the single-layer bit line processed film 8 having a height of about 100 nm. On the other hand, the prior art is complicated with a three-layer structure of a lower gate electrode 6 (about 100 to 200 nm polysilicon film) and a bit line processed film 8 (about 10 nm silicon oxide film and about 100 nm silicon nitride film), In addition, it was necessary to process a height of about 200 nm. For example, assuming that the minimum processing dimension is 50 nm, the aspect ratio of this embodiment (ratio of processing width to height) is 2.0, and the aspect ratio of the prior art is 4.0, and the processing of this embodiment is more accurate. it can. Furthermore, when processing a three-layer structure film, an etching step is likely to occur at the boundary of each layer, and in some cases, it is necessary to use a plurality of processing apparatuses, which causes problems in process simplicity and stability. .

  Further, in the present embodiment, since the bit line processed film 8 in which the buried insulating film 7 is buried has a low aspect ratio, the filling is easy. This means that a stable embedded structure can be realized and an inexpensive manufacturing apparatus can be used.

  Furthermore, when removing the bit line processed film 8, in this embodiment, one layer of the silicon nitride film may be removed, but in the prior art, the silicon oxide film must be removed after removing the silicon nitride film. Therefore, the process is complicated. This is because the substrate selection ratio when the silicon nitride film is removed by etching can be increased by the phosphoric acid boil method if the silicon oxide film is used, but the substrate selection ratio is decreased in the polysilicon film.

  Furthermore, since the word line electrode 3 is formed of a single layer polysilicon film, the instability of electrical connection between the lower gate electrode 6 and the word line electrode 3 does not occur as in the prior art.

  Furthermore, when the word line electrode 3 is processed, a single-layer polysilicon film having a height of about 100 to 200 nm may be processed, and a double-layer polysilicon film having a height of about 200 nm as in the prior art is not processed. It's okay. For this reason, since the aspect ratio is small and an etching step due to the boundary portion of the two-layer polysilicon film does not occur, processing with high accuracy becomes possible.

  As described above, according to the method of manufacturing the nonvolatile semiconductor memory device of this embodiment, the P-type well 4, the isolation diffusion layer 2, the charge trap layer 5, and the bit line processed film 8 are sequentially formed on the semiconductor substrate. Then, the bit line processing film 8 is processed using the bit line formation mask, the bit line diffusion layer 1 is formed by ion implantation in a self-alignment manner using these as masks, the buried insulating film 7 is deposited on the entire surface, and the CMP method is used. The bit line processed film 8 is removed and the word line electrode 3 is deposited on the entire surface, and the word line electrode 3 is processed. That is, a bit line processed film, that is, a SiN dummy gate is formed, and the buried insulating film 7 is formed first using the bit line processed film, and then the bit line processed film 8 is removed, and then an independent gate electrode and word line for each memory cell. The electrode 3 is formed of the same film formed simultaneously.

  As a result, the material to be processed when forming the word line can be only a single-layer polysilicon film, so that the height of the material at the time of processing the word line can be reduced, and the buried bit line structure can be made of single-layer polysilicon. Since it can be formed, the manufacturing process is simplified.

  Although the CMP method has been described here as a method of embedding the buried insulating film 7 between the bit line processed films 8, other methods such as an etch back method may be used.

(Second Embodiment)
Hereinafter, a method for manufacturing a nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described with reference to the drawings.

  In FIG. 19 of the prior art, the bit line processing film 8 and the lower gate electrode 6 are processed using a bit line formation mask, and the bit line diffusion layer 1 is formed by ion implantation in a self-alignment manner using these as masks. It is a process. Usually this is followed by an oxidation step. This oxidation step is performed for the purpose of removing etching residues by oxidation and for recovering damage to the charge trap layer due to processing and ion implantation.

  In the present embodiment, an oxidation step is inserted in the step of FIG. 8 corresponding to FIG. 19 of the prior art or the step of FIG. In the prior art, there has been a problem that the lower gate electrode 6 is oxidized by the oxidation in the process of FIG. 19 and the gate length is shortened. In the present embodiment, however, the polysilicon film that becomes the gate electrode in the oxidation process is reduced. Therefore, such a problem does not occur.

  Furthermore, by including an oxidation step in the step of FIG. 10, the region that becomes the gate oxide film of the memory can be directly oxidized, so that improvement in reliability can be expected.

(Third embodiment)
Hereinafter, a method for manufacturing a nonvolatile semiconductor memory device according to the third embodiment of the present invention will be described with reference to the drawings.

  In the present embodiment, an ion implantation process as shown in FIG. 13 is performed in the process of FIG. In the prior art, since the lower gate electrode 6 is grown at the beginning of the manufacturing process, ion implantation for controlling the threshold voltage must be performed before the growth process of the lower gate electrode 6. However, if ion implantation for controlling the threshold voltage is performed in this step, a plurality of heat treatment steps are performed thereafter, so that the distribution in the depth direction of ions (impurities) for controlling the threshold voltage is widened. It becomes weak against the channel effect and causes a problem in miniaturization.

  On the other hand, in the case of the present embodiment, since the manufacturing process of the word line electrode 3 is performed at the final stage, ion implantation for controlling the threshold voltage can be performed in the process of FIG. For this reason, the heat treatment after ion implantation can be reduced, the distribution in the depth direction of ions (impurities) for controlling the threshold voltage can be suppressed, the short channel effect is enhanced, and it is advantageous for miniaturization. is there.

(Fourth embodiment)
A method for manufacturing a nonvolatile semiconductor memory device according to the fourth embodiment of the present invention will be described below with reference to the drawings.

  Since the basic structure is the same as that of the first embodiment, FIGS. 23 (a) and (b) to FIGS. 27 (a) and 27 (b) (A-A cross-sectional view and CC of FIG. 2). The method for manufacturing the buried bit line structure according to the fourth embodiment will be described with reference to FIG.

  First, as shown in FIGS. 23A and 23B, a P-type well 4, an isolation diffusion layer 2, a charge trap layer 5, a bit line processed film 8, and a hard mask film 9 are sequentially formed on a semiconductor substrate. . Here, the bit line processed film 8 is preferably formed of a silicon nitride film of about 50 to 100 nm, and the hard mask film 9 is formed of a silicon oxide film of about 50 to 150 nm.

  Here, the hard mask refers to an inorganic material (including a metal film in some cases), such as a silicon oxide film or a silicon nitride film, when etching other members with respect to a resist mask that is an organic material. This is the name when used as a mask.

  Next, as shown in FIGS. 24A and 24B, in the AA cross-sectional view, the hard mask film 9 and the bit line processed film 8 are sequentially processed with the bit line forming mask, and the processed hard mask is processed. The bit line diffusion layer 1 is formed by ion implantation in a self-aligning manner using the film 9 and the bit line processed film 8 as a mask. Here, it is important to set the hard mask film 9 and the bit line processed film 8 so as to prevent the implanted ions from penetrating into the charge trap layer 5.

  Next, as shown in FIGS. 25A and 25B, a buried insulating film 7 is deposited on the entire surface and flattened by a CMP method or the like. Here, it is desirable to use a silicon oxide film for the buried insulating film 7. In the CMP method, since polishing can be stopped on the bit line processed film 8, the remaining film thickness of the buried insulating film 7 can be controlled with high accuracy by the film thickness of the bit line processed film 8. Since the hard mask film 9 is made of the same material as the buried insulating film 7, it is polished and removed together with the buried insulating film 7 by the CMP method.

  Next, as shown in FIGS. 26A and 26B, the bit line processed film 8 is removed. Here, when the bit line processed film 8 is formed of a silicon nitride film, it can be removed while leaving the charge trap layer 5 by the phosphoric acid boiling method.

  Next, as shown in FIGS. 27A and 27B, the word line electrode 3 is deposited on the entire surface. Here, the word line electrode 3 is formed of a polysilicon film of about 100 to 200 nm.

  As described above, according to the present embodiment, the hard mask film 9 and the bit line processed film 8 secure a film thickness necessary for preventing implanted ions from penetrating into the charge trap layer 5, and buried insulation. Since the height of the film 7 is controlled by the film thickness of the bit line processed film 8, an optimum film thickness can be set for each.

  In particular, if the height of the buried insulating film 7 is increased, it becomes difficult to process the surface of the word line electrode 3 such as unevenness. Therefore, it is desirable to suppress the thickness to about 30 to 70 nm.

  In each of the above-described embodiments, the silicon nitride film is used as the bit line processed film 8 in the above-described embodiment. However, the present invention is not limited to this. What is a silicon nitride film such as a silicon oxide film? Other different insulating films are also applicable. However, when a hard mask is used, if a silicon oxide film is used as the bit line processing film, an insulating film made of a material different from the insulating film used as the bit line processing film is used as the hard mask. It is necessary to use it.

  In each of the above embodiments, a polysilicon film is used as the word line electrode 3, but another conductive film different from the polysilicon film can be applied.

  As described above, the method for manufacturing a nonvolatile semiconductor memory device according to the present invention can cope with the miniaturization of the nonvolatile semiconductor memory device and can realize a simpler process, particularly a non-conductive charge trap layer. This is useful in a method for manufacturing a nonvolatile semiconductor memory device using the above as a memory element.

1 is a circuit diagram showing an electrical connection structure of a memory cell array according to a first embodiment of the present invention and a prior art. FIG. 1 is a plan view of a memory cell array according to a first embodiment of the present invention and a prior art. FIG. 1 is a cross-sectional view of the memory cell array taken along the line AA in the first embodiment of the present invention. FIG. FIG. 3 is a cross-sectional view of the memory cell array taken along the line BB in the first embodiment of the present invention. FIG. 3 is a cross-sectional view of the memory cell array taken along the line CC in the first embodiment of the present invention. It is DD sectional drawing of the memory cell array in the 1st Embodiment of this invention. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step 1 in the 1st Embodiment of this invention. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step 2 in the 1st Embodiment of this invention. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step 3 in the 1st Embodiment of this invention. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step 4 in the 1st Embodiment of this invention. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step 5 in the 1st Embodiment of this invention. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step 6 in the 1st Embodiment of this invention. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step in the 3rd Embodiment of this invention. It is AA sectional drawing of the memory cell array in a prior art. It is BB sectional drawing of the memory cell array in a prior art. It is CC sectional drawing of the memory cell array in a prior art. It is DD sectional drawing of the memory cell array in a prior art. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step 1 in a prior art. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step 2 in a prior art. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step 3 in a prior art. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step 4 in a prior art. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step 5 in a prior art. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step 1 in the 4th Embodiment of this invention. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step 2 in the 4th Embodiment of this invention. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step 3 in the 4th Embodiment of this invention. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step 4 in the 4th Embodiment of this invention. (A), (b) is AA sectional drawing and CC sectional drawing of the manufacturing step 5 in the 4th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Bit line diffusion layer 2 Separation diffusion layer 3 Word line electrode 4 P-type well 5 Charge trap layer 6 Lower gate electrode 7 Embedded insulating film 8 Bit line processed film 9 Hard mask film

Claims (10)

A first step of forming a charge trap layer on a semiconductor substrate;
A second step of forming a bit line processed film on the charge trapping layer;
A third step of selectively etching away the bit line processed film to form an opening for forming a bit line;
A fourth step of introducing a bit line forming impurity into the semiconductor substrate from the opening;
A fifth step of exposing an upper portion of the bit line processed film after embedding an insulating film in the opening;
A sixth step of removing the bit line processed film;
A seventh step of forming a gate electrode formation film on the region from which the bit line processed film has been removed and the insulating film;
And an eighth step of selectively removing the gate electrode formation film by etching to form a word line.   2. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the charge trapping layer includes three layers of a silicon oxide film, a silicon nitride film, and a silicon oxide film.   2. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the charge trap layer is made of a silicon oxide film containing minute silicon grains.   The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the bit line processed film is made of a single layer silicon nitride film.   The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the gate electrode formation film is made of a single-layer polysilicon film.   The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein an oxidation step is provided between the third step and the fifth step.   6. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein an oxidation step is provided between the sixth step and the seventh step.   The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein an impurity is introduced into the semiconductor substrate between the sixth step and the seventh step. . The second step includes a step of further forming a hard mask film on the bit line processed film,
2. The nonvolatile semiconductor memory according to claim 1, wherein in the third step, the hard mask film and the bit line processed film are selectively removed by etching to form an opening for bit line formation. 3. Device manufacturing method.   The method for manufacturing a nonvolatile semiconductor memory device according to claim 9, wherein the hard mask film is made of a silicon oxide film.

Images