CN107785269B - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

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Publication number
CN107785269B
CN107785269B CN201610784554.4A CN201610784554A CN107785269B CN 107785269 B CN107785269 B CN 107785269B CN 201610784554 A CN201610784554 A CN 201610784554A CN 107785269 B CN107785269 B CN 107785269B
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interlayer dielectric
dielectric layer
forming
layer
protective layer
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CN107785269A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a semiconductor device, comprising: providing a substrate with sparse areas and dense areas; forming a pseudo gate structure on a substrate, wherein the pseudo gate structure comprises a pseudo gate electrode on the substrate, the top surface of the pseudo gate electrode is provided with a protective layer, and the protective layer has a first hardness; forming an interlayer dielectric layer on the substrate to cover the side wall of the pseudo gate structure and the side wall of the protective layer, wherein the hardness of the interlayer dielectric layer is less than the first hardness; the forming method of the interlayer dielectric layer comprises the following steps: forming a first interlayer dielectric layer covering the side wall of the pseudo gate structure and the side wall of the protective layer on the substrate; after the first interlayer dielectric layer is formed, ion implantation is carried out on the protective layer, so that the protective layer has a second hardness which is smaller than the first hardness; grinding the interlayer dielectric layer and the protective layer until the top surface of the pseudo gate electrode is exposed; removing the dummy gate electrode, forming a first opening in the sparse region, and forming a second opening in the dense region; a metal gate electrode is formed in the first opening and the second opening. The method improves the high uniformity of the metal gate electrode.

Description

Method for forming semiconductor device
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor device.
Background
MOS transistors are one of the most important components in modern integrated circuits. The basic structure of the MOS transistor includes: a semiconductor substrate; the semiconductor device comprises a grid structure positioned on the surface of a semiconductor substrate, a source region positioned in the semiconductor substrate on one side of the grid structure and a drain region positioned in the semiconductor substrate on the other side of the grid structure. The operating principle of the MOS transistor is as follows: the switching signal is generated by applying a voltage to the gate structure to regulate current through the bottom channel of the gate structure.
With the development of semiconductor technology, the conventional planar MOS transistor has a weak ability to control channel current, resulting in a serious leakage current. Fin field effect transistors (Fin FETs) are emerging multi-gate devices, which generally include a Fin protruding from the surface of a semiconductor substrate, a gate structure covering a portion of the top surface and sidewall surfaces of the Fin, a source region in the Fin on one side of the gate structure, and a drain region in the Fin on the other side of the gate structure.
No matter the semiconductor device is a planar MOS transistor or a fin field effect transistor, the height uniformity of the gate structure is poor.
Disclosure of Invention
The invention provides a method for forming a semiconductor device, which aims to improve the high uniformity of metal gate electrodes in sparse areas and dense areas.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein the substrate comprises a sparse area and a dense area; forming a dummy gate structure on a substrate, wherein the dummy gate structure comprises a dummy gate electrode positioned on the substrate, the top surface of the dummy gate electrode is provided with a protective layer, and the protective layer has a first hardness; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the side wall of the pseudo gate structure and the side wall of the protective layer, the interlayer dielectric layer is exposed out of the top surface of the protective layer, and the hardness of the interlayer dielectric layer is smaller than a first hardness; the forming method of the interlayer dielectric layer comprises the following steps: forming a first interlayer dielectric layer covering the side wall of the pseudo gate structure and the side wall of the protective layer on the substrate; after the first interlayer dielectric layer is formed, carrying out ion implantation on the protective layer to enable the protective layer to have second hardness, wherein the second hardness is smaller than the first hardness; grinding the interlayer dielectric layer and the protective layer until the top surface of the dummy gate electrode is exposed; after the interlayer dielectric layer and the protective layer are ground, removing the pseudo gate electrode, forming a first opening in the sparse area, and forming a second opening in the dense area; a metal gate electrode is formed in the first opening and the second opening.
Optionally, the ion implantation uses Ar ions, Si ions, or N ions.
Optionally, when the ions are Ar ions, the implantation energy of the ion implantation is 8KeV to 100KeV, and the implantation dose is 1.0E13atom/cm2～1.0E17atom/cm2The injection angle is 0-45 degrees.
Optionally, when the ions are Si ions, thenThe implantation energy of the ion implantation is 3 KeV-80 KeV, and the implantation dose is 1.0E13atom/cm2～1.0E17atom/cm2The injection angle is 0-45 degrees.
Optionally, when the ions are N ions, the implantation energy of the ion implantation is 1KeV to 30KeV, and the implantation dose is 1.0E13atom/cm2～1.0E17atom/cm2The injection angle is 0-45 degrees.
Optionally, the interlayer dielectric layer is a first interlayer dielectric layer; performing ion implantation only on the protective layer; the method for grinding the interlayer dielectric layer and the protective layer comprises the following steps: and grinding the first interlayer dielectric layer and the protective layer until the top surface of the dummy gate electrode is exposed.
Optionally, the method further includes: forming a mask layer, wherein the mask layer covers the surface of the first interlayer dielectric layer and exposes the top surface of the protective layer; the ion implantation is carried out by taking the mask layer as a mask; and removing the mask layer after ion implantation.
Optionally, the ion implantation also acts on the first interlayer dielectric layer; the method for forming the semiconductor device further comprises the following steps: removing the first interlayer dielectric layer with partial thickness after ion implantation; removing part of the first interlayer dielectric layer, and then forming a second interlayer dielectric layer on the first interlayer dielectric layer, wherein the second interlayer dielectric layer exposes out of the top surface of the protective layer, and the hardness of the second interlayer dielectric layer is greater than or equal to that of the first interlayer dielectric layer and is less than the first hardness; after the second interlayer dielectric layer is formed, the second interlayer dielectric layer and the first interlayer dielectric layer form an interlayer dielectric layer; the method for grinding the interlayer dielectric layer and the protective layer comprises the following steps: and grinding the second interlayer dielectric layer and the protective layer until the top surface of the dummy gate electrode is exposed.
Optionally, the process of polishing the second interlayer dielectric layer and the protective layer includes a second chemical mechanical polishing process.
Optionally, the second interlayer dielectric layer is made of silicon oxide, silicon oxycarbide, or silicon oxynitride.
Optionally, the method for forming the second interlayer dielectric layer includes: forming a second interlayer dielectric film covering the first interlayer dielectric layer and the protective layer; and removing the second interlayer dielectric film higher than the top surface of the protective layer so as to form a second interlayer dielectric layer.
Optionally, the method for forming the first interlayer dielectric layer includes: forming a first interlayer dielectric film covering the substrate, the dummy gate structure and the protective layer; and removing the first interlayer dielectric film higher than the top surface of the protective layer so as to form a first interlayer dielectric layer.
Optionally, the process for forming the first interlayer dielectric film is a fluid chemical vapor deposition process or a high aspect ratio deposition process; the process for forming the second interlayer dielectric film is a high-density plasma chemical vapor deposition process or a plasma enhanced chemical vapor deposition process.
Optionally, the process of polishing the first interlayer dielectric layer and the protective layer includes a first chemical mechanical polishing process.
Optionally, the protective layer is made of SiN, SiCN, SiOCN, or SiBCN.
Optionally, the first interlayer dielectric layer is made of silicon oxide, silicon oxycarbide, or silicon oxynitride.
Optionally, the dummy gate structure further includes a dummy gate dielectric layer on the substrate, and the dummy gate electrode is located on the dummy gate dielectric layer; the method for forming the semiconductor device further comprises the following steps: removing the pseudo gate dielectric layer after removing the pseudo gate electrode, forming a first opening in the sparse area, and forming a second opening in the dense area; and after removing the pseudo gate dielectric layer, forming a gate dielectric layer and a metal gate electrode positioned on the gate dielectric layer, wherein the gate dielectric layer is positioned on the side wall and the bottom of the first opening and the second opening.
Optionally, the base includes a semiconductor substrate and a fin portion located on the semiconductor substrate; the dummy gate structure crosses over the fin portion.
Optionally, the base is a planar semiconductor substrate.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the forming method of the semiconductor device, due to the fact that the protective layer is subjected to ion implantation, the hardness of the protective layer is reduced, and therefore the hardness difference between the protective layer and the interlayer dielectric layer is reduced. Therefore, in the process of grinding the interlayer dielectric layers and the protective layers, the difference between the blocking effect of the protective layer in the sparse area and the blocking effect of the protective layer in the dense area is reduced, and the difference between the grinding degrees of the interlayer dielectric layers in the sparse area and the interlayer dielectric layers in the dense area is reduced. After the interlayer dielectric layer and the protective layer are ground, the thickness difference of the interlayer dielectric layer respectively reserved in the sparse area and the dense area is small. Therefore, after the dummy gate electrode is removed, the height difference between the formed first opening and the second opening is smaller, and the height difference between the metal gate electrodes formed in the first opening and the second opening is smaller. The high uniformity of the metal gate electrode in the sparse region and the dense region is improved.
Drawings
Fig. 1 to 9 are schematic structural views illustrating a process of forming a semiconductor device according to an embodiment of the present invention;
fig. 10 to 15 are schematic structural views illustrating a process of forming a semiconductor device according to another embodiment of the present invention.
Detailed Description
As described in the background, the semiconductor device formed in the prior art has a metal gate structure with poor uniformity in height.
A method of forming a semiconductor device, comprising: providing a substrate; forming a pseudo gate structure on a substrate, wherein the pseudo gate structure comprises a pseudo gate electrode positioned on the substrate, and the top surface of the pseudo gate electrode is provided with a mask layer; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the side wall of the pseudo gate structure and the side wall of the mask layer, and the interlayer dielectric layer is exposed out of the top surface of the mask layer; grinding the interlayer dielectric layer and the mask layer until the top surface of the dummy gate electrode is exposed; removing the dummy gate electrode to form an opening; and forming a metal gate electrode in the opening.
The substrate includes a dense region and a sparse region. The density of the dummy gate structures in the sparse region is less than that of the dummy gate structures in the dense region.
The mask layer is made of silicon nitride. The interlayer dielectric layer is made of silicon oxide.
However, in the semiconductor device formed by the above method, the high uniformity of the metal gate electrode is poor, and the reason is found by research:
because the mask layer is made of silicon nitride and the interlayer dielectric layer is made of silicon oxide, the hardness of the interlayer dielectric layer is greater than that of the mask layer, and the difference between the hardness of the interlayer dielectric layer and that of the mask layer is large. Because the density of the dummy gate structures in the sparse area is less than that of the dummy gate structures in the dense area, the density of the mask layer in the sparse area is less than that of the mask layer in the dense area. In the process of grinding the interlayer dielectric layer and the mask layer, the mask layer can block grinding. Because the density of the mask layer in the sparse area is less than that of the mask layer in the dense area, the barrier effect of the mask layer in the sparse area is much less than that of the mask layer in the dense area in the process of grinding the interlayer dielectric layer and the mask layer. Correspondingly, the difference of the grinding degree of the interlayer dielectric layers in the sparse area and the dense area is large. After the interlayer dielectric layer and the mask layer are ground, the thickness difference of the interlayer dielectric layer respectively reserved in the sparse area and the dense area is large. Resulting in a large difference in height between the sparse region and the dense region of the formed opening after removing the dummy gate electrode. Thereby resulting in a large difference in the height of the formed metal gate electrode.
On the basis, the invention provides a method for forming a semiconductor device, which comprises the following steps: providing a substrate, wherein the substrate comprises a sparse area and a dense area; forming a dummy gate structure on a substrate, wherein the dummy gate structure comprises a dummy gate electrode positioned on the substrate, the top surface of the dummy gate electrode is provided with a protective layer, and the protective layer has a first hardness; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the side wall of the pseudo gate structure and the side wall of the protective layer, the interlayer dielectric layer is exposed out of the top surface of the protective layer, and the hardness of the interlayer dielectric layer is smaller than a first hardness; the forming method of the interlayer dielectric layer comprises the following steps: forming a first interlayer dielectric layer covering the side wall of the pseudo gate structure and the side wall of the protective layer on the substrate; after the first interlayer dielectric layer is formed, carrying out ion implantation on the protective layer to enable the protective layer to have second hardness, wherein the second hardness is smaller than the first hardness; grinding the interlayer dielectric layer and the protective layer until the top surface of the dummy gate electrode is exposed; after the interlayer dielectric layer and the protective layer are ground, removing the pseudo gate electrode, forming a first opening in the sparse area, and forming a second opening in the dense area; a metal gate electrode is formed in the first opening and the second opening.
Because the protective layer is subjected to ion implantation, the hardness of the protective layer is reduced, and the hardness difference between the protective layer and the interlayer dielectric layer is reduced. Therefore, in the process of grinding the interlayer dielectric layers and the protective layers, the difference between the blocking effect of the protective layer in the sparse area and the blocking effect of the protective layer in the dense area is reduced, and the difference between the grinding degrees of the interlayer dielectric layers in the sparse area and the interlayer dielectric layers in the dense area is reduced. After the interlayer dielectric layer and the protective layer are ground, the thickness difference of the interlayer dielectric layer respectively reserved in the sparse area and the dense area is small. Therefore, after the dummy gate electrode is removed, the height difference between the formed first opening and the second opening is smaller, and the height difference between the metal gate electrodes formed in the first opening and the second opening is smaller. The high uniformity of the metal gate electrode in the sparse region and the dense region is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The semiconductor device may be a fin field effect transistor. The semiconductor device may also be a planar MOS transistor. The semiconductor device is a fin field effect transistor as an example.
Fig. 1 to 9 are schematic structural views illustrating a semiconductor device forming process according to an embodiment of the present invention.
Referring to fig. 1 and 2 in combination, fig. 2 is a schematic view of a structure taken along cutting lines a-a1 and a2-A3 in fig. 1, providing a substrate.
In this embodiment, the base includes a semiconductor substrate 100 and a fin 120 on the semiconductor substrate 100. In other embodiments, when the semiconductor device is a planar MOS transistor, the base is a planar semiconductor substrate.
The semiconductor substrate 100 provides a process platform for forming semiconductor devices.
The material of the semiconductor substrate 100 may be monocrystalline silicon, polycrystalline silicon or amorphous silicon; the material of the semiconductor substrate 100 may be a semiconductor material such as silicon, germanium, silicon germanium, or gallium arsenide; the semiconductor substrate 100 may also be other semiconductor materials, which are not illustrated here. In this embodiment, the material of the semiconductor substrate 100 is monocrystalline silicon.
In this embodiment, the fin 120 is formed by patterning the semiconductor substrate 100. In other embodiments, it may also be: forming a fin material layer (not shown) on the semiconductor substrate; and patterning the fin part material layer to form a fin part.
The substrate comprises a sparse area I and a dense area II.
After the pseudo gate structure is formed subsequently, the density of the pseudo gate structure in the sparse region I is smaller than that of the pseudo gate structure in the dense region II. Correspondingly, the density of the metal gate structures correspondingly formed in the sparse area I is smaller than that of the metal gate structures correspondingly formed in the dense area II.
In this embodiment, the method further includes: isolation structures 110 are formed on the semiconductor substrate 100 on the sides of the fins 120. The top surface of the isolation structures 110 is lower than the top surface of the fins 120. The isolation structure 110 is used to electrically isolate adjacent fins 120.
With continuing reference to fig. 1 and 2, a dummy gate structure 130 is formed on the substrate, the dummy gate structure 130 includes a dummy gate electrode 132 on the substrate, a top surface of the dummy gate electrode 132 has a protection layer 140, and the protection layer 140 has a first hardness.
Specifically, the dummy gate structures 130 are formed on the substrate in both the sparse region i and the dense region ii.
The density of the dummy gate structures 130 in the sparse region i is less than the density of the dummy gate structures 130 in the dense region ii.
In this embodiment, the dummy gate structure 130 spans the fins 120 in the sparse region i and the dense region ii, covers the top surfaces and the sidewalls of some of the fins 120 in the sparse region i, and covers the top surfaces and the sidewalls of some of the fins 120 in the dense region ii.
The dummy gate structure 130 includes: a dummy gate dielectric layer 131 on the substrate and a dummy gate electrode 132 on the dummy gate dielectric layer 131.
In this embodiment, the dummy gate dielectric layer 131 spans the fin portions 120 of the sparse region i and the dense region ii, and the dummy gate dielectric layer 131 is located on the isolation structure surfaces of the sparse region i and the dense region ii, covers a part of the fin portions 120 and the top surface and the sidewalls of the sparse region i, and covers the top surface and the sidewalls of the fin portions 120 of the dense region ii.
The material of the dummy gate electrode 132 is polysilicon.
If the dummy gate electrode 132 is subsequently removed, so that a first opening is formed in the sparse region i and a second opening is formed in the dense region ii, after the first opening and the second opening are formed, the dummy gate dielectric layer 131 constitutes a gate dielectric layer, and therefore, the material of the dummy gate dielectric layer 131 needs to be a high-K dielectric material (K is greater than 3.9).
If the dummy gate structure 130 is subsequently removed, so that a first opening is formed in the sparse region i and a second opening is formed in the dense region ii, after the first opening and the second opening are formed, a gate dielectric layer needs to be formed on the sidewalls and the bottoms of the first opening and the second opening. The material of the dummy gate dielectric layer 131 is silicon oxide.
In this embodiment, the first opening and the second opening formed by removing the dummy gate structure 130 will be described as an example.
In this embodiment, the material of the protection layer 140 is silicon nitride (SiN). In other embodiments, the material of the protective layer may be SiCN, SiOCN, or SiBCN.
The thickness of the protective layer 140 is 150 to 500 angstroms.
In this embodiment, the protection layer 140 and the dummy gate structure 130 are formed in a single process.
Specifically, the steps of forming the dummy gate structure 130 and the protection layer 140 include: forming a pseudo gate dielectric material layer on the substrate; forming a dummy gate electrode material layer on the dummy gate dielectric material layer; forming a protective material layer on the dummy gate electrode material layer; the protective material layer, the dummy gate electrode material layer and the dummy gate dielectric material layer are patterned to form a dummy gate structure 130 and a protective layer 140 on the top surface of the dummy gate structure 130.
Note that the protection layer 140 serves as a mask layer for patterning the dummy gate electrode material layer and the dummy gate dielectric material layer.
The dummy gate dielectric layer 131 corresponds to the dummy gate dielectric material layer; the dummy gate electrode 132 corresponds to a dummy gate electrode material layer; the protection layer 140 corresponds to a protection material layer.
Referring to fig. 3, fig. 3 is a schematic structural diagram formed on the basis of fig. 1, and source and drain doped regions (not labeled) are formed in the fin portions 120 on both sides of the dummy gate structure 130; after the source-drain doped region is formed, a first interlayer dielectric layer 150 covering the side wall of the dummy gate structure 130 and the side wall of the protection layer is formed on the substrate, the first interlayer dielectric layer 150 is exposed out of the top surface of the protection layer 140, and the hardness of the first interlayer dielectric layer 150 is smaller than the first hardness.
The method of forming the first interlayer dielectric layer 150 includes: forming a first interlayer dielectric film (not shown) covering the substrate, the dummy gate structure 130 and the protection layer 140, the entire surface of the first interlayer dielectric film being higher than the top surface of the protection layer 140; the first interlayer dielectric film above the top surface of the protection layer 140 is removed to form a first interlayer dielectric layer 150.
In this embodiment, the first interlayer dielectric layer 150 is made of silicon oxide. In other embodiments, the material of the first interlayer dielectric layer may be silicon oxycarbide or silicon oxynitride.
The process for forming the first interlayer dielectric film is a deposition process, such as a fluid chemical vapor deposition process (FCVD), a high aspect ratio deposition process, a low pressure chemical vapor deposition process, a sub-atmospheric pressure chemical vapor deposition process, a high density plasma chemical vapor deposition process, or a plasma enhanced chemical vapor deposition process.
In this embodiment, the process of forming the first interlayer dielectric film is a fluid chemical vapor deposition process, so that the filling performance of the region between the adjacent dummy gate structures 130 is better.
Next, ion implantation is performed on the protection layer 140, so that the protection layer 140 has a second hardness, which is less than the first hardness.
In this embodiment, only the protection layer 140 is ion-implanted. Referring to fig. 4, a mask layer 160 is formed, wherein the mask layer 160 covers the surface of the first interlayer dielectric layer 150 and exposes the top surface of the protection layer 140; referring to fig. 5, ion implantation is performed on the protection layer 140 by using the mask layer 160 as a mask; referring to fig. 6, after ion implantation, the mask layer 160 (refer to fig. 5) is removed.
The physical bombardment of the protective layer 140 by ion implantation causes the chemical bonds of the protective layer 140 to break, so that the internal structure of the protective layer 140 becomes loose, thereby causing the hardness of the protective layer 140 to decrease. Specifically, after the ion implantation is performed on the protection layer 140, the protection layer 140 has a second hardness, which is smaller than the first hardness.
The material of the mask layer 160 may be photoresist.
The ion implantation uses ions with relatively large atomic mass to bombard the protective layer 140, so that the chemical bonds in the protective layer 140 are broken.
In this embodiment, the ions used for the ion implantation are Ar ions, Si ions, or N ions.
The implantation energy of the ion implantation needs to be selected in a suitable range. If the implantation energy of the ion implantation is too large and the implantation depth is deep, the ion implantation may be performed into the dummy gate structure 130 to physically bombard the dummy gate structure 130. If the implantation energy of the ion implantation is too small, the implanted ions are distributed on the surface of the protection layer 140, and only the material on the surface of the protection layer 140 is bombarded to change the hardness.
The implantation dose of the ion implantation needs to be selected in a proper range. If the implantation dosage of the ion implantation is too large, the process is wasted. If the implantation dose of the ion implantation is too small, the bombardment effect on the unit volume of the protection layer 140 is reduced, and the change amount of the hardness of the protection layer 140 is small.
The implantation angle of the ion implantation affects the depth of the ion implantation. The implantation angle refers to an angle with respect to a normal direction of the semiconductor substrate 100. Under the condition that the range of the implantation depth is certain, the larger the implantation angle is, the larger the required implantation energy is; conversely, as the implantation angle is smaller, the implantation energy required is smaller.
In summary, the parameters of the ion implantation process need to be selected in appropriate ranges. And the atomic masses corresponding to different ions are different. For the same implantation depth, ions having a large atomic mass need to lose a large amount of energy, and thus a large implantation energy is required.
When the ions are Ar ions, the implantation energy of the ion implantation is 8 KeV-100 KeV, and the implantation dose is 1.0E13atom/cm2～1.0E17atom/cm2The injection angle is 0-45 degrees.
When the ions are Si ions, the implantation energy of the ion implantation is 3 KeV-80 KeV, and the implantation dosage is 1.0E13atom/cm2～1.0E17atom/cm2The injection angle is 0-45 degrees.
When the ions are N ions, the implantation energy of the ion implantation is 1 KeV-30 KeV, and the implantation dosage is 1.0E13atom/cm2～1.0E17atom/cm2The injection angle is 0-45 degrees.
After the ion implantation, the hardness of the protection layer 140 is reduced, so that the hardness difference between the protection layer 140 and the first interlayer dielectric layer 150 can be reduced.
In this embodiment, the first interlayer dielectric layer 150 constitutes an interlayer dielectric layer.
Next, referring to fig. 7, the first interlayer dielectric layer 150 and the protection layer 140 are polished until the top surface of the dummy gate electrode 132 is exposed.
The process of polishing the first interlayer dielectric layer 150 and the protection layer 140 includes a first chemical mechanical polishing process.
Specifically, after the first interlayer dielectric layer 150 and the protection layer 140 are polished, the top surface of the dummy gate electrode 132 in the sparse region i and the top surface of the dummy gate electrode 132 in the dense region ii are exposed.
Since the hardness difference between the protective layer 140 and the first interlayer dielectric layer 150 is reduced, the difference between the blocking effect of the protective layer 140 in the sparse region i and the blocking effect of the protective layer 140 in the dense region ii is reduced in the process of polishing the first interlayer dielectric layer 150 and the protective layer 140. Thus, the difference in the degree of grinding the first interlayer dielectric layer 150 in the sparse area i and the dense area ii is reduced, and thus, after the first interlayer dielectric layer 150 and the protective layer 140 are ground, the difference in the thickness of the first interlayer dielectric layer 150 respectively retained in the sparse area i and the dense area ii is small.
Referring to fig. 8, the dummy gate structure 130 (see fig. 7) is removed, and a first opening 171 is formed in the sparse region i and a second opening 172 is formed in the dense region ii.
The process of removing the dummy gate structure 130 is a wet etching process, a dry etching process, or a combination of the dry etching process and the wet etching process.
Since the thickness difference of the first interlayer dielectric layer 150 respectively reserved in the sparse region i and the dense region ii is small, the height difference of the first opening 171 and the second opening 172 formed after the dummy gate structure 130 is removed is small.
Referring to fig. 9, a metal gate structure 180 is formed in the first opening 171 (refer to fig. 8) and the second opening 172 (refer to fig. 8).
The metal gate structure 180 includes: a gate dielectric layer 181 positioned on the sidewalls and bottom of the first and second openings 171 and 172, and a metal gate electrode 182 positioned on the gate dielectric layer 181.
Since the difference in height between the first opening 171 and the second opening 172 is small, the difference in height between the metal gate electrode 182 in the sparse region i and the dense region ii is small.
In other embodiments, it may be: removing the dummy gate electrode to form a first opening in the sparse region and a second opening in the dense region; after the first opening and the second opening are formed, the pseudo gate dielectric layer forms a gate dielectric layer; and then forming a metal gate electrode positioned on the gate dielectric layer in the first opening and the second opening.
Fig. 10 to 15 are schematic structural views illustrating a process of forming a semiconductor device according to another embodiment of the present invention.
The present embodiment differs from the previous embodiment in that: and simultaneously carrying out ion implantation on the protective layer and the first interlayer dielectric layer, wherein a mask layer is not needed in the process of carrying out ion implantation. After ion implantation is carried out on the protective layer and the first interlayer dielectric layer, the first interlayer dielectric layer with partial thickness is removed; removing part of the first interlayer dielectric layer, and then forming a second interlayer dielectric layer on the first interlayer dielectric layer, wherein the second interlayer dielectric layer exposes out of the top surface of the protective layer, and the hardness of the second interlayer dielectric layer is greater than or equal to that of the first interlayer dielectric layer and is less than the first hardness; and grinding the second interlayer dielectric layer and the protective layer until the top surface of the dummy gate electrode is exposed. The dummy gate structure is then removed.
Referring to fig. 10, fig. 10 is a schematic structural diagram formed on the basis of fig. 3, and the protective layer 140 and the first interlayer dielectric layer 150 are subjected to ion implantation.
In this embodiment, the parameters for performing the ion implantation on the protection layer 140 and the first interlayer dielectric layer 150 refer to the previous embodiment, and are not described in detail.
In this embodiment, since the protection layer 140 and the first interlayer dielectric layer 150 are both subjected to ion implantation, a mask layer covering the surface of the first interlayer dielectric layer 150 and exposing the top surface of the protection layer 140 is not required to be formed, thereby reducing the difficulty and cost of the process.
Since the first interlayer dielectric layer 150 is also ion-implanted, the ion implantation also reduces the hardness of the first interlayer dielectric layer 150.
It should be noted that in this embodiment, the hardness of the first interlayer dielectric layer 150 is reduced by ion implantation, so that the hardness difference between the protection layer 140 and the first interlayer dielectric layer 150 is reduced after ion implantation, or the hardness difference between the protection layer 140 and the first interlayer dielectric layer 150 is increased after ion implantation, or the hardness difference between the protection layer 140 and the first interlayer dielectric layer 150 is not changed after ion implantation. Therefore, the first interlayer dielectric layer with partial thickness needs to be removed subsequently, and a second interlayer dielectric layer is formed on the first interlayer dielectric layer.
Referring to fig. 11, after ion implantation is performed on the protective layer 140 and the first interlayer dielectric layer 150, a portion of the thickness of the first interlayer dielectric layer 150 is removed.
The process of removing a portion of the thickness of the first interlayer dielectric layer 150 is a dry etching process or a wet etching process.
In this embodiment, a portion of the thickness of the first interlayer dielectric layer 150 is removed, such that at least a portion of the first interlayer dielectric layer 150 doped with ions is removed. In other embodiments, the first interlayer dielectric layer may be entirely removed.
In this embodiment, the process cost and the process time required for removing the first interlayer dielectric layer 150 with a partial thickness are relatively low. And only part of the first interlayer dielectric layer 150 is removed, so that the thickness of the subsequently formed second interlayer dielectric layer is smaller, and the process cost and the process time corresponding to the subsequently formed second interlayer dielectric layer are lower.
Referring to fig. 12, after removing a portion of the thickness of the first interlayer dielectric layer 150, a second interlayer dielectric layer 280 is formed on the first interlayer dielectric layer 150, the second interlayer dielectric layer 280 exposes the top surface of the protection layer 140, and the hardness of the second interlayer dielectric layer 280 is greater than or equal to the hardness of the first interlayer dielectric layer 150 and is less than the first hardness.
After the second interlayer dielectric layer 280 is formed, the second interlayer dielectric layer 280 and the first interlayer dielectric layer 150 form an interlayer dielectric layer.
The second interlayer dielectric layer 280 is made of silicon oxide, silicon oxycarbide or silicon oxynitride.
The method of forming the second interlayer dielectric layer 280 includes: forming a second interlayer dielectric film (not shown) covering the first interlayer dielectric layer 150 and the protection layer 140, the second interlayer dielectric film having an entire surface higher than the top surface of the protection layer 140; the second interlayer dielectric film above the top surface of the protection layer 140 is removed to form a second interlayer dielectric layer 280.
If the hardness of the second interlayer dielectric layer 280 is greater than the hardness of the first interlayer dielectric layer 150 and less than the first hardness, the process for forming the first interlayer dielectric film is a fluid chemical vapor deposition process or a high aspect ratio deposition process; the process for forming the second interlayer dielectric film is a high-density plasma chemical vapor deposition process or a plasma enhanced chemical vapor deposition process.
Since the hardness of the second interlayer dielectric layer 280 is greater than or equal to the hardness of the first interlayer dielectric layer 150 and less than the first hardness, and the hardness of the protection layer 140 is reduced after the ion implantation, the hardness difference between the protection layer 140 and the second interlayer dielectric layer 280 can be reduced.
In this embodiment, the hardness of the second interlayer dielectric layer 280 is equal to the hardness of the protection layer 140 after ion implantation. I.e., the hardness of the second interlayer dielectric layer 280 is equal to the second hardness.
Referring to fig. 13, the second interlayer dielectric layer 280 and the protection layer 140 are polished until the top surface of the dummy gate electrode 132 is exposed.
The process of polishing the second interlayer dielectric layer 280 and the protection layer 140 includes a second chemical mechanical polishing process.
Specifically, after the second interlayer dielectric layer 280 and the protection layer 140 are polished, the top surface of the dummy gate electrode 132 in the sparse region i and the top surface of the dummy gate electrode 132 in the dense region ii are exposed.
Because the hardness difference between the protective layer 140 and the second interlayer dielectric layer 280 is reduced, the difference between the blocking effect of the protective layer 140 in the sparse area I and the blocking effect of the protective layer 140 in the dense area II is reduced in the process of grinding the second interlayer dielectric layer 280 and the protective layer 140. Thus, the difference in the degree of grinding the second interlayer dielectric layers 280 in the sparse zone i and the dense zone ii is reduced, and thus, after the second interlayer dielectric layers 280 and the protective layer 140 are ground, the difference in the thickness of the second interlayer dielectric layers 280 respectively retained in the sparse zone i and the dense zone ii is small.
Referring to fig. 14, after the second interlayer dielectric layer 280 and the protection layer 140 are polished, the dummy gate structure 130 (refer to fig. 13) is removed, and the first opening 271 is formed in the sparse region i and the second opening 272 is formed in the dense region ii.
The method for removing the dummy gate structure 130 is described in the previous embodiment and will not be described in detail.
Since the thickness difference of the second interlayer dielectric layer 280 respectively reserved in the sparse region i and the dense region ii is small, the height difference of the first opening 271 and the second opening 272 formed after the dummy gate structure 130 is removed is small.
Referring to fig. 15, a metal gate structure 290 is formed in the first opening 271 (refer to fig. 14) and the second opening 272 (refer to fig. 14).
The metal gate structure 290 includes: a gate dielectric layer 291 on sidewalls and bottom of the first and second openings 271 and 272, and a metal gate electrode 292 on the gate dielectric layer 291.
Since the difference in height between the first opening 271 and the second opening 272 is small, the difference in height between the metal gate electrode 292 in the sparse region i and the dense region ii is small.
It should be noted that, in other embodiments, the following may be used: removing the dummy gate electrode to form a first opening in the sparse region I and a second opening in the dense region II; after the first opening and the second opening are formed, the pseudo gate dielectric layer forms a gate dielectric layer; then, a metal gate electrode filling the first opening and the second opening is formed.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a sparse area and a dense area;
forming a dummy gate structure on a substrate, wherein the dummy gate structure comprises a dummy gate electrode positioned on the substrate, the top surface of the dummy gate electrode is provided with a protective layer, and the protective layer has a first hardness;
forming an interlayer dielectric layer on a substrate to cover the side wall of the pseudo gate structure and the side wall of the protective layer, wherein the interlayer dielectric layer is exposed out of the top surface of the protective layer, the hardness of the interlayer dielectric layer is less than a first hardness, and the forming method of the interlayer dielectric layer comprises the following steps: forming a first interlayer dielectric layer covering the side wall of the pseudo gate structure and the side wall of the protective layer on the substrate; after the first interlayer dielectric layer is formed, carrying out ion implantation on the protective layer to enable the protective layer to have second hardness, wherein the second hardness is smaller than the first hardness;
grinding the interlayer dielectric layer and the protective layer until the top surface of the pseudo gate electrode is exposed;
after the interlayer dielectric layer and the protective layer are ground, removing the pseudo gate electrode, forming a first opening in the sparse area, and forming a second opening in the dense area;
a metal gate electrode is formed in the first opening and the second opening.
2. The method according to claim 1, wherein the ion implantation uses Ar ions, Si ions, or N ions.
3. The method according to claim 2, wherein when the ions are Ar ions, the ion implantation energy is 8KeV to 100KeV, and the implantation dose is 1.0E13atom/cm2～1.0E17atom/cm2The injection angle is 0-45 degrees.
4. The method of claim 2, wherein when the ions are Si ions, the ion implantation energy is 3KeV to 80KeV, and the implantation dose is 1.0E13atom/cm2～1.0E17atom/cm2The injection angle is 0-45 degrees.
5. The method of claim 2, wherein when the ions are N ions, the ion implantation energy is 1KeV to 30KeV, and the implantation dose is 1.0E13atom/cm2～1.0E17atom/cm2The injection angle is 0-45 degrees.
6. The method for forming a semiconductor device according to claim 1, wherein the interlayer dielectric layer is a first interlayer dielectric layer; performing ion implantation only on the protective layer;
the method for grinding the interlayer dielectric layer and the protective layer comprises the following steps: and grinding the first interlayer dielectric layer and the protective layer until the top surface of the dummy gate electrode is exposed.
7. The method for forming a semiconductor device according to claim 6, further comprising: forming a mask layer, wherein the mask layer covers the surface of the first interlayer dielectric layer and exposes the top surface of the protective layer; the ion implantation is carried out by taking the mask layer as a mask; and removing the mask layer after ion implantation.
8. The method of claim 1, wherein the ion implantation also acts on the first interlayer dielectric layer;
the method for forming the semiconductor device further comprises the following steps:
removing the first interlayer dielectric layer with partial thickness after ion implantation;
removing part of the first interlayer dielectric layer, and then forming a second interlayer dielectric layer on the first interlayer dielectric layer, wherein the second interlayer dielectric layer exposes out of the top surface of the protective layer, and the hardness of the second interlayer dielectric layer is greater than or equal to that of the first interlayer dielectric layer and is less than the first hardness;
after the second interlayer dielectric layer is formed, the second interlayer dielectric layer and the first interlayer dielectric layer form an interlayer dielectric layer;
the method for grinding the interlayer dielectric layer and the protective layer comprises the following steps: and grinding the second interlayer dielectric layer and the protective layer until the top surface of the dummy gate electrode is exposed.
9. The method of claim 8, wherein the process of polishing the second interlevel dielectric layer and the protective layer comprises a second chemical mechanical polishing process.
10. The method of claim 8, wherein the second interlayer dielectric layer is made of silicon oxide, silicon oxycarbide, or silicon oxynitride.
11. The method of claim 8, wherein the step of forming the second interlevel dielectric layer comprises: forming a second interlayer dielectric film covering the first interlayer dielectric layer and the protective layer; and removing the second interlayer dielectric film higher than the top surface of the protective layer so as to form a second interlayer dielectric layer.
12. The method of claim 11, wherein the step of forming the first interlayer dielectric layer comprises: forming a first interlayer dielectric film covering the substrate, the dummy gate structure and the protective layer; and removing the first interlayer dielectric film higher than the top surface of the protective layer so as to form a first interlayer dielectric layer.
13. The method as claimed in claim 12, wherein the process of forming the first interlayer dielectric film is a fluid chemical vapor deposition process or a high aspect ratio deposition process; the process for forming the second interlayer dielectric film is a high-density plasma chemical vapor deposition process or a plasma enhanced chemical vapor deposition process.
14. The method of claim 1, wherein the step of polishing the first interlayer dielectric layer and the protective layer comprises a first chemical mechanical polishing process.
15. The method according to claim 1, wherein a material of the protective layer is SiN, SiCN, SiOCN, or SiBCN.
16. The method of claim 1, wherein the first interlayer dielectric layer is made of silicon oxide, silicon oxycarbide, or silicon oxynitride.
17. The method of claim 1, wherein the dummy gate structure further comprises a dummy gate dielectric layer on the substrate, the dummy gate electrode being on the dummy gate dielectric layer; the method for forming the semiconductor device further comprises the following steps:
removing the pseudo gate dielectric layer after removing the pseudo gate electrode, forming a first opening in the sparse area, and forming a second opening in the dense area;
and after removing the pseudo gate dielectric layer, forming a gate dielectric layer and a metal gate electrode positioned on the gate dielectric layer, wherein the gate dielectric layer is positioned on the side wall and the bottom of the first opening and the second opening.
18. The method for forming the semiconductor device according to claim 1, wherein the base comprises a semiconductor substrate and a fin portion located on the semiconductor substrate; the dummy gate structure crosses over the fin portion.
19. The method according to claim 1, wherein the base is a planar semiconductor substrate.
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CN103000671A (en) * 2011-09-16 2013-03-27 中国科学院微电子研究所 MOSFET (metal oxide semiconductor field effect transistor) and manufacturing method thereof
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103000671A (en) * 2011-09-16 2013-03-27 中国科学院微电子研究所 MOSFET (metal oxide semiconductor field effect transistor) and manufacturing method thereof
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