CN113113308B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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CN113113308B
CN113113308B CN202010032455.7A CN202010032455A CN113113308B CN 113113308 B CN113113308 B CN 113113308B CN 202010032455 A CN202010032455 A CN 202010032455A CN 113113308 B CN113113308 B CN 113113308B
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layer
forming
side wall
source
groove
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CN113113308A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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Abstract

The invention provides a semiconductor device and a forming method thereof, wherein the forming method comprises the following steps: providing a substrate, wherein a first source doping layer is formed on the substrate; forming a channel column on the first source doping layer; forming a sacrificial side wall on the side wall of the channel column; etching and removing the first source doping layer on two sides of the sacrificial side wall and the substrate with partial thickness by taking the sacrificial side wall as a mask, and forming a first groove and a second groove in the substrate; and forming a second source doping layer on the bottom and the side wall of the first groove. When the forming method of the invention forms the grid structure subsequently, the parasitic capacitance between the grid structure and the second source doping layer is reduced, and the performance reliability and quality of the semiconductor device are improved.

Description

Semiconductor device and method of forming the same
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
A Fin field effect transistor (Fin FET) is an emerging multi-gate device, which generally includes a Fin portion protruding from a surface of a semiconductor substrate, a gate structure covering a portion of a top surface and a sidewall of the Fin portion, and source-drain doped regions in the Fin portion located at both sides of the gate structure. Compared with a planar metal-oxide semiconductor field effect transistor, the fin type field effect transistor has stronger short channel inhibition capability and stronger working current.
With the further development of semiconductor technology, the size of integrated circuit devices is smaller and smaller, and the conventional fin field effect transistor has a limitation in further increasing the operating current. Specifically, only the region near the top surface and the sidewall in the fin is used as a channel region, so that the volume of the fin used as the channel region is small, which limits the increase of the operating current of the finfet. Therefore, a gate-all-around (GAA) structure fin field effect transistor is proposed, so that the volume of the fin field effect transistor used as a channel region is increased, and the working current of the gate-all-around structure fin field effect transistor is further increased.
However, the performance of the prior art finfet with a trench gate wrap-around structure is still to be improved.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which can improve the performance of the semiconductor device.
In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein a first source doping layer is formed on the substrate; forming a channel column on the first source doping layer; forming a sacrificial side wall on the side wall of the channel column; etching and removing the first source doping layer on two sides of the sacrificial side wall and the substrate with partial thickness by taking the sacrificial side wall as a mask, and forming a first groove and a second groove in the substrate; and forming a second source doping layer on the bottom and the side wall of the first groove.
Optionally, the top surface of the second source doped layer is lower than the top surface of the first source doped layer.
Optionally, the doping concentration of the second source doping layer is greater than the doping concentration of the first source doping layer.
Optionally, the doping concentration range of the second source doping layer is 1.0E21atm/cm 3 ～1.2E22atm/cm 3 。
Optionally, the process of forming the second source doping layer includes an epitaxial growth process.
Optionally, the process parameters of the epitaxial growth process include: the method comprises the following steps: h 2 、HCl、SiH 2 Cl 2 、B 2 H 6 Or by using a gas mixture comprising H 2 、HCl、SiH 2 Cl 2 、PH 3 The mixed gas of (1).
Optionally, when the method includes: h 2 、HCl、SiH 2 Cl 2 、B 2 H 6 In the mixed gas of (1), wherein, the H 2 The gas flow rate of (A) is 100-2000 sccm, the gas flow rate of HCl is 10-800 sccm, and the SiH 2 Cl 2 The gas flow rate of (A) is 50-1000 sccm, B 2 H 6 The gas flow rate of (2) is 10-400 sccm; the technological parameters of the epitaxial growth process further comprise: the pressure is 20-400 torr, and the temperature is 600-800 ℃.
Optionally, when the method includes: h 2 、HCl、SiH 2 Cl 2 、PH 3 In the mixed gas of (1), wherein, the H 2 The gas flow rate of (A) is 100-2000 sccm, the gas flow rate of HCl is 10-800 sccm, and the SiH 2 Cl 2 The gas flow rate is 50-1000 sccm and the PH 3 The gas flow rate of (2) is 100-2500 sccm; the technological parameters of the epitaxial growth process further comprise: the pressure is 20-400 torr, and the temperature is 600-800 ℃.
Optionally, before forming the second source doping layer, the method further includes: forming a protective layer on the bottom and the side wall of the first groove and the second groove, wherein the protective layer extends to the side wall of the sacrifice side wall and the top surface of the channel column; and etching to remove the protective layer on the bottom and the side wall of the first groove and the protective layer on the side wall of the sacrificial side wall close to the first groove.
Optionally, after the second source doping layer is formed, the bottom and the side wall of the second groove, the protective layer on the side wall of the sacrificial side wall close to the second groove and the top of the channel column are etched and removed.
Optionally, a process of forming the first groove and the second groove is a dry etching process or a wet etching process.
Optionally, after forming the second source doping layer, the method further includes: and removing the sacrificial side wall.
Correspondingly, the technical scheme of the invention also provides a semiconductor device formed by the method, which comprises the following steps: a substrate; a first source doping layer located on the substrate; the channel column is positioned on the first source doping layer; the sacrificial side wall is positioned on the side wall of the channel column; a first groove in the substrate on one side of the channel pillar; a second groove located in the substrate on the other side of the channel column; and the second source doping layer is positioned at the bottom and on the side wall of the first groove.
Optionally, the top surface of the second source doped layer is lower than the top surface of the first source doped layer.
Optionally, the doping concentration of the second source doping layer is greater than the doping concentration of the first source doping layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
after a first source doping layer is formed on a substrate, a channel column is formed on the first source doping layer, a sacrificial side wall is formed on the side wall of the channel column, the first source doping layer on two sides of the sacrificial side wall and the substrate with partial thickness are removed through etching by taking the sacrificial side wall as a mask, a first groove and a second groove are formed in the substrate, and a second source doping layer is formed on the bottom and the side wall of the first groove. The first source doping layer and the substrate with partial thickness on two sides of the trench column are etched after the first source doping layer is formed, the first groove and the second groove are formed in the substrate, the second source doping layer is formed in the first groove, and the second source doping layer is not formed in the second groove.
Furthermore, the top surface of the second source doping layer is lower than the top surface of the first source doping layer, so that the distance between the channel and the second source doping layer is increased on one hand, and the distance between the gate structure and the second source doping layer is increased on the other hand, thereby reducing the parasitic capacitance between the gate structure and the second source doping layer and improving the alternating current characteristic of the semiconductor device.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment;
fig. 2 to 14 are schematic cross-sectional views illustrating a process of forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
The performance of the currently formed channel gate surrounding structure finfet is yet to be improved. The analysis will now be described with reference to specific examples.
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment.
Referring to fig. 1, the semiconductor device includes a substrate 100, a source doped layer 101 on the substrate 100; a channel pillar 104 on the source doping layer 101; an isolation layer 102 on the source doped layer 101, wherein the isolation layer 102 is located on a partial sidewall of the channel pillar 104; a gate structure located on a sidewall of the trench pillar 104, the gate structure surrounding the trench pillar 104, the gate structure including a gate dielectric layer 105 located on a sidewall surface of the trench pillar 104, a work function layer 106 located on the gate dielectric layer 105, and a gate layer 107 located on the work function layer 106, wherein a portion of the work function layer 106 and a portion of the gate layer 107 extend to a surface of the isolation layer 102; a dielectric layer 103 located on the isolation layer 102, wherein the gate structure is located in the dielectric layer 103; the source conductive structures are positioned on the surface of the source doping layer 101, in the isolation layer 102 and in the dielectric layer 103, and comprise a source contact layer 109 positioned in the source doping layer 101 and a source plug 108 positioned on the source contact layer 109; the drain conductive structure is positioned at the top of the channel column 104 and in the dielectric layer 103, and comprises a drain contact layer 110 and a drain plug 111 positioned on the drain contact layer 110; and a gate conductive plug 112 positioned on the gate layer 107 and in the dielectric layer 103.
The inventor finds that: the distance between the gate structure and the source doping layer 101 formed by the forming method is too small, the parasitic capacitance between the gate structure and the source doping layer 101 is too large, and the interference effect of the parasitic capacitance on the device is larger when the semiconductor device is used, so that the alternating current characteristic of the semiconductor device is poor, and the stability of the use performance of the semiconductor device is influenced.
The inventor researches and discovers that: forming a first source doping layer on a substrate, forming a channel column on the first source doping layer, forming a sacrificial side wall on the side wall of the channel column, etching the first source doping layer on two sides of the channel column and the substrate with partial thickness by using the sacrificial side wall as a mask, forming a first groove and a second groove in the substrate, forming a second source doping layer on the bottom and the side wall of the first groove, and when forming a gate structure subsequently, on one hand, increasing the distance between the gate structure and the second source doping layer and simultaneously increasing the distance between the channel and the source doping layer, on the other hand, not forming the source doping layer at the bottom of the gate structure, so that the parasitic capacitance between the gate structure and the source doping layer is reduced, and thus, in the using process of a semiconductor device, the interference effect of the parasitic capacitance on the semiconductor device is smaller, and the semiconductor device is better in use performance, the better the stability.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 14 are schematic cross-sectional views illustrating a process of forming a semiconductor device according to an embodiment of the present invention.
Referring to fig. 2, a substrate 200 is provided, and a first source doped layer 210 is formed on the substrate 200.
In this embodiment, the substrate 200 is made of monocrystalline silicon; in other embodiments, the substrate 200 may also be polysilicon or amorphous silicon; in other embodiments, the substrate may also be made of a semiconductor material such as germanium, silicon germanium, gallium arsenide, or the like.
In this embodiment, the method for forming the first source doping layer 210 includes an epitaxial growth method.
In this embodiment, when forming the NMOS, the first source doping layer is formed by an epitaxial growth methodThe technological parameters comprise: the gases used included: h 2 、HCl、SiH 2 Cl 2 、PH 3 In the mixed gas of (1), wherein, the H 2 The gas flow rate of (A) is 100-2000 sccm, the gas flow rate of HCl is 10-800 sccm, and the SiH 2 Cl 2 The gas flow rate is 50-1000 sccm and the PH 3 The gas flow rate of (2) is 100-1500 sccm; the technological parameters of the epitaxial growth process further comprise: the pressure is 20-400 torr, and the temperature is 600-800 ℃.
In this embodiment, when forming the PMOS, the process parameters for forming the first source doping layer by using the epitaxial growth method include: the gases used included: h 2 、HCl、SiH 2 Cl 2 、B 2 H 6 In the mixed gas of (1), wherein, the H 2 The gas flow rate of (A) is 100-2000 sccm, the gas flow rate of HCl is 10-800 sccm, and the SiH 2 Cl 2 The gas flow rate of B is 50-1000 sccm 2 H 6 The gas flow rate of (2) is 10-300 sccm; the technological parameters of the epitaxial growth process further comprise: the pressure is 20-400 torr, and the temperature is 600-800 ℃.
In this embodiment, the doping concentration of the first source doping layer 210 is 2.0E 20-8.0E 21atm/cm 3 。
Referring to fig. 3, a channel material layer 211 is formed on the first source doping layer 210.
In this embodiment, the channel material layer 211 is made of silicon.
In other embodiments, the material of the channel material layer 211 may also be a semiconductor material such as germanium, silicon germanium, gallium arsenide, or the like.
In this embodiment, the process of forming the channel material layer 211 includes a physical vapor deposition process. In other embodiments, the process of forming the channel material layer 211 includes an epitaxial growth process or an atomic layer deposition process.
In this embodiment, a hard mask layer 212 is further formed on the channel material layer 211; in other embodiments, the hard mask layer 212 may not be formed on the channel material layer 211.
In this embodiment, the hard mask layer 212 is formed to protect the top of the subsequently formed trench pillar on the one hand and to improve the accuracy of pattern transfer on the other hand.
Referring to fig. 4, a channel pillar 220 is formed on the first source doping layer 210.
In this embodiment, a mask layer (shown in the figure) is formed on the channel material layer 211, and the mask layer exposes a portion of the surface of the channel material layer 211; and etching the channel material layer 211 by using the mask layer as a mask until the surface of the first source doping layer 210 is exposed, and forming the channel pillar 220 on the first source doping layer 210.
In this embodiment, the process of etching the channel material layer 211 includes a dry etching process.
In this embodiment, the specific parameters of the dry etching process include: the adopted etching gas comprises HBr and Ar, wherein the flow rate of HBr is 10 sccm-1000 sccm, and the flow rate of Ar is 10 sccm-1000 sccm.
In this embodiment, the material of the mask layer includes a photoresist; in other embodiments, the material of the mask layer comprises a hard mask material comprising silicon oxide or silicon nitride.
In this embodiment, the process of forming the mask layer includes a spin coating process.
After the channel pillar 220 is formed, the mask layer is removed.
In this embodiment, the process of removing the mask layer includes an ashing process.
Referring to fig. 5, sacrificial spacers 221 are formed on sidewalls of the channel pillars 220.
In this embodiment, the sacrificial sidewall 221 is made of silicon carbide; in other embodiments, the material of the sacrificial layer 221 is silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, or the like.
In this embodiment, the sacrificial spacer 221 is formed to protect the surface of the channel pillar 220, so as to prevent the sidewall of the channel pillar 220 from being damaged in the subsequent etching process, which may affect the quality of the formed channel pillar 220.
In this embodiment, a chemical vapor deposition process is used to form the sacrificial spacer 221 material layer on the first source doping layer 210 and the channel pillar 220, and the sacrificial spacer 221 material layer is etched back to form the sacrificial spacer 221 on the sidewall of the channel pillar 220.
In this embodiment, the process parameters of the chemical vapor deposition process include that the adopted gas includes hydrogen, HCl gas, SiH 2 Cl 2 And pH 3 The flow rate of the hydrogen gas is 2000sccm to 20000sccm, the flow rate of the HCl gas is 30sccm to 150sccm, and the SiH gas 2 Cl 2 The flow rate of (2) is 50sccm to 1000sccm, and the pH value is 3 The flow rate of the gas is 10-2000 sccm, the pressure of the chamber is 10-600 torr, and the temperature is 650-850 ℃.
In this embodiment, the sacrificial spacer 221 material layer is dry etched, and the specific dry etching process parameters include that the adopted gas includes CF 4 Gas, CH 3 F gas and O 2 ，CF 4 The flow rate of the gas is 5 sccm-100 sccm, CH 3 The flow rate of the F gas is 8sccm to 50sccm, and O 2 The flow rate of the gas is 10-100 sccm, the pressure of the chamber is 10-2000 mtorr, the radio frequency power is 50-300W, the bias voltage is 30-100V, and the time is 4-50 seconds.
Referring to fig. 6, with the sacrificial sidewall 221 as a mask, the first source doping layer 210 and the substrate 200 with a partial thickness on both sides of the sacrificial sidewall 221 are etched and removed, and a first groove 201 and a second groove 202 are formed in the substrate.
In this embodiment, the process of forming the first groove 201 and the second groove 202 is a dry etching process; in other embodiments, the first groove 201 and the second groove 202 may also be formed by a wet etching process.
In this embodiment, the etching gas used in the dry etching process includes: CF (compact flash) 4 、O 2 、CH 3 F and He wherein, the CF 4 The gas flow rate of (A) is 10to 300sccm, O 2 The gas flow rate of (C) is 5-200 sccm, and the CH 3 The gas flow rate of (A) is 60-800 sccm, the HeThe gas flow rate is 60-200 sccm.
Referring to fig. 7, a protective layer 230 is formed on the bottom and the sidewalls of the first groove 201 and the second groove 202, and the protective layer 230 extends to the sidewalls of the sacrificial sidewall 221 and the top of the channel pillar 220.
In this embodiment, the protection layer 230 extends to the top of the hard mask layer 212.
In this embodiment, the material of the protection layer 230 is silicon nitride; in other embodiments, the material of the protection layer 230 may also be silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, or the like.
In this embodiment, the forming process of the protection layer 230 is an atomic layer deposition process; in other embodiments, the forming method of the protection layer 230 may also be a physical vapor deposition process or a chemical vapor deposition process.
In this embodiment, the protective layer 230 is formed by an atomic layer deposition method, and the specific process parameters include: the gas used comprises DCS gas doped SiH 2 Cl 2 Or ammonia (NH) 3 ) The flow rate of the gas is 1500-4000 sccm; the temperature is 200-600 ℃; the etching pressure is 1-10 mTorr.
Referring to fig. 8, the protective layer 230 on the bottom and the sidewall of the first groove 201 is removed by etching, and the protective layer 230 on the sidewall of the sacrificial sidewall 221 near the first groove 201 is removed by etching until the bottom and the sidewall of the first groove 201 are exposed.
In this embodiment, the protection layer 230 on the bottom and the sidewall of the first groove 201, the protection layer 230 on the sidewall of the sacrificial sidewall 221 near the first groove 201, and the protection layer 230 on the top of the hard mask layer 212 are etched and removed until the bottom and the sidewall of the first groove 201 are exposed, and the protection layer 230 on the bottom and the sidewall of the second groove 202 is not removed, so as to ensure that a second source doped layer is only formed in the first groove 201 in the following step, and a second source doped layer is not also formed in the second groove 202; and on the other hand, the diffusion of doping ions in the subsequently formed second source doping layer into the channel is reduced, the damage to the channel is reduced, and the quality of the formed channel is ensured.
In this embodiment, the method for removing the protection layer 230 is dry etching; in other embodiments, the protection layer 230 may be removed by wet etching.
In this embodiment, the etching process is performed by using carbon tetrafluoride (CF) 4 )、CH 3 F gas and oxygen (O) 2 ) As an etching atmosphere; the carbon tetrafluoride (CF) 4 ) The gas flow range of the gas is 5-100 sccm, and the CH 3 The gas flow range of the F gas is 8-250 sccm; the oxygen (O) 2 ) The gas flow range of (2) is 10-400 sccm; the range of the source radio frequency power RF is 50-300W; the voltage range is 30 to 100V; the etching treatment time is 4 to 50 s; the etching pressure is 10-2000 mTorr.
Referring to fig. 9, a second source doping layer 240 is formed on the bottom and sidewalls of the first groove 201.
In this embodiment, the second source doped layer 240 serves as a source of the semiconductor device.
In this embodiment, the process of forming the second source doping layer 240 includes an epitaxial growth process.
In this embodiment, an initial second source doping layer is formed by an epitaxial growth process, and the formed initial second source doping layer is ion-doped to form the second source doping layer 240.
In this embodiment, the ion doping adopts an ion implantation process; in other embodiments, the ion doping may also be an in-situ doping process.
In this embodiment, the doping concentration range of the second source doping layer 240 is 1.0E21atm/cm 3 ～1.2E22atm/cm 3 。
In this embodiment, the doping concentration of the second source doping layer 240 is greater than the doping concentration of the first source doping layer 210, and the purpose of ensuring that the doping concentration of the second source doping layer 240 is greater than the doping concentration of the first source doping layer 210 is to: the second source doping layer 240 requires a larger doping concentration to reduce contact resistance, but the doping concentration of the first source doping layer 210 is lower to control dopant ions not to diffuse into the channel.
In this embodiment, the process parameters of the epitaxial growth process include: the method comprises the following steps: h 2 、HCl、SiH 2 Cl 2 、B 2 H 6 Or by using a gas mixture comprising H 2 、HCl、SiH 2 Cl 2 、PH 3 The mixed gas of (1).
In this embodiment, when forming a PMOS, the method includes: h 2 、HCl、SiH 2 Cl 2 、B 2 H 6 Wherein the H is 2 The gas flow rate of (A) is 100-2000 sccm, the gas flow rate of HCl is 10-800 sccm, and the SiH 2 Cl 2 The gas flow rate of B is 50-1000 sccm 2 H 6 The gas flow rate of (2) is 10-400 sccm; the technological parameters of the epitaxial growth process further comprise: the pressure is 20-400 torr, and the temperature is 600-800 ℃.
In this embodiment, when forming an NMOS, the method includes: h 2 、HCl、SiH 2 Cl 2 、PH 3 Wherein the H is 2 The gas flow rate of (A) is 100-2000 sccm, the gas flow rate of HCl is 10-800 sccm, and the SiH 2 Cl 2 The gas flow rate is 50-1000 sccm and the PH 3 The gas flow rate of (2) is 100-2500 sccm; the technological parameters of the epitaxial growth process further comprise: the pressure is 20-400 torr, and the temperature is 600-800 ℃.
In this embodiment, the top surface of the second source doping layer 240 is lower than the top surface of the first source doping layer 210, so that when a gate structure is formed subsequently, the distance from the gate structure to the second source doping layer 240 is increased, and the distance from a channel to the second source doping layer 240 is also increased, so that the parasitic capacitance between the gate structure and the second source doping layer 240 is reduced, so that in the using process of a semiconductor device, the interference effect of the parasitic capacitance on the semiconductor device is smaller, the alternating current characteristic of the semiconductor device is enhanced, and the using performance and the stability of the semiconductor device are improved.
Referring to fig. 10, the protective layer 230 on the bottom and the sidewall of the second groove 202, the sidewall of the sacrificial sidewall 221 near the second groove 202, and the top of the channel pillar 220 are etched away until the bottom and the sidewall of the second groove 202 and the top and the sidewall of the channel pillar are exposed.
In this embodiment, after the second source doping layer 240 is formed, the remaining protection layer 230 is removed until the second groove 202 is exposed.
In this embodiment, the second source doping layer is not formed on the bottom and the sidewall of the second groove 202, and when the gate structure is formed on the second groove 202, the second source doping layer is not formed at the bottom of the gate structure, so that the parasitic capacitance between the gate structure and the second source doping layer is reduced, and the influence of the parasitic capacitance on the performance of the semiconductor device is reduced during the use of the semiconductor device, thereby improving the stability of the performance of the formed semiconductor device.
Referring to fig. 11, the sacrificial spacers 221 are removed.
In this embodiment, the hard mask layer 212 on top of the trench pillar 220 is removed simultaneously.
In this embodiment, the process of removing the sacrificial side wall 221 is a dry etching process; in other embodiments, a wet etching process or an ashing process may be used for removal.
Referring to fig. 12, an isolation layer 250 is formed on the substrate 200 and the second source doped layer 240, the isolation layer 250 is located on a portion of the sidewall of the channel pillar 220, and a top surface of the isolation layer 250 is lower than a top surface of the channel pillar 220.
In this embodiment, the material of the isolation layer 250 is silicon oxide; in other embodiments, the material of the isolation layer 250 may also be silicon nitride, silicon carbide, silicon oxynitride, or the like.
In this embodiment, the isolation layer 250 plays a role of electrical isolation.
Referring to fig. 13, a gate structure is formed on a sidewall surface of the channel pillar 220.
The gate structure includes a first portion surrounding the channel pillar 220 and a second portion on the surface of the substrate 200 at one side of the channel pillar 220.
The gate structure first portion includes: a gate dielectric layer 222 on the sidewall and the top of the trench pillar 220, a work function layer 223 on the surface of the gate dielectric layer 222, and a gate layer 224 on the surface of the work function layer 223.
The gate structure second portion comprises: a work function layer 223 on the surface of the substrate 200, and a gate layer 224 on the surface of the work function layer 223.
The forming method of the gate dielectric layer 222 includes: forming a gate dielectric material layer (not shown) on the surface of the substrate 200 and the sidewall surface and the top surface of the channel pillar 220; forming a mask layer (not shown) on the surface of the gate dielectric material layer, wherein the mask layer exposes a part of the surface of the gate dielectric material layer; and etching the gate dielectric material layer by taking the mask layer as a mask until the surface of the second source doping layer 240 is exposed, and forming the gate dielectric layer 222 on the side wall and the top of the channel column 220.
In this embodiment, the gate dielectric layer 222 is made of a high-k material, and the dielectric constant of the high-k material is greater than 3.9; the high dielectric constant material comprises hafnium oxide or aluminum oxide.
In other embodiments, the material of the gate dielectric layer includes silicon oxide.
After the gate dielectric layer 222 is formed, the mask layer is removed.
The forming method of the work function layer 223 and the gate layer 224 includes: forming a work function material layer (not shown) on the surface of the substrate 200 and the surface of the gate dielectric layer 222; forming a gate material layer (not shown) on the surface of the work function material layer; forming a mask layer (not shown) on the surface of the gate material layer, wherein the mask layer exposes a part of the surface of the gate material layer; and etching the gate material layer and the work function material layer by using the mask layer as a mask until the surface of the second source doping layer 240 is exposed, and forming the work function layer 223 and the gate layer 224 on the work function layer 223 on the sidewall of the channel pillar 220 and the surface of the substrate 200.
The material of the work function layer 223 includes titanium nitride, titanium aluminum nitride, or tantalum nitride.
The material of the gate layer 224 includes polysilicon or metal. In the present embodiment, the material of the gate layer 224 includes a metal, and the metal includes tungsten.
After the work function layer 223 and the gate layer 224 are formed, the mask layer is removed.
Referring to fig. 14, after the gate structure is formed, a second isolation layer 260 is formed on the isolation layer 250, the second isolation layer 260 exposes the top of the channel pillar 220, a third isolation layer 270 is formed on the gate structure and on the second isolation layer 260, a first trench (not shown) is formed in the third isolation layer 270, the second isolation layer 260, the isolation layer 250 and the second source doping layer 240, and a first conductive structure 271 is formed in the first trench; forming a second trench (not shown) in the third isolation layer 270, wherein the bottom of the second trench exposes the top surface of the channel pillar 220, and forming a second conductive structure 272 in the second trench; a third trench (not shown) is formed in the third isolation layer 270 and the second isolation layer 260, the bottom of the third trench exposing a second portion of the gate structure, and a third conductive structure 273 is formed in the third trench.
In this embodiment, before forming the third isolation layer 270, an initial second isolation layer is formed, the top surface of the initial isolation layer is higher than the top surface of the gate structure, and the initial second isolation layer and the gate structure on the top of the channel pillar 220 are etched back until the top of the channel pillar 220 is exposed, so as to form the second isolation layer 260.
The second isolation layer 260 and the isolation layer 250 together provide structural support and electrical isolation for the first conductive structure in the second source doped layer 240 and the third conductive structure formed on the second portion of the gate structure.
The third spacer 270, the second spacer 260, and the spacer 250 together provide structural support and electrical isolation for the first conductive structure in the second source doped layer 240, the third conductive structure formed on the second portion of the gate structure, and the second conductive structure formed on the top surface of the channel pillar.
The top surface of the third isolation layer 270 is higher than the top surface of the gate structure.
In this embodiment, the process of forming the first trench, the second trench, and the third trench is a conventional process, and will not be described redundantly here.
In this embodiment, the processes of forming the first conductive structure 271, the second conductive structure 272, and the third conductive structure 273 are conventional processes, and will not be described redundantly here.
In this embodiment, the material of the first conductive structure 271 includes a metal, and the metal includes copper, aluminum, tungsten, cobalt, titanium, or nickel.
In this embodiment, the material of the second conductive structure 272 includes a metal, and the metal includes copper, aluminum, tungsten, cobalt, titanium, or nickel.
In this embodiment, the material of the third conductive structure 273 includes a metal including copper, aluminum, tungsten, cobalt, titanium, or nickel.
Accordingly, the present invention also provides a semiconductor device comprising: a substrate 200; a first source doped layer 210 on the substrate 200; a channel pillar 220 on the first source doping layer 210; sacrificial side walls 221 located on the side walls of the channel pillars 220; a first groove 201 in the substrate 200 at one side of the channel pillar 220; a second groove 202 in the substrate 200 on the other side of the channel pillar 220; and a second source doping layer 240 on the bottom and sidewalls of the first groove 201.
In this embodiment, the second source doping layer 240 is formed in the first groove 201, the second source doping layer is not formed in the second groove 202, and subsequently, when the gate structure is formed, the source doping layer is not formed at the bottom of the gate structure, so that the parasitic capacitance between the gate structure and the source doping layer is reduced, thereby reducing the interference effect of the parasitic capacitance generated in the operation process of the semiconductor device, improving the alternating current characteristics of the semiconductor device, and improving the quality and performance of the formed semiconductor device.
In this embodiment, the top surface of the second source doping layer 240 is lower than the top surface of the first source doping layer 210, so that when a gate structure is formed, the distance between the gate structure and the second source doping layer 240 is increased, and the distance between a channel and the second source doping layer 240 is also increased, thereby reducing the parasitic capacitance between the gate structure and the second source doping layer 240, and facilitating to improve the performance and stability of the formed semiconductor device.
In this embodiment, the doping concentration of the second source doping layer 240 is greater than that of the first source doping layer 210, the second source doping layer 240 needs a greater doping concentration to reduce the contact resistance, but the lower concentration of the first source doping layer 210 is to control the diffusion of the dopant ions into the channel.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (13)

1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein a first source doping layer is formed on the substrate;
forming a channel column on the first source doping layer;
forming a sacrificial side wall on the side wall of the channel column;
etching and removing the first source doping layer on two sides of the sacrificial side wall and the substrate with partial thickness by taking the sacrificial side wall as a mask, and forming a first groove and a second groove in the substrate;
forming a second source doping layer on the bottom and the side wall of the first groove;
the doping concentration of the second source doping layer is greater than that of the first source doping layer.
2. The method of forming of claim 1, wherein a top surface of the second source doped layer is lower than a top surface of the first source doped layer.
3. The forming method of claim 1, wherein a doping concentration of the second source doped layer ranges from 1.0E21atm/cm 3 ～1.2E22atm/cm 3 。
4. The method of forming of claim 1, wherein the process of forming the second source dopant layer comprises an epitaxial growth process.
5. The formation method of claim 4, wherein the process parameters of the epitaxial growth process comprise: the method comprises the following steps: h 2 、HCl、SiH 2 Cl 2 、B 2 H 6 Or by using a gas mixture comprising H 2 、HCl、SiH 2 Cl 2 、PH 3 The mixed gas of (2).
6. The method of forming as claimed in claim 5, wherein when employed, comprises: h 2 、HCl、SiH 2 Cl 2 、B 2 H 6 In the mixed gas of (1), wherein, the H 2 The gas flow rate of (A) is 100-2000 sccm, the gas flow rate of HCl is 10-800 sccm, and the SiH 2 Cl 2 The gas flow rate of B is 50-1000 sccm 2 H 6 The gas flow rate of (2) is 10-400 sccm; the technological parameters of the epitaxial growth process further comprise: the pressure is 20-400 torr, and the temperature is 600-800 ℃.
7. The method of forming as claimed in claim 5, wherein when employed, comprises: h 2 、HCl、SiH 2 Cl 2 、PH 3 In the mixed gas of (1), wherein, the H 2 The gas flow rate of the gas is 100 to 2000sccm, the gas flow of HCl is 10-800 sccm, and SiH 2 Cl 2 The gas flow rate is 50-1000 sccm and the PH 3 The gas flow rate of (2) is 100-2500 sccm; the technological parameters of the epitaxial growth process further comprise: the pressure is 20-400 torr, and the temperature is 600-800 ℃.
8. The method of forming as claimed in claim 1, further comprising, prior to forming the second source doped layer:
forming a protective layer on the bottom and the side wall of the first groove and the second groove, wherein the protective layer extends to the side wall of the sacrificial side wall and the top surface of the channel column;
and etching to remove the protective layer on the bottom and the side wall of the first groove so as to be close to the protective layer on the side wall of the sacrificial side wall of the first groove.
9. The method of claim 8, wherein after forming the second source dopant layer, etching away the bottom and sidewalls of the second recess, the protective layer on sidewalls of the sacrificial sidewall near the second recess, and the top of the trench pillar.
10. The forming method of claim 1, wherein a process of forming the first recess and the second recess is a dry etching process or a wet etching process.
11. The method of forming as claimed in claim 1, wherein after forming the second source doping layer, further comprising: and removing the sacrificial side wall.
12. A semiconductor device, comprising:
a substrate;
the first source doping layer is positioned on the substrate;
the channel column is positioned on the first source doping layer;
the sacrificial side wall is positioned on the side wall of the channel column;
a first groove in the substrate on one side of the channel pillar;
a second groove located in the substrate on the other side of the channel column;
the second source doping layer is positioned at the bottom and on the side wall of the first groove;
the doping concentration of the second source doping layer is greater than that of the first source doping layer.
13. The semiconductor device of claim 12, wherein a top surface of the second source doped layer is lower than a top surface of the first source doped layer.
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CN101226960A (en) * 2007-01-18 2008-07-23 三星电子株式会社 Access device having vertical channel and related semiconductor device and a method of fabricating the access device
CN107845579A (en) * 2016-09-19 2018-03-27 格芯公司 The method that bottom and top source/drain regions are formed in vertical transistor devices
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