CN110098151A - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN110098151A CN110098151A CN201810097227.0A CN201810097227A CN110098151A CN 110098151 A CN110098151 A CN 110098151A CN 201810097227 A CN201810097227 A CN 201810097227A CN 110098151 A CN110098151 A CN 110098151A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 238000000034 method Methods 0.000 title claims abstract description 78
- 150000002500 ions Chemical class 0.000 claims abstract description 72
- 238000000137 annealing Methods 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000010410 layer Substances 0.000 claims description 177
- 239000011241 protective layer Substances 0.000 claims description 62
- 239000000463 material Substances 0.000 claims description 43
- 239000007789 gas Substances 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 23
- -1 phosphonium ion Chemical class 0.000 claims description 21
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 229910052796 boron Inorganic materials 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- 238000011065 in-situ storage Methods 0.000 claims description 4
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 3
- 241000208340 Araliaceae Species 0.000 claims description 2
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 claims description 2
- 235000003140 Panax quinquefolius Nutrition 0.000 claims description 2
- 235000008434 ginseng Nutrition 0.000 claims description 2
- 229910001449 indium ion Inorganic materials 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 1
- 229910052698 phosphorus Inorganic materials 0.000 claims 1
- 239000011574 phosphorus Substances 0.000 claims 1
- 238000002955 isolation Methods 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 230000005669 field effect Effects 0.000 description 8
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- 125000006850 spacer group Chemical group 0.000 description 6
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- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
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- 230000033001 locomotion Effects 0.000 description 4
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- 239000013078 crystal Substances 0.000 description 3
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- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
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- 238000001039 wet etching Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of semiconductor devices and forming method thereof, method include: offer semiconductor substrate, have the first fin and the first grid structure across first fin in the semiconductor substrate；The first fin side wall and top surface in first grid structure two sides form the first doped layer, have the first Doped ions in first doped layer；The first annealing is carried out, so that the first Doped ions in the first doped layer enter fin, forms the first lightly doped district in the first fin.The method improves the performance of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of semiconductor devices and forming method thereof.
Background technique
With the rapid development of semiconductor processing technology, semiconductor devices is towards higher component density and higher
The direction of integrated level is developed.Device is just widely used at present as most basic semiconductor devices, traditional planar device pair
The control ability of channel current dies down, and generates short-channel effect and leads to leakage current, the final electrical property for influencing semiconductor devices
Energy.
In order to overcome the short-channel effect of device, inhibit leakage current, the prior art proposes fin formula field effect transistor
(Fin FET), fin formula field effect transistor are a kind of common multi-gate devices, and the structure of fin formula field effect transistor includes: position
In the fin and separation layer of semiconductor substrate surface, the side wall of fin described in the separation layer covering part, and insulation surface
Lower than at the top of fin；Gate structure positioned at the top and sidewall surfaces of insulation surface and fin；Positioned at the grid knot
Source region and drain region in the fin of structure two sides.
However, to be formed by performance of semiconductor device poor for the forming method of existing semiconductor devices.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of semiconductor devices and forming method thereof, can optimize semiconductor device
The performance of part.
In order to solve the above technical problems, the present invention provides a kind of forming method of semiconductor devices, comprising: provide semiconductor
Substrate has the first fin and the first grid structure across first fin in the semiconductor substrate；In first grid
The the first fin side wall and top surface of structure two sides form the first doped layer, have in first doped layer first adulterate from
Son；The first annealing is carried out, so that the first Doped ions in the first doped layer enter fin, forms the in the first fin
One lightly doped district；
Optionally, further includes: formed before first doped layer, form protection side wall in first grid structure side wall；
The forming method of the protection side wall includes: to form initial protective layers on a semiconductor substrate, initial protective layers covering the
The side wall and top surface of one gate structure sidewall and top surface and the first fin；Remove the of first grid structure two sides
The initial protective layers of one fin side wall and top form protection side wall in first grid structure side wall.
Optionally, further includes: after the first annealing, in the first fin of first grid structure and protection side wall two sides
Form the first source and drain doping layer.
Optionally, after the forming method of the first source and drain doping layer includes: the first annealing, in first grid structure
The first groove is formed in the first fin of protection side wall two sides；The first source and drain doping layer is formed in the first groove.
Optionally, the forming method of the source and drain doping layer further include: after the first annealing, form first groove
Before, it is etched back to first doped layer, forms the first sacrificial layer in the first fin side wall；After forming first sacrificial layer, go
Except the first fin of first grid structure and protection side wall two sides forms the first groove, the side wall of the first groove exposes described the
One sacrificial layer；The first source and drain doping layer is formed in the first groove；After forming the first source and drain doping layer, removes described first and sacrifice
Layer.
Optionally, the technique for forming first doped layer includes depositing operation；Described is adulterated in the first doped layer
The technique of one Doped ions is doping process in situ.
Optionally, when the first grid structure is used to form N-type device, the material of first doped layer includes oxidation
Silicon, silicon nitride；First Doped ions are N-type ion, and first Doped ions include phosphonium ion or arsenic ion.
Optionally, first doped layer with a thickness of 10 angstroms~50 angstroms,
Optionally, first Doped ions are phosphonium ion, and the concentration containing phosphonium ion is in first doped layer
1.0E18atm/cm3~1.0E21atm/cm3。
Optionally, when the first grid structure is used to form P-type device, the material of first doped layer includes oxygen
SiClx, silicon nitride；First Doped ions are P-type ion, and first Doped ions include boron ion, BF2-Ion or indium
Ion.
Optionally, first doped layer with a thickness of 20 angstroms~80 angstroms.
Optionally, first Doped ions are boron ion, and the concentration containing boron ion is in first doped layer
1.0E19atm/cm3~2.5E22atm/cm3。
Optionally, it is described first annealing parameter include: the annealing temperature range be 900 degrees Celsius~
1100 degrees Celsius, the time of the annealing is 0 second~20 seconds, and the gas of the annealing utilized is nitrogen, described
The range of flow of nitrogen is 10sccm~1000sccm.
Optionally, the semiconductor substrate includes first area and second area, and first area and second area are formed
Semiconductor devices type it is opposite；First fin and first grid structure are located at semiconductor substrate first area, semiconductor lining
Bottom second area also has the second fin, has the second grid structure across the second fin on second fin.
Optionally, the initial protective layers are also located at the second fin side wall and top surface and second grid structure side wall
And top surface, after forming protection side wall, the initial protective layers are located at the part on second area as protective layer.
Optionally, the method for removal first grid structure two sides the first fin side wall and the initial protective layers at top includes:
The first patterned layer is formed on initial protective layers, first patterned layer exposes the position of semiconductor substrate first area
It sets；The initial protective layers are etched back to using first patterned layer as exposure mask, until exposing the first fin and first grid
The top surface of structure forms initial protection side wall in first grid structure side wall and the first fin side wall；Form initial protection
After side wall, second graphical layer is formed in first fin, first grid structure, the second fin and second grid structure；
The second graphical layer exposes the position of the initial protection side wall of the first fin side wall, is to cover with the second graphical layer
Film, the initial protection side wall of etching the first fin side wall of removal, exposes first grid structure and protection the first fin of side wall two sides
Portion's side wall and top surface.
It optionally, further include forming the second source on the second region after forming the first source and drain doping layer on the first region
Doped layer is leaked, after the forming step of the second source and drain doping layer includes: removal first sacrificial layer, in the first fin, the
The second protective layer is formed in one gate structure, the first source and drain doping layer, the second fin and second grid structure；Remove second area
Second fin side wall of upper second grid structure two sides and second protective layer at top；Remove second grid structure on second area
After second fin side wall of two sides and second protective layer at top, at the second fin side wall of second grid structure two sides and top
Surface forms the second doped layer, and second doped layer has the second Doped ions；To second doped layer and the second fin
The second annealing is carried out, so that the second Doped ions in second doped layer enter formation second in the second fin and gently mix
Miscellaneous area；After second annealing, the second groove is formed in the second fin of second grid structure two sides, the shape in the second groove
At the second source and drain doping layer.
The present invention also provides a kind of semiconductor devices formed using above-mentioned any one method.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In technical solution of the present invention, by forming the first doped layer, institute on the first fin of first grid structure two sides
Stating has the first Doped ions in the first doped layer, drives first Doped ions to diffuse into the by the first annealing
One fin is to form the first lightly doped district.Since the first Doped ions are unordered diffusions, the movement of all directions has, so
The first lightly doped district of first grid structure can be formed close to.First annealing is carried out by the first Doped ions of thermal drivers
Unordered diffusion, the energy comparison that the first Doped ions carry is small, and smaller, while thermal annealing is damaged caused by the first fin
The damage defect in the first fin can be repaired, improves the crystal lattice state in the first fin, to improve the performance of device.
Detailed description of the invention
Fig. 1 to Figure 16 is the structural schematic diagram of the forming method of the semiconductor devices of one embodiment of the invention.
Specific embodiment
As stated in the background art, as the density of semiconductor devices improves, size reduction, performance of semiconductor device still needs
It improves.
A kind of forming method of semiconductor devices, comprising: semiconductor substrate is provided, there are several fins in semiconductor substrate
Portion；Isolation structure is formed on the semiconductor substrate, and the isolation structure covers fin partial sidewall；The shape on the fin
At the gate structure across the fin, the gate structure covering part fin side wall and top surface；In the grid knot
Structure two sides form the first side wall, and first side wall covers gate structure sidewall；After forming the first side wall, the fin is formed
Lightly doped district ion implanting forms lightly doped district, after forming lightly doped district, is formed in the gate structure and the first side wall side wall
Second side wall forms groove in the gate structure and the second side wall two sides；It is epitaxially formed source and drain doping layer in a groove.
However, the performance for the semiconductor devices that the method is formed is poor, in the above-described embodiments, with semiconductor technology
Development, the size in fin width direction is smaller and smaller, directly carries out ion implanting, ion to the fin lightly doped district that exposes
The energy bombardment of injection is easy so that the part lattice of fin becomes amorphous state by monocrystalline state, and Atomic Arrangement is become by regular array
Disordered state causes to damage to the fin；Meanwhile the fuel factor of annealing can be leading in the monocrystalline state of perfect lattice
In the case where, not by the fin of ion implanting be monocrystalline state, based on the monocrystalline state fin to amorphous fin into
Row recrystallization, makes the lattice of most of fin become amorphous state, monocrystalline state by monocrystalline state since fin is too small, after ion bombardment
It is limited that ability is recrystallized in the case where on the low side, can not recrystallize to form the neat fin of lattice structure, so that the damage of fin
The defects of wound can not repair completely, will cause electric leakage.
In order to solve the above-mentioned technical problem, technical solution of the present invention passes through Solid Source by forming doped layer on fin
The mode of doping realizes the ion doping to fin lightly doped district, so that device performance gets a promotion.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Fig. 1 to Figure 16 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
Fig. 1 and Fig. 2 are please referred to, the area Tu2Zhong I is sectional view of the Fig. 1 along the direction M-M1, and the area Zhong Dui II Fig. 2 is Fig. 3 along M2-
The sectional view in the direction M3 provides semiconductor substrate 200.
The semiconductor substrate 200 includes first area I and second area II, the semiconductor substrate of the first area I
There is the first fin 211 on 200, there is the second fin 212 in the semiconductor substrate 200 of the second area II.It is described partly to lead
Also there is isolation structure 201, the isolation structure 201 covers the first fin 211 and 212 part of the second fin in body substrate 200
Side wall.
When the first area I is used to form P-type device, second area II is used to form N-type device, the first area
When I is used to form N-type device, the second area II is used to form P-type device.
In the present embodiment, the first area I is used to form N-type fin formula field effect transistor, and second area II is used for shape
At p-type fin formula field effect transistor.
The material of the semiconductor substrate 200 includes the semiconductor materials such as silicon, germanium, SiGe, GaAs, indium gallium arsenic,
Middle silicon materials include monocrystalline silicon, polysilicon or amorphous silicon.The semiconductor substrate 200 can also be semiconductor-on-insulator knot
Structure, the semiconductor-on-insulator structure include insulator and the semiconductor material layer on insulator, the semiconductor material
The material of the bed of material includes the semiconductor materials such as silicon, germanium, SiGe, GaAs, indium gallium arsenic.
In the present embodiment, the material of the semiconductor substrate 200 is monocrystalline silicon.
In the present embodiment, first fin 211 and the second fin 212 pass through the graphical semiconductor substrate 200
It is formed.In other embodiments, it may is that formation fin material layer on the semiconductor substrate, then the graphical fin
Portion's material layer, to form first fin 211 and the second fin 212.
In the present embodiment, the material of first fin 211 and the second fin 212 is monocrystalline silicon.In other embodiments,
The material of first fin 211 and the second fin 212 is monocrystalline germanium silicon or other semiconductor materials.
The forming step of the isolation structure 201 includes: that initial isolation film (not shown) is formed on the substrate 200,
The initial isolation film covers the top surface of first fin 211 and the second fin 212；Planarize the initial isolation
Film, until exposing the surface at 212 top of the first fin 211 and the second fin；It is etched back to the initial isolation film, is exposed described
The partial sidewall of first fin 211 and the second fin 212 forms isolation structure 201.The isolation structure 201 for electricity every
From the first fin 211 and the second fin 212.
The material of the initial isolation film includes silicon oxide or silicon nitride.
In the present embodiment, the material of the initial isolation film is silica；It is etched back to the thickness of the rear initial isolation film
Degree is the 1/4~1/2 of 212 height of first fin 211 and the second fin.The formation process of the initial isolation film is fluid
Chemical vapor deposition process (Flowable Chemical Vapor Deposition, abbreviation FCVD).
In other embodiments, the initial isolation film can also using plasma enhancing chemical vapor deposition process
(PECVD) or high-aspect-ratio chemical vapor deposition process (HARP).
The flatening process is CMP process (CMP)；In the present embodiment, the chemically mechanical polishing work
Skill is until the top surface for exposing first fin 211 and the second fin 212.
In the present embodiment, the material of the isolation structure 201 is silica.
Referring to FIG. 3, Fig. 3 with Fig. 2 profile direction is consistent, it is developed across on the 200 first area I of semiconductor substrate
The first grid structure 221 of first fin 211, first grid structure 221 is across the first fin 211 and the first fin 211 of covering
Atop part surface and partial sidewall surface；The second fin 212 is developed across on 200 second area II of semiconductor substrate
Second grid structure 222, second grid structure 222 is across the atop part surface of the second fin 212 and the second fin 212 of covering
With partial sidewall surface.
In the present embodiment, first grid structure 221 includes across the first gate dielectric layer of the first fin 211, positioned at first
First gate electrode layer on gate dielectric layer and the first grid protective layer at the top of first gate electrode layer.Second grid structure
222 include across the second gate dielectric layer of the second fin 212, the second gate electrode layer on gate dielectric layer and positioned at second
Second gate protective layer at the top of gate electrode layer.In other embodiments, first grid protective layer and second gate protective layer are not formed.
In the present embodiment, the material of the first gate dielectric layer and the second gate dielectric layer is silica, the first gate electrode layer
Material with the second gate electrode layer is polysilicon.The material of the first grid protective layer and second gate protective layer is silicon nitride, nitrogen
Silica, silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.
In the present embodiment, the first grid structure 221 and second grid structure 222 are as pseudo- grid structure, rear extended meeting shape
Pseudo- grid structure is substituted at high-K metal gate.In other embodiments, the first grid structure 221 and second grid structure 222 are made
For the gate structure of device.
Referring to FIG. 4, after forming first grid structure 221 and second grid structure 222, in first grid structure 221
Side wall forms the first side wall 231, forms the second side wall 232 in the side wall of second grid structure 222.
First side wall 231 protects the first grid layer side wall, and the second side wall 232 protects second grid layer side wall.
The forming step of first side wall 231 and the second side wall 232 includes: in 201 first fin of isolation structure
211, the first spacer material layer is formed in first grid structure 221, the second fin 212 and second grid structure 222, described first
Spacer material layer covers the partial sidewall surface and atop part surface, the first grid structure 221 of first fin 211
Side wall and top surface, the partial sidewall surface of the second fin 212 and atop part surface and the second grid structure
222 side wall and top surface；It is etched back to the first spacer material layer, until exposing first fin 211, the second fin
Portion 212, first grid protective layer and second gate protective layer top surface, on the first fin 211 formed be covered in described first
First side wall 231 of 221 side wall of gate structure forms on the second fin 212 and is covered in 222 side wall of second grid structure
The second side wall 232.
The formation process of the first spacer material layer is chemical vapor deposition process, physical gas-phase deposition or atom
One of layer depositing operation or multiple combinations.
The material of the first spacer material layer includes silica, silicon nitride, silicon oxynitride, silicon oxide carbide, carbonitride of silicium
Or carbon silicon oxynitride.
In the present embodiment, the formation process of the first spacer material layer is chemical vapor deposition process.First side
The material of wall 231 and the second side wall 232 is silicon nitride.
With reference to Fig. 5 and Fig. 6, Fig. 5 is consistent with Fig. 4 profile direction, and Fig. 6 is sectional view of the Fig. 5 along the direction N-N1, forms first
After side wall 231 and the second side wall 232, in 201 first fin 211 of isolation structure, first grid structure 221, the second fin
Initial protective layers 240 are formed in portion 212 and second grid structure 222.
In the present embodiment, first area I and second area II is formed by device difference, forms N-type on the I of first area
During fin formula field effect transistor, the initial protective layers 240 are used to form second on protective layer protection second area II
Gate structure 222 and the second fin 212, while protection side wall protection first grid knot is formed in 221 side wall of first grid structure
Structure 221.
The material of the initial protective layers 240 includes: silica, silicon nitride, silicon oxynitride, silicon oxide carbide, carbonitride of silicium
Or carbon silicon oxynitride.
The technique for forming initial protective layers 240 is depositing operation, such as atom layer deposition process or plasma enhanced chemical vapor
Depositing operation.
In the present embodiment, the material of the initial protective layers 240 is silicon nitride.
The initial protective layers 240 with a thickness of 20 angstroms~200 angstroms.
The thickness of the initial protective layers 240 is greater than 200 angstroms, and 241 thickness of protection side wall of formation is thicker, and subsequent first is light
Farther out apart from trench area, the first Doped ions need the distance of horizontal proliferation farther out to doped region, are unfavorable for the first lightly doped district
It is formed；For the thickness of the initial protective layers 240 less than 20 angstroms, source and drain doping layer and the channel region distance being subsequently formed are too short, short
Channelling effect is obvious.
The technique of the initial protective layers 240 is atom layer deposition process, and the parameter of the atom layer deposition process includes:
The gas used is SiH2Cl2And NH3Mixed gas, the flow of mixed gas is 1500sccm~4000sccm, and pressure is
1mtorr~10mtorr, temperature are 200 degrees Celsius~600 degrees Celsius, and frequency of depositing is 30 times~300 times.
Fig. 7 and Fig. 8 are please referred to, Fig. 7 is consistent with Fig. 5 profile direction, and Fig. 8 is sectional view of the Fig. 7 along the direction N-N1, described first
After beginning protective layer 240 is formed, 211 side wall of the first fin of 221 two sides of first grid structure and top in the I of first area are removed
The initial protective layers 240 on surface form protection side wall 241 in 221 side wall of first grid structure.
Remove 221 two sides of first grid structure 211 side wall of the first fin and top protective layer the step of include: back quarter
The initial protective layers 240 on the I of first area are lost, form initial protection side in first grid structure 221 and 211 side wall of the first fin
Wall；After forming initial protection side wall, the initial protection side wall of 211 side wall of the first fin is removed, first grid structure 221 is exposed
211 side wall of the first fin of two sides and top surface, while protection side wall 241 is formed in 221 side wall of first grid structure.
The protection side wall 241 defines the position for the first source and drain doping layer being subsequently formed, while can protect first
Gate structure 221.
The step of initial protective layers 240 being etched back on the I of first area includes: to form first on initial protective layers 240
Patterned layer (not shown), first patterned layer expose the position of semiconductor substrate first area I, with first figure
Shape layer (not shown) is initial protective layers 240 described in mask etching, exposes 221 top surface of first grid structure and first
211 top surface of fin forms initial protection side wall in 211 side wall of the first fin and 221 side wall of first grid structure.
240 technique of initial protective layers being etched back on the I of first area is dry etch process, the dry etch process ginseng
Number includes: that the gas of use includes CF4Gas, CH3F gas and O2, CF4The flow of gas is 5sccm~100sccm, CH3F gas
The flow of body is 8sccm~50sccm, O2Flow be 10sccm~100sccm, chamber pressure be 10mtorr~
2000mtorr, radio-frequency power are 50W~300W, and voltage is 30V~100V, and the time is 4 seconds~50 seconds.
The step of removing the initial protection side wall of 211 side wall of the first fin includes: in first fin 211, the first grid
Second graphical layer (for diagram), second graphical layer are formed in pole structure 221, the second fin 212 and second grid structure 222
Expose the position of the initial protection side wall of 211 side wall of the first fin；Using the second graphical layer as mask etching removal the
The initial protection side wall of one fin, 211 side wall, exposes the top surface of isolation structure 201.
The technique for removing the initial protection side wall of 211 side wall of the first fin is dry etch process, the dry etching work
Skill parameter includes: that the gas of use includes CH3F gas, N2And O2, CH3The flow of F gas is 8sccm~50sccm, N2Gas
Flow is 200sccm, O2Flow be 10sccm, chamber pressure be 10mtorr~200mtorr, radio-frequency power 100W, electricity
Pressure is 30V~100V, and the time is 4 seconds~50 seconds.
During removing 211 side wall of the first fin of 221 two sides of first grid structure and the initial protective layers at top, the
Initial protective layers 240 on two region II are not gone out, and the protective layer 242 on second area II is become.
In the present embodiment, the type that first area I and second area II is formed by semiconductor devices is different, is forming the
During the semiconductor devices of one region I, initial protective layers, which become, forms protective layer on second area II, protects the second fin
With second grid structure.In other embodiments, first area I is identical with the type that second area II is formed by semiconductor devices
When, it does not need to form protective layer on second area II, during forming the semiconductor devices on the I of first area, be formed yet
Semiconductor devices on second area II.
Fig. 9 and Figure 10 are please referred to, Fig. 9 is consistent with Fig. 7 profile direction, and Figure 10 is sectional view of the Fig. 9 along the direction N-N1, removal
211 side wall of the first fin and top surface of first grid structure 221 and protection 241 two sides of side wall is initial in the I of first area
After protective layer 240, in 242 surface of protective layer on second area II, the isolation structure 201 on the I of first area, the first fin
211, the first doped layer 204 is formed in first grid structure 221.First doped layer 204 covers the part of the first fin 221
Side wall and top surface.
First doped layer 204 has the first Doped ions.
When the first grid structure 221 is used to form P-type device, the material of first doped layer 204 includes oxidation
Silicon, silicon nitride；First Doped ions are P-type ion, and first Doped ions include boron ion, BF2-Ion or indium from
Son.
When the first grid structure 221 is used to form N-type device, the material of first doped layer 204 includes oxidation
Silicon, silicon nitride；First Doped ions are N-type ion, and the first Doped ions include phosphonium ion or arsenic ion.
In the present embodiment, the first area I is used to form N-type fin formula field effect transistor.First fin 221
Material is silicon, and the material of first doped layer 204 is silica, and first Doped ions are phosphonium ion.
First doped layer 204 with a thickness of 10 angstroms~50 angstroms.Concentration containing phosphonium ion in first doped layer 204
For 1.0E18atm/cm3~1.0E21atm/cm3。
The formation process of first doped layer 204 includes: chemical vapor deposition process or atom layer deposition process.
In the present embodiment, first doped layer 204, the chemical vapor deposition are formed using chemical vapor deposition process
The parameter of technique are as follows: use the organic precursor gas containing Si and O, be 200 degrees Celsius~700 degrees Celsius in temperature, pressure is
Under conditions of 5mtorr~50torr, it is passed through PH3Gas, PH3Flow be 20sccm~5000sccm, technique number be 5 times~
100 times.
In other embodiments, the first area I is used to form p-type fin formula field effect transistor.First fin 221
Material be silicon, the material of first doped layer 206 is silica, and first Doped ions are boron ion.
First doped layer 204 with a thickness of 20 angstroms~80 angstroms.Dosage containing boron ion in first doped layer 204
For 1.0E19atm/cm3~2.5E22atm/cm3。
First doped layer 204, the parameter of the chemical vapor deposition process are formed using chemical vapor deposition process
Are as follows: use the organic precursor gas containing Si and O, temperature be 200 degrees Celsius~700 degrees Celsius, pressure be 5mtorr~
Under conditions of 50torr, it is passed through BH3Gas, BH3Flow be 10sccm~2000sccm, technique number be 5 times~100 times.
The concentration of first Doped ions is too low in first doped layer 204, is unable to satisfy to form the first lightly doped district
Ion concentration demand；The excessive concentration of first doped layer, 204 first Doped ions, the first Doped ions transverse diffusion distance
Excessive, the first Doped ions quantity into fin channel area is excessive, is easy to turn on, is unfavorable for device performance.
It is subsequent to institute due to being made by doping process in situ doped with the first Doped ions in first doped layer 204
State the first doped layer 204 and the first fin 211 made annealing treatment, heat power in annealing drive the first Doped ions into
Enter the first fin 211, since the diffusion of ion is disordered motion, first Doped ions be also can diffuse into positioned at the first grid
First fin 211 of 241 lower section of the first side wall 231 and protection side wall of 221 side wall of pole structure forms the first lightly doped district.Due to
First Doped ions enter the first fin 211 by diffusion motion, will not have an impact to the lattice of the first fin 211, to the
The damage of one fin 211 is smaller, while can repair the lattice damage of the first fin 211, so that the performance of device be made to be mentioned
It rises.
Please refer to Figure 11, Figure 11 is consistent with Fig. 9 profile direction, formed the first doped layer 204 after, to the first fin 221 into
Row first makes annealing treatment, so that the first Doped ions in the first doped layer 204 enter formation first in the first fin 211 and gently mix
Miscellaneous area.
First annealing is used to drive the first Doped ions in the first doped layer 204 to enter the first fin 211, due to
First Doped ions are unordered diffusions, and the movement of all directions has, it is possible to be formed close to first grid structure 221
First lightly doped district.First annealing is the unordered diffusion carried out by the first Doped ions of thermal drivers, the first Doped ions
The energy comparison of carrying is small, smaller to damaging caused by the first fin 211, while thermal annealing can be repaired in the first fin 211
Damage defect, improve the first fin 211 in crystal lattice state, to improve the performance of device.
First annealing can be rapid thermal annealing, laser annealing, peak value annealing or furnace anneal.The present embodiment
In, first annealing is rapid thermal annealing.The temperature range of the annealing is 900 degrees Celsius~1100 Celsius
Degree, the time of the annealing are 0 second~20 seconds, and the gas of the annealing utilized is nitrogen, the stream of the nitrogen
Amount range is 10sccm~1000sccm.
In one embodiment, using laser annealing, the temperature range of the annealing between 1000 DEG C~1350 DEG C,
The annealing time is at 40 milliseconds~100 milliseconds.
First annealing, the time is shorter, smaller to the damage of the first fin 211, while temperature is higher, and enough the
One Doped ions diffuse into the first fin 211 of first grid structural base, form the first lightly doped district, while can be with
The lattice damage of the first fin 211 is repaired, improves the crystal lattice state in the first fin 211, to improve the performance of device.
With reference to Figure 12, Figure 12 is consistent with Figure 10 profile direction, after the first annealing, is etched back to first doped layer
204, the first sacrificial layer 251 is formed in 221 side wall of the first fin.
It is etched back to first doped layer 204, it is sacrificial also to form second in 241 side wall of protective layer of 222 side wall of the second fin
Domestic animal layer 252.
First sacrificial layer 251 is also located at 221 side wall of first grid structure, and the second sacrificial layer 252 is also located at second gate
The side wall of pole structure 222.
First sacrificial layer 251 limits the direction of growth for 261 bottom of the first source and drain doping layer being subsequently formed, makes
It is smaller to obtain size of 261 bottom of the first source and drain doping layer in 211 width direction of the first fin, the first source being subsequently formed
Leak doped layer 261 in 211 width direction of the first fin growth rate it is slower, in the lesser situation of 211 width of the first fin
Under, avoid adjacent source and drain doping layer joint from influencing the performance of device to cause to leak electricity.
The technique for being etched back to first doped layer 204 is anisotropic dry etching, the dry etching parameter packet
Include: the gas of use includes CH4Gas, CHF3Gas, CH4The flow of gas is 8sccm~500sccm, CHF3The flow of gas
For 30sccm~200sccm, chamber pressure is 10mtorr~2000mtorr, and radio-frequency power is 100W~1300W, and voltage is
80V~500V, time are 4 seconds~50 seconds.
With reference to Figure 13, after forming the first sacrificial layer 251, in first grid structure 221 and the first of protection 241 two sides of side wall
The first groove 205 is formed in fin 211.
First groove 205 is to be subsequently formed the first source and drain doping layer 261 to provide space.
Specifically, the first fin 211 of etching first grid structure 221 and protection 241 two sides of side wall, in the first fin
The first groove 205 is formed in 211, first sacrificial layer 251 is located at 205 side wall of the first groove.
It etches first grid structure 221 and protects the first fin 211 of 241 two sides of side wall, formed in the first fin 211
The technique of first groove 205 is dry etch process, and the technological parameter includes: the first stage using CF4And H2The mixing of gas
Gas, CF4Flow is 10sccm~30sccm, H2Flow is 10sccm~30sccm, and time 7s, temperature is 70 degrees Celsius；The
It includes CH that two-stage, which uses,3F gas, O2With the mixed gas of He, CH3F flow is 60sccm~200sccm, O2Flow is
50sccm~115sccm, He flow are 50sccm~200sccm, and the time is 5 seconds~100s, and temperature is taken the photograph for 35 degrees Celsius~75
Family name's degree.
Figure 14 is please referred to, after forming the formation of the first groove 205, forms the first source and drain doping layer in the first groove 205
261。
The technique for forming the first source and drain doping layer 261 is epitaxial growth technology.It is being epitaxially-formed the first source and drain
It further include that doping in situ is carried out to the first source and drain doping layer 261 during doped layer 261, the Doped ions are the
One source and drain ion.
When the first grid structure is used to form P-type device, the material of the first source and drain doping layer 261 include doped with
The SiGe of first source and drain doping ion, the conduction type of the first source and drain doping ion are p-type；When the first grid structure is used for
When forming N-type device, the material of the first source and drain doping layer 261 includes the silicon doped with the first source and drain doping ion, the first source and drain
The conduction type of Doped ions is N-type.
In the present embodiment, the first area I is used to form N-type device, and the material of the first source and drain doping layer 261 is
Doped with the silicon of phosphonium ion, the first source and drain ion is phosphonium ion.
In embodiment, the first area I is used to form P-type device, and the material of the first source and drain doping layer 261 is
Doped with the SiGe of boron ion, the first source and drain ion is boron ion.
Figure 15 is please referred to, after forming the first source and drain doping layer 261, removes the first sacrificial layer of 211 side wall of the first fin
251。
In the present embodiment, the first sacrificial layer 251 of removal 211 side wall of the first fin also removes 212 side of the second fin simultaneously
Second sacrificial layer 252 of 242 side wall of protective layer of wall.In other embodiments, the guarantor of 212 side wall of the second fin can not also be removed
Second sacrificial layer 252 of 242 side wall of sheath.
The technique for removing the first sacrificial layer 251 of 211 side wall of the first fin is wet-etching technology, the wet etching work
The parameter of skill includes: that the gas of use includes NH3Gas, NF3Gas and He, NH3The flow of gas be 200sccm~
500sccm, NF3The flow of gas is 20sccm~200sccm, and the flow of He is 600sccm~2000sccm, and pressure is
2torr~10torr, time are 20 seconds~100 seconds.
Second is formed on second area II after forming the first source and drain doping layer 261 on the I of first area with reference to Figure 16
Source and drain doping layer 262.
The forming step of the second source and drain doping layer 262 includes: after removing first sacrificial layer 251, in the first fin
Is formed in portion 211, first grid structure 221, the first source and drain doping layer 261, the second fin 212 and second grid structure 222
Two protective layers；Remove the second protection of 212 side wall of the second fin of 222 two sides of second grid structure and top on second area II
Layer；It removes on second area II after 212 side wall of the second fin of 222 two sides of second grid structure and second protective layer at top,
212 side wall of the second fin and top surface in 222 two sides of second grid structure form the second doped layer, second doped layer
With the second Doped ions；Second annealing is carried out to second doped layer and the second fin 212, so that described second mixes
The second Doped ions in diamicton, which enter, forms the second lightly doped district in the second fin；After second annealing, in second grid
The second groove is formed in second fin of structure two sides, forms the second source and drain doping layer in the second groove.
Correspondingly, the present embodiment also provides a kind of semiconductor devices formed using the above method.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (18)
1. a kind of forming method of semiconductor devices characterized by comprising
Semiconductor substrate is provided, there is the first fin and the first grid knot across first fin in the semiconductor substrate
Structure；
The first fin side wall and top surface in first grid structure two sides form the first doped layer, in first doped layer
With the first Doped ions；
The first annealing is carried out, so that the first Doped ions in the first doped layer enter fin, is formed in the first fin
First lightly doped district.
2. the forming method of semiconductor devices as described in claim 1, which is characterized in that further include: it forms described first and mixes
Before diamicton, protection side wall is formed in first grid structure side wall；The forming method of the protection side wall includes: to serve as a contrast in semiconductor
Form initial protective layers on bottom, the initial protective layers covering first grid structure side wall and top surface and the first fin
Side wall and top surface；The initial protective layers for removing the first fin side wall and top of first grid structure two sides, in the first grid
Pole structure side wall forms protection side wall.
3. the forming method of semiconductor devices as claimed in claim 2, which is characterized in that further include: after the first annealing,
The first source and drain doping layer is formed in the first fin of first grid structure and protection side wall two sides.
4. the forming method of semiconductor devices as claimed in claim 3, which is characterized in that the shape of the first source and drain doping layer
After including: the first annealing at method, it is recessed in the first fin of first grid structure and protection side wall two sides to form first
Slot；The first source and drain doping layer is formed in the first groove.
5. the forming method of semiconductor devices as claimed in claim 4, which is characterized in that the formation side of the source and drain doping layer
Method further include: after the first annealing, before forming first groove, first doped layer is etched back to, in the first fin side
Wall forms the first sacrificial layer；After forming first sacrificial layer, removal first grid structure and the first fin for protecting side wall two sides
Portion forms the first groove, and the side wall of the first groove exposes first sacrificial layer；The first source and drain is formed in the first groove to mix
Diamicton；After forming the first source and drain doping layer, first sacrificial layer is removed.
6. the forming method of semiconductor devices as described in claim 1, which is characterized in that form the work of first doped layer
Skill includes depositing operation；The technique of first Doped ions is adulterated in the first doped layer as doping process in situ.
7. the forming method of semiconductor devices as described in claim 1, which is characterized in that when the first grid structure is used for
N-type device is formed, the material of first doped layer includes silica, silicon nitride；First Doped ions are N-type ion,
First Doped ions include phosphonium ion or arsenic ion.
8. the forming method of semiconductor devices as claimed in claim 7, which is characterized in that first doped layer with a thickness of
10 angstroms~50 angstroms.
9. the forming method of semiconductor devices as claimed in claim 8, which is characterized in that first Doped ions be phosphorus from
Son, the concentration containing phosphonium ion is 1.0E18atm/cm in first doped layer3~1.0E21atm/cm3。
10. the forming method of semiconductor devices as described in claim 1, which is characterized in that when the first grid structure is used
When forming P-type device, the material of first doped layer includes silica, silicon nitride；First Doped ions be p-type from
Son, first Doped ions include boron ion, BF2-Ion or indium ion.
11. the forming method of semiconductor devices as claimed in claim 10, which is characterized in that the thickness of first doped layer
It is 20 angstroms~80 angstroms.
12. the forming method of semiconductor devices as claimed in claim 11, which is characterized in that first Doped ions are boron
Ion, the concentration containing boron ion is 1.0E19atm/cm in first doped layer3~2.5E22atm/cm3。
13. the forming method of semiconductor devices as described in claim 1, which is characterized in that the ginseng of first annealing
Number includes: that the temperature range of the annealing is 900 degrees Celsius~1100 degrees Celsius, and the time of the annealing is 0 second
~20 seconds, the gas of the annealing utilized was nitrogen, and the range of flow of the nitrogen is 10sccm~1000sccm.
14. the forming method of semiconductor devices as claimed in claim 5, which is characterized in that the semiconductor substrate includes the
The type that one region and second area, first area and second area are formed by semiconductor devices is opposite；First fin and
One gate structure is located at semiconductor substrate first area, and semiconductor substrate second area also has the second fin, second fin
There is the second grid structure across the second fin in portion.
15. the forming method of semiconductor devices as claimed in claim 14, which is characterized in that the initial protective layers are also located at
Second fin side wall and top surface and second grid structure side wall and top surface, it is described initial after forming protection side wall
Protective layer is located at the part on second area as protective layer.
16. the forming method of semiconductor devices as claimed in claim 15, which is characterized in that removal first grid structure two sides
The method of first fin side wall and the initial protective layers at top includes: that the first patterned layer is formed on initial protective layers, described
First patterned layer exposes the position of semiconductor substrate first area；It is etched back to using first patterned layer as exposure mask described
Initial protective layers, until expose the top surface of the first fin and first grid structure, in first grid structure side wall and the
One fin side wall forms initial protection side wall；After forming initial protection side wall, in first fin, first grid structure, the
Second graphical layer is formed on two fins and second grid structure；The second graphical layer exposes the first of the first fin side wall
Begin to protect the position of side wall to etch the initial protection side wall of the first fin side wall of removal using the second graphical layer as exposure mask,
Expose first grid structure and protection side wall two sides the first fin side wall and top surface.
17. the forming method of semiconductor devices as claimed in claim 14, which is characterized in that form first on the first region
It further include forming the second source and drain doping layer on the second region after source and drain doping layer, the formation step of the second source and drain doping layer
Suddenly after including: removal first sacrificial layer, the first fin, first grid structure, the first source and drain doping layer, the second fin and
The second protective layer is formed in second grid structure；Remove the second fin side wall of second grid structure two sides and top on second area
Second protective layer in portion；Remove the second fin side wall of second grid structure two sides and second protective layer at top on second area
Afterwards, the second fin side wall and top surface in second grid structure two sides form the second doped layer, the second doped layer tool
There are the second Doped ions；Second annealing is carried out to second doped layer and the second fin, so that second doped layer
In the second Doped ions enter the second fin in formed the second lightly doped district；After second annealing, in second grid structure
The second groove is formed in second fin of two sides, forms the second source and drain doping layer in the second groove.
18. a kind of as claim 1 to 17 any one method is formed by semiconductor devices.
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| CN106952806A (en) * | 2016-01-07 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | Improve the method for fin field effect pipe performance |
| US20170229556A1 (en) * | 2016-02-08 | 2017-08-10 | International Business Machines Corporation | Vertical transistor device |
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| CN106298522A (en) * | 2015-05-20 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN106952806A (en) * | 2016-01-07 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | Improve the method for fin field effect pipe performance |
| US20170229556A1 (en) * | 2016-02-08 | 2017-08-10 | International Business Machines Corporation | Vertical transistor device |
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