CN103021925A - STI (shallow trench isolation) manufacturing process, trench etching method and photoresist processing method - Google Patents
STI (shallow trench isolation) manufacturing process, trench etching method and photoresist processing method Download PDFInfo
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- CN103021925A CN103021925A CN2012105643639A CN201210564363A CN103021925A CN 103021925 A CN103021925 A CN 103021925A CN 2012105643639 A CN2012105643639 A CN 2012105643639A CN 201210564363 A CN201210564363 A CN 201210564363A CN 103021925 A CN103021925 A CN 103021925A
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Abstract
Disclosed are an STI manufacturing process, a trench etching method and a photoresist processing method. The STI manufacturing process includes: treating photoresist by HBr to enhance hardness of the photoresist, and forming a polymer film on the surface of the photoresist; removing the polymer film by strong corrosive containing C-F groups or S-F groups; and etching to form a flat-bottom STI trench pattern in a semiconductor substrate by using the photoresist as a mask. The HBr treatment hardens the photoresist, the polymer film formed in the HBr treatment is removed then, and accordingly effect of the polymer film on the subsequent trench etching is avoided, isolation trenches formed have good appearance with no sharp corners. Voids generated in the filling process of silicon dioxide are few or none, and accordingly leakage of the STI is reduced and the satisfactory isolation effect can be achieved.
Description
Technical field
The present invention relates to semiconductor fabrication process, relate in particular to a kind of STI(fleet plough groove isolation structure) the lithographic method of manufacture craft, groove and the manufacture craft of the processing method of photoresist.
Background technology
Along with semiconductor technology enters the deep-submicron epoch, mostly adopt fleet plough groove isolation structure (STI) to carry out lateral isolation between the element below 0.18 micron (for example active area of CMOS integrated circuit) and make.
Fleet plough groove isolation structure is as a kind of device separation, and its concrete technology mainly comprises: with reference to figure 1, provide substrate 101, form successively from bottom to up pad oxide 102, silicon nitride layer 103 and photoresist layer 104 on its surface; With reference to figure 2, in photoresist layer 104, form opening 1 behind the exposure imaging, described opening 1 has the shape corresponding with the isolation structure that defines active area; With reference to figure 3, utilize to have opening 1(such as Fig. 1 indicates) photoresist layer 104 as mask, etching forms and runs through described silicon nitride layer 103 and pad oxide 102 until the interior isolated groove 3 of described substrate 101; With reference to figure 4, remove photoresist 104, and the 3 interior cvd silicon oxide materials 105 of the isolated groove in Fig. 3, described silica material 105 is filled full isolated groove 3 and is covered the silicon nitride layer 103 of isolated groove 3 both sides; With reference to figure 5, by unnecessary silica material 105 on the silicon nitride layer 103 among CMP technique removal Fig. 4, form fleet plough groove isolation structure 4.
, in general technique, the shape of the isolated groove of formation is not fine, sometimes also can form sharp-pointed angle at channel bottom.And the shape of isolated groove affects trench fill, thereby directly affects the fleet plough groove isolation structure that forms.Especially, the fleet plough groove isolation structure that forms in the isolated groove with sharp-pointed groove angle causes edge current leakage easily.
Summary of the invention
The problem that the present invention solves is to avoid the shape of formation isolated groove in the fleet plough groove isolation structure manufacturing process bad, causes the phenomenon of the fleet plough groove isolation structure generation edge current leakage of formation.
For addressing the above problem, the present invention proposes a kind of manufacture craft of fleet plough groove isolation structure, comprising:
Semiconductor substrate is provided;
Form pad oxide in Semiconductor substrate;
Form silicon nitride layer at described pad oxide;
Form the photoresist with fleet plough groove isolation structure figure at described silicon nitride layer;
Utilize HBr to process described photoresist, so that described photoresist hardness strengthens, form polymer film on the surface of photoresist simultaneously;
Utilization contains the corrosive agent of C-F group or S-F group and removes described polymer film;
Utilize photoresist to carry out etching as mask, in described Semiconductor substrate, form the groove figure of the smooth fleet plough groove isolation structure in bottom.
Optionally, described photoresist comprises the ArF photoresist.
Optionally, the corrosive agent of the described C-F of containing group or S-F group comprises SF
6Or CF
4In at least a.
Optionally, the described utilization corrosive agent that contains C-F group or the S-F group technique of removing described polymer film is carried out in that plasma chamber is indoor; The corrosive agent that adopts is SF
6The time, SF is set
6Flow be 50sccm ~ 150sccm, the indoor pressure of plasma chamber is 5mTorr ~ 30mTorr, the time of carrying out is 5s ~ 15s; The corrosive agent that adopts is CF
4The time, CF is set
4Flow be 50sccm ~ 200sccm, the indoor pressure of plasma chamber is 5mTorr ~ 30mTorr, the time of carrying out is 5s ~ 15s.
Optionally, the technique that the described HBr of utilization processes described photoresist is carried out in that plasma chamber is indoor, and the flow that the indoor HBr of described plasma chamber is set is 100sccm ~ 200sccm, and bias power is zero, and pressure is 5mTorr ~ 30mTorr, and the time of carrying out is 5s ~ 15s.
Optionally, also comprise base coat between described photoresist and the silicon nitride, after described silicon nitride layer forms the step of the photoresist with fleet plough groove isolation structure figure, utilizing before HBr processes described photoresist, the photoresist that also comprises having the fleet plough groove isolation structure figure is mask, described base coat is carried out the step of etching.
Optionally, described etching to base coat comprises main etching and two steps of over etching, in the described over etching used etching agent to the etching selection ratio of base coat and base coat next-door neighbour's layer dielectric less than the etching selection ratio of the used etching agent in the described main etching to base coat and base coat next-door neighbour's layer dielectric.
Wherein, relate to a kind of lithographic method of groove in the aforementioned fleet plough groove isolation structure, comprising:
Semiconductor substrate is provided;
Utilize photoetching process to form the photoresist with groove figure in described Semiconductor substrate;
Utilize HBr to process described photoresist, so that described photoresist hardness strengthens, form polymer film on the surface of photoresist simultaneously;
Utilization contains the corrosive agent of C-F group or S-F group and removes described polymer film;
Utilize photoresist to carry out etching as mask, in described Semiconductor substrate, form groove figure.
Optionally, described photoresist comprises the ArF photoresist.
Optionally, the corrosive agent of the described C-F of containing group or S-F group comprises SF
6Or CF
4In at least a.
Optionally, the described utilization corrosive agent that contains C-F group or the S-F group technique of removing described polymer film is carried out in that plasma chamber is indoor; The corrosive agent that adopts is SF
6The time, SF is set
6Flow be 50sccm ~ 150sccm, the indoor pressure of plasma chamber is 5mTorr ~ 30mTorr, the time of carrying out is 5s ~ 15s; The corrosive agent that adopts is CF
4The time, CF is set
4Flow be 50sccm ~ 200sccm, the indoor pressure of plasma chamber is 5mTorr ~ 30mTorr, the time of carrying out is 5s ~ 15s.
Optionally, the technique that the described HBr of utilization processes described photoresist is carried out in that plasma chamber is indoor, and the flow that the indoor HBr of described plasma chamber is set is 100sccm ~ 200sccm, and bias power is zero, and pressure is 5mTorr ~ 30mTorr, and the time of carrying out is 5s～15s.
In addition, the manufacture craft of aforementioned fleet plough groove isolation structure or the lithographic method of groove also relate to a kind of processing method of photoresist, comprising:
Utilize photoetching process to form photoetching offset plate figure at the described graphical substrate for the treatment of;
Utilize HBr to process described photoresist, so that the enhancing of described photoresist hardness, and at photoresist surface formation polymer film;
Utilization contains the corrosive agent of C-F group or S-F group and removes described polymer film.
Optionally, described photoresist comprises the ArF photoresist.
Optionally, the corrosive agent of the described C-F of containing group or S-F group comprises SF
6Or CF
4In at least a.
Optionally, the described utilization corrosive agent that contains C-F group or the S-F group technique of removing described polymer film is carried out in that plasma chamber is indoor; The employing corrosive agent is SF
6The time, SF is set
6Flow be 50sccm ~ 150sccm, the indoor pressure of plasma chamber is 5mTorr ~ 30mTorr, the time of carrying out is 5s ~ 15s; The employing corrosive agent is CF
4The time, CF is set
4Flow be 50sccm ~ 200sccm, the indoor pressure of plasma chamber is 5mTorr ~ 30mTorr, the time of carrying out is 5s ~ 15s.
Optionally, the technique that the described HBr of utilization processes described photoresist is carried out in that plasma chamber is indoor, and the flow that the indoor HBr of described plasma chamber is set is 100sccm ~ 200sccm, and bias power is zero, and pressure is 5mTorr ~ 30mTorr, and the time of carrying out is 5s～15s.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the manufacture method of the fleet plough groove isolation structure that technical scheme of the present invention provides, by HBr process so that photoresist by hardization, and removed the polymer film that forms when HBr processes, avoided described polymer film on the impact of subsequent etching groove, so that pattern is better in the isolated groove that forms, do not have angular generation, it is less or do not have to form the situation in cavity in the filling process of described silicon dioxide, reduce the situation of described fleet plough groove isolation structure electric leakage, can realize satisfactory isolation effect.And the etching of the HBr that provides in present embodiment processing, polymer film etching, isolated groove can both be indoor carrying out of plasma chamber, in technological operation, do not increase complexity, and only need to adopt the problem of original equipment with regard to occurring in the production that solves the fleet plough groove isolation structure under the less critical size, realize the lifting of technology node.
The lithographic method of the groove that technical scheme of the present invention provides, by HBr process so that photoresist by hardization, and removed the polymer film that forms when HBr processes, avoided described polymer film on the impact of subsequent etching groove, so that the pattern of the groove that forms is better.
The processing method of the photoresist that technical scheme of the present invention provides has not only realized hardization so that photoresist is processed by HBr, has also removed the polymer film that forms when HBr processes, and has avoided the impact on subsequent technique.
Description of drawings
Fig. 1 to Fig. 5 is the schematic diagram of making fleet plough groove isolation structure in the prior art;
Fig. 6 to Fig. 7 is existing a kind of schematic diagram that forms the isolated groove of isolation trench structure;
Fig. 8 to Figure 12 is the schematic diagram of the making fleet plough groove isolation structure that provides in the embodiments of the invention.
Embodiment
As stated in the Background Art, in general technique, the shape of the isolated groove of formation is not fine, sometimes also can form sharp-pointed groove angle at channel bottom.As in a kind of typical specific embodiment, to have the grid structure of flash memory of floating boom and the isolated groove of fleet plough groove isolation structure forms together by etching technics, with reference to shown in Figure 6, have pad oxide 202, polysilicon layer 203, silicon nitride layer 204, TEOS(tetraethoxysilane on the Semiconductor substrate 201) layer 205, bottom organic coating 206 and photoresist layer 207.Described isolated groove 4 be by photoresist layer 207 as mask, be etched in bottom organic coating 206, TEOS layer 205, silicon nitride layer 204, polysilicon layer 203, pad oxide 202 on the Semiconductor substrate 201, form until etch in the Semiconductor substrate 201.From top to bottom, the thickness of described photoresistance 207 is
The thickness of bottom organic coating 206 is
The thickness of TEOS layer 205 is
The thickness of silicon nitride layer 204 is
The thickness of polysilicon layer 203 is
The thickness of pad oxide 202 is
The degree of depth of described isolated groove 4 in Semiconductor substrate 201 is
Wherein as seen, form in the process of isolated groove 4 in etching, thickness only is
Photoresistance 207 need to be as the etching gross thickness
The mask of material layer.Photoresist loses in etching process seriously, even may also not finish in the situation of etching, and photoresist layer 207 is just incomplete, and this is so that the isolated groove shape that forms can be able to not satisfy the requirement of STI technique.Especially in photoetching process was carried out manufacturing process below 90nm, employed photoresist (as: ArF photoresist) was softer and thin, and the photoresist that needs reinforcement is so that photoresist becomes hard processing.General, utilize HBr to carry out the described photoresist that makes and become hard processing (HBr cure).And the inventor finds, after utilization HBr reinforced the processing of photoresist, the groove shape of formation still can not satisfy the requirement of STI technique, tapers off to a point in the bottom of isolated groove especially easily, as shown in Figure 7.And the tip of bottom causes electric leakage easily in the follow-up cavity that forms easily when carrying out the filling of isolated groove, so that the fleet plough groove isolation structure that forms can not be realized qualified isolation effect.
The inventor finds through research, it is described after HBr reinforces the processing of photoresist, surface at photoresist can form polymeric layer, described polymeric layer can not be etched away in follow-up etching, not only affect the carrying out of etching technics, so that the pattern of the isolated groove that forms is not good, the residue of described polymeric layer also can run up to the bottom of groove, so that the bottom of groove presents is skewed, consist of wedge angle with the sidewall of isolated groove, such problem shows obviously all the more along with the semiconductor technology critical size dwindles gradually.Thus, the inventor has proposed a kind of processing method of photoresist and has been based upon the lithographic method of the groove on the basis of processing method of described photoresist and a kind of manufacture craft of fleet plough groove isolation structure.In the manufacture method of the fleet plough groove isolation structure that technical scheme of the present invention provides, by HBr process so that photoresist by hardization, and removed the polymer film that forms when HBr processes, avoided described polymer film on the impact of subsequent etching groove, so that pattern is better in the isolated groove that forms, do not have angular generation, it is less or do not have to form the situation in cavity in the filling process of described silicon dioxide, reduce the situation of described fleet plough groove isolation structure electric leakage, can realize satisfactory isolation effect.And the etching of the HBr that provides in present embodiment processing, polymer film etching, isolated groove can both be indoor carrying out of plasma chamber, in technological operation, do not increase complexity, and only need to adopt the problem of original equipment with regard to occurring in the production that solves the fleet plough groove isolation structure under the less critical size, realize the lifting of technology node.
The lithographic method of the groove that technical scheme of the present invention provides, by HBr process so that photoresist by hardization, and removed the polymer film that forms when HBr processes, avoided described polymer film on the impact of subsequent etching groove, so that the pattern of the groove that forms is better.
The processing method of the photoresist that technical scheme of the present invention provides has not only realized hardization so that photoresist is processed by HBr, has also removed the polymer film that forms when HBr processes, and has avoided the impact on subsequent technique.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Embodiments of the invention provide a kind of manufacture craft of fleet plough groove isolation structure, and it comprises:
As shown in Figure 8, Semiconductor substrate 201 is provided, forms pad oxide 202 in Semiconductor substrate 201, form silicon nitride layer 204 at described pad oxide 202, form photoresist layer 207 at described silicon nitride layer 204, described photoresist layer also includes base coat 206 207 times;
Wherein, in a kind of performance, also be formed with polysilicon layer 203 between described pad oxide 202 and the described silicon nitride layer 204, described polysilicon layer 203 is the floating boom material layer of flash memory.
Also be formed with TEOS layer 205 between silicon nitride layer 204 and base coat 206, the effect of described TEOS layer 205 is the auxiliary mask layers as photoresist.
Wherein, described silicon nitride layer 204 is as the hard mask layer of subsequent etching.The effect of bottom organic coating 206 is the adhesivenesses that increase photoresist layer 207 and subsurface material layer.
In the present embodiment, the thickness of described photoresist layer 207 is
The thickness of bottom organic coating 206 is
The thickness of TEOS layer 205 is
The thickness of silicon nitride layer 204 is
The thickness of polysilicon layer 203 is
The thickness of pad oxide 202 is
The degree of depth of the isolated groove that forms in the subsequent technique in Semiconductor substrate 201 is
After exposure and the development, form the exposure figure of isolated grooves at described photoresist layer 207.
Then utilize described photoresist layer 207 as mask, described base coat 206 is carried out the first etching, so that the exposure figure of the described isolated groove in described photoresist layer 207 is transferred in the described base coat 206, form groove 11.Because the character of base coat 206 and photoresist layer 207 is similar, etching to base coat 206 must be carried out before photoresist is carried out hardization processing, the formation figure has not just carried out the hardization processing to photoresist before if base coat 206 is etched, meeting is so that described base coat 206 also can become hard, and the formation figure is difficult to be etched.
Described first etching of wherein, base coat 206 being carried out comprises the first main etching and the first over etching.The etching agent that adopts in described the first over etching is greater than the etching agent that adopts in the first main etching for the etching selection ratio of described base coat 206 and TEOS layer 205 for the etching selection ratio of the TEOS layer 205 of described base coat 206 and the described base coat 206 of next-door neighbour.This is because in whole semiconductor technology processing procedure, can be less than the etch rate at the sparse place of figure at graphics intensive place etch rate, can occur in the etching process to have proceeded to base coat 206 etchings at the sparse place of figure complete, but state the phenomenon that base coat 206 has not also been carved in the graphics intensive place.If the etching that continues to adopt the same etching can occur in the sparse place of figure can injure subsurface material layer (being TEOS layer 205 in this step), even base coat 206 etchings that might occur in the graphics intensive place are complete the time, and the subsurface material layer at the sparse place of figure has been etched away most of even has been etched away fully.The mode that adopts main etching and over etching to combine is carried out etching, can adopt main etching before base coat 206 etchings at the sparse place of figure are complete, then adopts over etching.Can reduce the loss to the sparse place of figure subsurface material layer.
Next, as shown in Figure 9, utilize HBr to process described photoresist, so that the hardness of described photoresist layer 207 and base coat 206 strengthens, become photoresist layer 207' and base coat 206', the trench wall in photoresist forms polymer film 300 simultaneously;
Concrete, the mode that described HBr processes is placed on the semiconductor structure among Fig. 8 in the plasma chamber, passes into HBr, wherein, the flow that the indoor HBr of described plasma chamber is set is 100sccm ~ 200sccm, and bias power is zero, pressure is 5mTorr ~ 30mTorr, and the time of carrying out is 5s ~ 15s.
Described HBr processes the hardness that can strengthen photoresist layer 207 and base coat 206, form photoresist layer 207' and base coat 206', so that photoresist more difficult being depleted of ratio script as the mask in the etching time, and can better stick to subsurface material layer (being TEOS layer 205 in the present embodiment), be not easy to come off or the situation such as photoresist alice, the figure that the etching that the photoresist after finally can guaranteeing to process with HBr carries out as mask forms keeps the shape.
But the inventor finds, after described HBr processes, can (surface of the surface of base coat 206' and TEOS layer 205 consists of) form the very thin polymeric layer 300 of one deck in the surface and groove 11 of photoresist layer 207'.Because the etching object of the etching agent in the follow-up etching technics is not polymeric layer 300, and described polymeric layer 300 also is difficult to be removed by general etching agent, so, described polymeric layer 300 can affect follow-up etching, and finally can deposit to isolated groove bottom and sidewall that subsequent etching forms.The isolated groove pattern that generally speaking, can cause subsequent etching to form is very poor, undesirable.
Next, as shown in figure 10, utilize highly corrosive agents to remove described polymer film 300;
As previously mentioned, polymer film among Fig. 9 is difficult to be removed by general etching agent, need to adopt the highly corrosive agents with severe corrosive to remove, generally speaking, need the very high corrosive agent of C-F group or S-F group content can realize removing described polymer film 300.In the present embodiment, described highly corrosive agents comprises SF
6Or CF
4In at least a.The described time of utilizing highly corrosive agents to remove described polymer film 300 is too short, can not realize the described polymer film 300 thorough effects of removing, and carry out overlong time, meeting also can affect the pattern of the groove of final etching formation so that described highly corrosive agents erodes to other material layer.Through inventor's many experiments and summary, the highly corrosive agents that obtains when employing is SF
6The time, its flow is 50 ~ 150sccm, and pressure is 5 ~ 30mTorr, and the time of carrying out is 5s ~ 15s; When the highly corrosive agents that adopts is CF
4, its flow is 50 ~ 200sccm, and pressure is 5 ~ 30mTorr, and the time of carrying out is 5s ~ 15s.
Remove described polymer film 300, namely eliminated the impact of described polymer film 300, and described photoresist also keeps the state larger than script hardness.The situation that photoresist is incomplete or come off neither can occur in the follow-up etching process, and also can not be aggregated thing film 300 affects etching, can carry out smoothly, and keep etching groove out to have good pattern.
Next, utilize photoresist to carry out etching as mask, in described Semiconductor substrate, form the groove figure of the smooth fleet plough groove isolation structure in bottom.
Ensuing etching mainly is divided into following steps and carries out:
As shown in figure 11, carry out the second etching: etching TEOS layer 205 and silicon nitride layer 204, the figure of groove 11 is transferred in TEOS layer 205 and the silicon nitride layer 204, form groove 12 in the material layer on polysilicon layer 203.The first etching of similar base coat 206, described the second etching comprises the second main etching and the second over etching.
Then, as shown in figure 12, carry out the 3rd etching: etch polysilicon layer 203 and pad oxide 202, the figure of groove 12 is transferred in polysilicon layer 203 and the pad oxide 202, form groove 13 in the material layer on Semiconductor substrate 201.The first etching of similar base coat 206, described the 3rd etching comprises the 3rd main etching and the 3rd over etching.
Then, continue as shown in figure 12, carry out the 4th etching: etching semiconductor substrate 201, the figure of groove 12 is transferred in the Semiconductor substrate, form isolated groove 14.
Forming good described isolated groove 14 has not had the accumulation of polymer film 300, and the etching technics that carries out previously is not subject to the impact of polymer film 300 yet, and the pattern sidewall up rightness of the groove of formation is good, and bottom flat, does not have wedge angle.
Can in described isolated groove 14, fill silicon dioxide to form complete fleet plough groove isolation structure (STI) in the subsequent technique.Because pattern is better in the described isolated groove 14, does not have angular generation, it is less or do not have to form the situation in cavity in the filling process of described silicon dioxide, has reduced the situation of described fleet plough groove isolation structure electric leakage, can realize satisfactory isolation effect.
And the first etching that provides in the present embodiment, HBr processing, polymer film etching, the second etching and the 3rd etching can both be indoor carrying out of plasma chamber, in technological operation, do not increase complexity, and only need to adopt the problem of original equipment with regard to occurring in the production that solves the fleet plough groove isolation structure under the less critical size, realize the lifting of technology node.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.
Although the present invention discloses as above with preferred embodiment, yet is not to limit the present invention.Any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (17)
1. the manufacture craft of a STI is characterized in that, comprising:
Semiconductor substrate is provided;
Form pad oxide in Semiconductor substrate;
Form silicon nitride layer at described pad oxide;
Form the photoresist with fleet plough groove isolation structure figure at described silicon nitride layer;
Utilize HBr to process described photoresist, to strengthen the hardness of described photoresist;
Utilization contains the described photoresist of caustic treatment of C-F group or S-F group, to remove the polymer film that is formed on the photoresist surface in the described HBr processing procedure;
Utilize photoresist to carry out etching as mask, in described Semiconductor substrate, form the groove figure of the smooth fleet plough groove isolation structure in bottom.
2. the manufacture craft of STI as claimed in claim 1 is characterized in that, described photoresist comprises the ArF photoresist.
3. the manufacture craft of STI as claimed in claim 1 is characterized in that, the corrosive agent of the described C-F of containing group or S-F group comprises SF
6Or CF
4In at least a.
4. the manufacture craft of STI as claimed in claim 3 is characterized in that, described utilization contains the technique of the described photoresist of caustic treatment of C-F group or S-F group and carries out in that plasma chamber is indoor; The corrosive agent that adopts is SF
6The time, SF is set
6Flow be 50sccm ~ 150sccm, the indoor pressure of plasma chamber is 5mTorr ~ 30mTorr, the time of carrying out is 5s ~ 15s; The corrosive agent that adopts is CF
4The time, CF is set
4Flow be 50sccm ~ 200sccm, the indoor pressure of plasma chamber is 5mTorr ~ 30mTorr, the time of carrying out is 5s ~ 15s.
5. the manufacture craft of STI as claimed in claim 1, it is characterized in that, the technique that the described HBr of utilization processes described photoresist is carried out in that plasma chamber is indoor, the flow that the indoor HBr of described plasma chamber is set is 100sccm ~ 200sccm, bias power is zero, pressure is 5mTorr ~ 30mTorr, and the time of carrying out is 5s ~ 15s.
6. the manufacture craft of STI as claimed in claim 1 is characterized in that, also comprises base coat between described photoresist and the silicon nitride layer; After described silicon nitride layer forms the step of the photoresist with fleet plough groove isolation structure figure, utilizing before HBr processes described photoresist, the photoresist that also comprises having the fleet plough groove isolation structure figure is mask, described base coat is carried out the step of etching.
7. the manufacture craft of STI as claimed in claim 6, it is characterized in that, described etching to base coat comprises main etching and two steps of over etching, in the described over etching used etching agent to the etching selection ratio of base coat and base coat next-door neighbour's layer dielectric less than the etching selection ratio of the used etching agent in the described main etching to base coat and base coat next-door neighbour's layer dielectric.
8. the lithographic method of a groove is characterized in that, comprising:
Semiconductor substrate is provided;
Utilize photoetching process to form the photoresist with groove figure in described Semiconductor substrate;
Utilize HBr to process described photoresist, to strengthen the hardness of described photoresist;
Utilization contains the described photoresist of caustic treatment of C-F group or S-F group, to remove the polymer film that is formed on the photoresist surface in the described HBr processing procedure;
Utilize photoresist to carry out etching as mask, in described Semiconductor substrate, form groove.
9. lithographic method as claimed in claim 8 is characterized in that, described photoresist comprises the ArF photoresist.
10. lithographic method as claimed in claim 8 is characterized in that, the corrosive agent of the described C-F of containing group or S-F group comprises SF
6Or CF
4In at least a.
11. lithographic method as claimed in claim 10 is characterized in that, described utilization contains the technique of the described photoresist of caustic treatment of C-F group or S-F group and carries out in that plasma chamber is indoor; The corrosive agent that adopts is SF
6The time, SF is set
6Flow be 50sccm ~ 150sccm, the indoor pressure of plasma chamber is 5mTorr ~ 30mTorr, the time of carrying out is 5s ~ 15s; The corrosive agent that adopts is CF
4The time, CF is set
4Flow be 50sccm ~ 200sccm, the indoor pressure of plasma chamber is 5mTorr ~ 30mTorr, the time of carrying out is 5s ~ 15s.
12. lithographic method as claimed in claim 8, it is characterized in that, the technique that the described HBr of utilization processes described photoresist is carried out in that plasma chamber is indoor, the flow that the indoor HBr of described plasma chamber is set is 100sccm ~ 200sccm, bias power is zero, pressure is 5mTorr ~ 30mTorr, and the time of carrying out is 5s ~ 15s.
13. the processing method of a photoresist is characterized in that, comprising:
Utilize photoetching process treating that graphical substrate forms photoetching offset plate figure;
Utilize HBr to process described photoresist, to strengthen the hardness of described photoresist;
Utilization contains the described photoresist of caustic treatment of C-F group or S-F group, to remove the polymer film that is formed on the photoresist surface in the described HBr processing procedure.
14. the processing method of photoresist as claimed in claim 13 is characterized in that, described photoresist comprises the ArF photoresist.
15. the processing method of photoresist as claimed in claim 13 is characterized in that, the corrosive agent of the described C-F of containing group or S-F group comprises SF
6Or CF
4In at least a.
16. the processing method of photoresist as claimed in claim 15 is characterized in that, described utilization contains the technique of the described photoresist of caustic treatment of C-F group or S-F group and carries out in that plasma chamber is indoor; The employing corrosive agent is SF
6The time, SF is set
6Flow be 50sccm～150sccm, the indoor pressure of plasma chamber is 5mTorr ~ 30mTorr, the time of carrying out is 5s ~ 15s; The employing corrosive agent is CF
4The time, CF is set
4Flow be 50sccm ~ 200sccm, the indoor pressure of plasma chamber is 5mTorr ~ 30mTorr, the time of carrying out is 5s ~ 15s.
17. the processing method of photoresist as claimed in claim 13, it is characterized in that, the technique that the described HBr of utilization processes described photoresist is carried out in that plasma chamber is indoor, the flow that the indoor HBr of described plasma chamber is set is 100sccm ~ 200sccm, bias power is zero, pressure is 5mTorr ~ 30mTorr, and the time of carrying out is 5s ~ 15s.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104752160A (en) * | 2013-12-31 | 2015-07-01 | 苏州同冠微电子有限公司 | Method for etching groove through common polycrystal etching device |
| CN110911344A (en) * | 2018-09-14 | 2020-03-24 | 长鑫存储技术有限公司 | Semiconductor substrate shallow groove manufacturing method and semiconductor substrate shallow groove structure |
| CN111933525A (en) * | 2020-09-22 | 2020-11-13 | 南京晶驱集成电路有限公司 | Etching method |
| CN116598254A (en) * | 2023-07-19 | 2023-08-15 | 粤芯半导体技术股份有限公司 | Method for forming deep trench isolation structure |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104752160A (en) * | 2013-12-31 | 2015-07-01 | 苏州同冠微电子有限公司 | Method for etching groove through common polycrystal etching device |
| CN110911344A (en) * | 2018-09-14 | 2020-03-24 | 长鑫存储技术有限公司 | Semiconductor substrate shallow groove manufacturing method and semiconductor substrate shallow groove structure |
| CN110911344B (en) * | 2018-09-14 | 2023-09-05 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor substrate shallow trench and semiconductor substrate shallow trench structure |
| CN111933525A (en) * | 2020-09-22 | 2020-11-13 | 南京晶驱集成电路有限公司 | Etching method |
| CN116598254A (en) * | 2023-07-19 | 2023-08-15 | 粤芯半导体技术股份有限公司 | Method for forming deep trench isolation structure |
| CN116598254B (en) * | 2023-07-19 | 2023-09-29 | 粤芯半导体技术股份有限公司 | Method for forming deep trench isolation structure |
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