CN110911344A - Semiconductor substrate shallow groove manufacturing method and semiconductor substrate shallow groove structure - Google Patents
Semiconductor substrate shallow groove manufacturing method and semiconductor substrate shallow groove structure Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 200
- 239000004065 semiconductor Substances 0.000 title claims abstract description 199
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 277
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- 238000000034 method Methods 0.000 claims abstract description 53
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 20
- 239000000460 chlorine Substances 0.000 claims description 20
- 239000001301 oxygen Substances 0.000 claims description 20
- 229910052760 oxygen Inorganic materials 0.000 claims description 20
- 239000012495 reaction gas Substances 0.000 claims description 20
- 229910052786 argon Inorganic materials 0.000 claims description 14
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 12
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 10
- 229910052801 chlorine Inorganic materials 0.000 claims description 10
- 239000001307 helium Substances 0.000 claims description 8
- 229910052734 helium Inorganic materials 0.000 claims description 8
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 8
- 239000007789 gas Substances 0.000 description 14
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000000376 reactant Substances 0.000 description 8
- 238000002955 isolation Methods 0.000 description 7
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- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
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- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
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- 230000004048 modification Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000000047 product Substances 0.000 description 2
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- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
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- 229910052905 tridymite Inorganic materials 0.000 description 2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract
The application relates to the field of semiconductor device manufacturing, and discloses a semiconductor substrate shallow trench manufacturing method and a structure, wherein the method comprises the following steps: 1) providing a semiconductor substrate, wherein a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the shape and the position of a shallow groove are defined by the first etching window; 2) performing a main etching step of cyclic etching, including performing deep etching on the semiconductor substrate through the first etching window to form a trench structure in the semiconductor substrate and a bottom etching byproduct at the bottom of the trench structure; 3) a bottom breakthrough step of cyclic etching comprising removing the bottom etch by-product; 4) performing a groove wall protection step of circular etching, wherein a side wall oxide layer is formed on the side wall of the groove structure; 5) and circularly executing the step 2) to the step 4) until the depth of the groove structure reaches a preset depth so as to form the shallow groove in the semiconductor substrate.
Description
Technical Field
The present disclosure relates to the field of semiconductor device manufacturing, and more particularly, to a method for manufacturing a semiconductor substrate shallow trench and a semiconductor substrate shallow trench structure.
Background
Semiconductor integrated circuits typically include active regions and isolation regions between the active regions, which are formed prior to fabrication of the active devices. As semiconductor processes enter the deep submicron era, active region Isolation layers of semiconductor devices have been mostly fabricated by using a Shallow Trench Isolation (STI) process.
With the evolution and progress of semiconductor technology nodes and semiconductor manufacturing machines, the density of devices on a silicon wafer is continuously increased, the critical dimension is continuously reduced, and in order to ensure a better isolation effect, a deeper shallow trench needs to be manufactured, so that the depth-to-width ratio of the shallow trench is improved. Referring to fig. 1A, 1B and 1C, since increasing the depth of the shallow trench requires a long etching time, the continuously output bias power may cause a flaring phenomenon of the opening of the shallow trench and may decrease the etching selection ratio; the etching byproducts are deposited at the bottom and the opening of the shallow trench, so that the etching is finished in advance, and the depth of the shallow trench cannot reach the target etching depth; due to the relationship of graphic design, the critical dimension of the shallow trench opening is different, and the depth uniformity of the shallow trench formed by etching is inconsistent due to the micro-load effect.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor substrate shallow groove and a semiconductor substrate shallow groove structure.
In order to achieve the above object, in a first aspect of the present application, there is provided a semiconductor substrate shallow trench fabrication method, including: 1) providing a semiconductor substrate, wherein a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the shape and the position of a shallow groove are defined by the first etching window; 2) performing a main etching step of cyclic etching, including performing deep etching on the semiconductor substrate through the first etching window to form a trench structure in the semiconductor substrate and a bottom etching byproduct at the bottom of the trench structure; 3) a bottom breakthrough step of cyclic etching comprising removing the bottom etch by-product; 4) performing a groove wall protection step of circular etching, wherein a side wall oxide layer is formed on the side wall of the groove structure; 5) and circularly executing the step 2) to the step 4) until the depth of the groove structure reaches a preset depth so as to form the shallow groove in the semiconductor substrate.
Optionally, in step 1), a surface protection layer is further formed on the semiconductor substrate, the surface protection layer is located between the mask layer and the semiconductor substrate, and the surface protection layer has a second etching window corresponding to the first etching window.
Optionally, in step 2), a surface etching byproduct is formed on the surface of the mask layer while the semiconductor substrate is deeply etched; and 3) removing the surface etching by-products on the surface of the mask layer while removing the bottom etching by-products.
Optionally, in the step 2), a pulse bias power output mode is adopted to carry out deep etching on the semiconductor substrate.
Optionally, in step 2), the duty ratio of the pulsed bias power output is between 10% and 60%.
Optionally, in the step 2), deep etching is performed on the semiconductor substrate in a low-frequency pulse type bias power output mode, the 13mHz source power of the reaction instrument used in the step 2) is 2000W-3000W, and the 2mHz pulse type bias power is 500W-1500W.
Optionally, the bottom etching by-products are removed in step 3) by using a pulsed bias power output mode.
Optionally, the 13mHz source power of the reaction apparatus used in step 3) is 500W-1500W, and the 13mHz pulsed bias power is 100-1000W.
Optionally, in step 3), the duty ratio of the pulsed bias power output is between 10% and 60%.
Optionally, the reaction gas introduced for performing the deep etching on the semiconductor substrate in the step 2) includes chlorine (Cl)2) Oxygen (O)2) And helium (He).
Optionally, the reaction gas introduced for removing the bottom etching by-product in step 3) includes carbon tetrafluoride (CF)4) And argon (Ar).
Optionally, the step 4) is formed on the side wall of the trench structureThe reaction gas introduced into the side wall oxide layer comprises oxygen (O)2) And argon (Ar).
Optionally, the 13mHz source power of the reaction instrument used in the step 4) is 2000-3000W.
Optionally, the number of execution times of step 5) is between 4 and 19.
Optionally, when the shallow trench is formed in the semiconductor substrate, the reaction apparatus used in the steps 2) to 5) is the same reaction apparatus.
Optionally, the shallow trenches include a first shallow trench and a second shallow trench, a width ratio of the second shallow trench to the first shallow trench is between 2 and 7, and a depth ratio of the second shallow trench to the first shallow trench is between 0.7 and 1.3.
In a second aspect, the present application provides a method for manufacturing a shallow trench in a semiconductor substrate, including: 1) providing a semiconductor substrate, wherein a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the shape and the position of a shallow groove are defined by the first etching window; 2) performing a first main etching step, including performing deep etching on the semiconductor substrate through the first etching window to form a trench structure in the semiconductor substrate and a bottom etching byproduct at the bottom of the trench structure; 3) performing a bottom breakthrough step comprising removing the bottom etch byproducts; 4) performing a trench wall protection step, including forming a sidewall oxide layer on the sidewall of the trench structure to form the shallow trench in the semiconductor substrate; 5) and performing a second main etching step, including performing deep etching on the semiconductor substrate through the first etching window.
Optionally, in step 1), a surface protection layer is further formed on the semiconductor substrate, the surface protection layer is located between the mask layer and the semiconductor substrate, and the surface protection layer has a second etching window corresponding to the first etching window.
Optionally, in step 2) and step 5), a surface etching byproduct is formed on the surface of the mask layer while the semiconductor substrate is deeply etched; and 3) removing the surface etching by-products on the surface of the mask layer while removing the bottom etching by-products.
Optionally, in step 2) and step 5), performing deep etching on the semiconductor substrate in a pulsed bias power output mode.
Optionally, in step 2) and step 5), the duty ratio of the pulsed bias power output is between 10% and 60%.
Optionally, deep etching is performed on the semiconductor substrate in the step 2) and the step 5) by adopting a low-frequency pulse type bias power output mode, the 13mHz source power of the reaction instrument used in the step 2) is 2000W-3000W, and the 2mHz pulse type bias power is 500W-1500W.
Optionally, the bottom etching by-products are removed in step 3) by using a pulsed bias power output mode.
Optionally, the 13mHz source power of the reaction apparatus used in step 3) is 500W-1500W, and the 13mHz pulsed bias power is 100-1000W.
Optionally, in step 3), the duty ratio of the pulsed bias power output is between 10% and 60%.
Optionally, the reaction gas introduced for performing the deep etching on the semiconductor substrate in the step 2) and the step 5) comprises chlorine (Cl)2) Oxygen (O)2) And helium (He).
Optionally, the reaction gas introduced for removing the bottom etching by-product (111) in the step 3) comprises carbon tetrafluoride (CF)4) And argon (Ar).
Optionally, the reaction gas introduced to form the sidewall oxide layer on the sidewall of the trench structure in step 4) includes oxygen (O)2) And argon (Ar).
Optionally, the 13mHz source power of the reaction instrument used in the step 4) is 2000-3000W.
Optionally, when the shallow trench is formed in the semiconductor substrate, the reaction apparatus used in the step 2) to the step 5) is the same reaction apparatus.
A third aspect of the present application provides a semiconductor substrate shallow trench structure, comprising: the semiconductor substrate comprises a first shallow trench and a second shallow trench which are formed in the semiconductor substrate, the width ratio of the second shallow trench to the first shallow trench is 2-7, and the depth ratio of the second shallow trench to the first shallow trench is 0.7-1.3.
Optionally, a surface protection layer is further formed on the semiconductor substrate, and the surface protection layer is located between the mask layer and the semiconductor substrate.
The method for manufacturing the shallow trench of the semiconductor substrate comprises three steps of main etching, bottom penetration and trench wall protection, wherein the steps are carried out in a circulating mode, and by means of a low-frequency pulse type bias power output mode, a low duty ratio and a mode of forming a sidewall oxide layer on a trench wall, flaring is relieved in the etching process, byproducts at the bottom and an opening of the shallow trench are effectively removed, the problem of etching termination is avoided, the depth of the trench is guaranteed to reach a target etching depth, the depth-to-width ratio of the shallow trench is improved, and the depth uniformity of the shallow.
Additional features and advantages of the present application will be described in detail in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not to limit the application. In the drawings:
FIGS. 1A-1C are schematic views of shallow trench structures fabricated according to the prior art;
FIG. 2 is a flow chart of a method for fabricating a shallow trench in a semiconductor substrate according to one embodiment of the present application;
FIG. 3 is a schematic view of a semiconductor substrate fabricated by a method for fabricating shallow trenches in a semiconductor substrate according to one embodiment of the present application;
FIG. 4 is a schematic view of another semiconductor substrate fabricated by a method for fabricating shallow trenches in a semiconductor substrate according to one embodiment of the present application;
FIG. 5 is a schematic diagram illustrating a main etching step in a cyclic etching step in a method for fabricating a shallow trench in a semiconductor substrate according to an embodiment of the present application;
FIGS. 6A and 6B are experimental results of a main shallow trench etching step using a continuous bias power output mode and a pulsed bias power output mode;
FIG. 7A is a schematic diagram of the duty cycle of the pulsed bias power output;
FIG. 7B is an experimental result of using different duty cycles of pulsed bias power output for the shallow trench main etch step;
FIG. 8A is a schematic diagram of ion energy distribution at 13.56mHz and 2 mHz;
FIG. 8B is the experimental results of using the 2mHz bias power output mode and the 13mHz bias power output mode for the main shallow trench etching step;
FIG. 9 is a schematic view of a bottom-piercing step in a cyclic etching step in a method for fabricating a shallow trench in a semiconductor substrate according to an embodiment of the present application;
FIG. 10 is a schematic view of a trench wall protection step in a cyclic etching step in a method for fabricating a shallow trench in a semiconductor substrate according to an embodiment of the present application;
fig. 11 is a schematic view of shallow trenches formed by performing steps 2) to 4) in a cycle in the method for fabricating shallow trenches in a semiconductor substrate according to one embodiment of the present application;
FIG. 12 is a schematic illustration of a shallow trench formed by a method of fabricating a shallow trench in a semiconductor substrate according to one embodiment of the present application;
FIG. 13 is a flow chart of a method for fabricating a shallow trench in a semiconductor substrate according to another embodiment of the present application;
FIG. 14 is a schematic view of a semiconductor substrate fabricated by a method for fabricating shallow trench isolation in a semiconductor substrate according to another embodiment of the present application;
FIG. 15 is a schematic view of another semiconductor substrate fabricated by a method for fabricating shallow trench isolation in a semiconductor substrate according to another embodiment of the present application;
FIG. 16 is a schematic diagram illustrating a main etching step in a method for fabricating a shallow trench in a semiconductor substrate according to another embodiment of the present application;
FIG. 17 is a schematic view of a bottom-piercing step in a method for fabricating a shallow trench in a semiconductor substrate according to another embodiment of the present application;
FIG. 18 is a schematic view of a trench wall protection step in a shallow trench isolation process for a semiconductor substrate according to another embodiment of the present application;
fig. 19 is a schematic view of a shallow trench formed by a method for forming a shallow trench in a semiconductor substrate according to another embodiment of the present application.
Description of the reference numerals
100 semiconductor substrate 110 trench structure
111 bottom etch by-product 112 sidewall oxide layer
120 shallow trench 121 first shallow trench
122 second shallow trench 200 mask layer
210 first etch window 220 surface etch byproducts
300 surface protection layer 310 second etch window
Detailed Description
The following detailed description of embodiments of the present application will be made with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present application, are given by way of illustration and explanation only, and are not intended to limit the present application.
In this application, the use of directional words such as "above/over, below/under, left/left, right/right" generally means up, down, left, right with reference to the drawings, unless stated to the contrary. "inner and outer" refer to the inner and outer contours of the respective component itself.
In the drawings, the shapes shown may be modified depending on manufacturing processes and/or tolerances. Accordingly, the exemplary embodiments of the present application are not limited to the specific shapes illustrated in the drawings, and may include shape changes caused during a manufacturing process. Furthermore, the different elements and regions in the drawings are only schematically shown, so that the application is not limited to the relative dimensions or distances shown in the drawings.
As shown in fig. 2, the present application provides a method for fabricating a shallow trench in a semiconductor substrate, comprising the following steps:
1) providing a semiconductor substrate, wherein a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the shape and the position of a shallow groove are defined by the first etching window;
2) performing a main etching step of cyclic etching, including performing deep etching on the semiconductor substrate through the first etching window to form a trench structure in the semiconductor substrate and a bottom etching byproduct at the bottom of the trench structure;
3) a bottom breakthrough step of cyclic etching comprising removing the bottom etch by-product;
4) performing a groove wall protection step of circular etching, wherein a side wall oxide layer is formed on the side wall of the groove structure;
5) and circularly executing the step 2) to the step 4) until the depth of the groove structure reaches a preset depth so as to form the shallow groove in the semiconductor substrate.
The method for fabricating the shallow trench in the semiconductor substrate provided by the present application will be described in detail below with reference to the accompanying drawings.
Firstly, step 1) is performed, a semiconductor substrate 100 is provided, a mask layer 200 is formed on the semiconductor substrate 100, the mask layer 200 has a first etching window 210, and the first etching window 210 defines the shape and the position of the shallow trench 120, as shown in fig. 3.
Specifically, a semiconductor substrate 100 is first provided, and the material of the semiconductor substrate 100 includes, but is not limited to, a single crystal or polycrystalline semiconductor material, and may be an intrinsic single crystal silicon substrate or a lightly doped silicon substrate, and further may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.
A mask layer 200 is formed on the semiconductor substrate 100, and the material of the mask layer 200 includes, but is not limited to, silicon nitride, silicon oxide, and carbon, which have a high selectivity with respect to other materials of the semiconductor substrate 100. The mask layer 200 has a first etch window 210, and the first etch window 210 may define the shape and location of the shallow trench 120.
Optionally, in step 1), a surface protection layer 300 is further formed on the semiconductor substrate 100, the surface protection layer 300 is located between the mask layer 200 and the semiconductor substrate 100, and the surface protection layer 300 has a second etching window 310 corresponding to the first etching window 210, as shown in fig. 4.
Specifically, a surface protection layer 300 is further formed between the mask layer 200 and the semiconductor substrate 100 for protecting the surface of the semiconductor substrate 100, and the material of the surface protection layer 300 includes, but is not limited to, silicon nitride, silicon oxide, carbon, and other materials having a high selectivity ratio with the materials of the semiconductor substrate 100 and the mask layer 200. The surface protection layer 300 has a second etch window 310 coinciding with the first etch window 210.
Next, step 2) of performing a main etching step of performing a cyclic etching, including performing a deep etching on the semiconductor substrate 100 through the first etching window 210, so as to form a trench structure 110 in the semiconductor substrate 100 and a bottom etching byproduct 111 at the bottom of the trench structure 110, as shown in fig. 5.
Specifically, the semiconductor substrate 100 is etched back downward through the first etching window 210, and the trench structure 110 is formed in the semiconductor substrate 100, and during the etching back, non-volatile or difficult-to-remove etching byproducts are generated and accumulated at the bottom of the trench structure 110 and the surface of the mask layer 200.
Optionally, in step 2), the semiconductor substrate 100 is deeply etched in a pulsed bias power output mode.
Specifically, referring to fig. 6A, in fig. 6A, the X-axis direction is the etching time, the Y-axis direction is the depth of the shallow trench, the triangle is marked as the continuous bias power output mode, and the circle is marked as the pulsed bias power output mode. It can be found from the experimental results that with increasing time, the shallow trench depth does not increase rapidly any more after the 4 th moment of the etching time using the continuous bias power output mode, indicating that the etching has terminated. And the use of the pulsed bias power output mode, the etching time is continuously increased from the shallow trench depth from the 1 st to the 6 th, which shows that the use of the pulsed bias power output mode can improve the etching termination.
Referring to fig. 6B, it can be seen from the experimental results that the load of the shallow trench depth continuously increases with the increase of time by using the continuous bias power output mode, which indicates that the non-uniformity of the depth continuously deteriorates, and the load of the shallow trench depth exceeds 6 units when the etching time reaches the 6 th time point in fig. 6B. And by using a pulse bias power output mode, the depth load of the shallow trench is obviously increased and is not obvious, and when the etching time reaches the 6 th moment, the depth load is about 2 units, so that the shallow trench depth load is obviously improved. Therefore, according to the experimental result, the pulse type bias power output mode is selected in the shallow trench main etching step.
Because the shallow trench 120 needs to be etched for a long time due to the increase of the aspect ratio, if the bias power is continuously output, the selection ratio of the mask layer 200 to silicon is insufficient, and the mask layer 200 is etched while the semiconductor substrate 100 is etched, thereby causing a flaring phenomenon. In the embodiment of the present application, a pulse bias power output mode may be further adopted to improve the flaring phenomenon, and the pulse bias power output mode may rapidly switch the bias power between the output mode and the close mode at a certain frequency, so that in the close mode, the consumption of the mask layer 200 may be reduced, the flaring phenomenon may be improved, and the selection ratio of the mask layer 200 to silicon may be increased.
Optionally, in step 2), the duty ratio of the pulsed bias power output is between 10% and 60%.
Specifically, referring to fig. 7A, the duty ratio refers to the proportion of the time that the bias power is in the output mode relative to the total time in one pulse cycle, and the whole etching process is composed of a plurality of pulse cycles. The duty ratio is larger as the output mode is longer, and the duty ratio is smaller as the output mode is shorter. If the bias power is always output, the duty ratio is 100%, and it is regarded as continuous bias power output. Referring to fig. 7B, the duty ratio of the pulsed bias power output is shown in the X-axis direction, and the depth load is shown in the Y-axis direction. From the experimental results, it can be found that the smaller the duty ratio, the better the depth load can be obtained, and thus the effect of improving the depth load can be achieved by optimizing the duty ratio. According to the technical scheme of the application, the etching depth uniformity of the shallow trench 120 can be improved by adjusting the duty ratio, wherein the smaller the duty ratio is, the better the etching depth uniformity of the shallow trench 120 is. Preferably, in the embodiment of the present application, the duty cycle of the pulsed bias power output is between 10% and 60%.
Optionally, in the step 2), the semiconductor substrate 100 is deeply etched in a low-frequency pulse bias power output mode, the 13mHz source power of the reaction instrument used in the step 2) is 2000W-3000W, and the 2mHz pulse bias power is 500W-1500W.
Specifically, referring to fig. 8A, the X-axis direction is the ion energy, and the Y-axis direction is the ion energy distribution, it is obvious that most of the ion energy is greater than 1000eV at low frequency (2mHz), and most of the ion energy is lower than 500eV at high frequency (13.56 mHz). Referring to FIG. 8B, the X-axis direction is 2mHz and 13mHz, the main Y-axis direction (left) is the depth of the shallow trench, and the sub Y-axis direction (right) is the bottom width of the shallow trench. From the experimental results, it can be found that under the same etching time, the depth of the shallow trench can be deeper by 2mHz, the depth of the shallow trench corresponding to 2mHz is about 2.5 units, and the depth of the shallow trench corresponding to 13mHz is about 2.2 units. Under the same etching time, 2mHz can obtain larger bottom width, the bottom width corresponding to 2mHz is about 12 units, and the bottom width corresponding to 13mHz is about 6 units. Experimental results prove that the lower frequency has higher ion energy, and the ions can reach deeper shallow trench etching silicon substrates. Therefore, according to the experimental result, the shallow trench main etching step selects a low-frequency bias power output mode. Preferably, a 2mHz pulse bias power output mode can be adopted, the bias power is between 500W and 1500W, the cavity temperature of a reaction instrument used in the deepening etching is between 50 ℃ and 80 ℃, the temperature of the electrostatic chuck is between 20 ℃ and 70 ℃, the cavity pressure is between 5mT and 30mT, and the source power of 13mHz is between 2000W and 3000W.
Optionally, the reaction gas introduced for performing the deep etching on the semiconductor substrate 100 in step 2) includes chlorine (Cl)2) Oxygen (O)2) And helium (He).
In particular, the present inventionIn the embodiment, the reaction gas introduced during the deep etching includes chlorine (Cl)2) Oxygen (O)2) And helium (He), in which chlorine (Cl) gas2) Which is the main etching gas, reacts with the semiconductor substrate 100 and the resulting product is carried away by the gas in the reaction apparatus.
Continuing with step 3), a bottom-piercing step of a cyclical etch is performed, including removing the bottom etch byproducts 111, as shown in FIG. 9.
Specifically, when the semiconductor substrate 100 is deeply etched, a bottom etching byproduct 111 is generated at the bottom of the trench structure 110, and due to the reduction of the critical dimension, the bottom etching byproduct 111 is not easily discharged, which affects the etching rate, and as the etching time increases, a large amount of the bottom etching byproduct 111 accumulates, and the etching reactant cannot contact with the bottom of the trench structure 110, so that the etching is ended in advance, and the trench structure 110 cannot reach the target etching depth. Therefore, after performing the etch-back, the bottom etch byproducts 111 need to be removed to ensure that the reactants can contact the bottom of the trench structure 110, and to ensure the etch rate and the etch depth of the trench structure 110.
Optionally, the bottom etching by-products 111 are removed in step 3) by using a pulsed bias power output mode.
Specifically, the pulse bias power output mode can rapidly switch the bias power between the output mode and the off mode at a certain frequency, and the off mode does not generate the bottom etching by-product 111, thereby facilitating the discharge of the bottom etching by-product 111, avoiding the termination of etching, improving the etching rate and ensuring the etching depth.
Optionally, in step 2), while performing deep etching on the semiconductor substrate 100, a surface etching byproduct 220 is formed on the surface of the mask layer 200; removing the bottom etching by-products 111 and simultaneously removing the surface etching by-products 220 on the surface of the mask layer 200 in step 3), as shown in fig. 5 and 9.
Specifically, during the deep etching process, when the bottom etching by-product 111 is discharged from the bottom of the trench structure 110, a part of the bottom etching by-product 111 may accumulate on the surface of the mask layer 200 to form a surface etching by-product 220, for the trench structure 110 with a small critical dimension, a reactant for etching the semiconductor substrate 100 is not easy to enter from the opening of the trench structure 110, which may cause a decrease in etching rate, and as the etching time increases, a large amount of accumulated surface etching by-product 220 may block the opening of the trench structure 110 to stop etching, while for the trench structure 110 with a large critical dimension, the influence of the surface etching by-product 220 on the etching depth is small, and the reactant for etching the semiconductor substrate 100 may enter the trench structure 110, which may cause poor uniformity of the etching depth. Thus, the bottom etch byproducts 111 are removed along with the surface etch byproducts 220 on the surface of the mask layer 200. The etching termination can be avoided, the etching rate is further improved, the etching depth is ensured, and the uniformity of the etching depth is improved.
Optionally, the temperature of the cavity of the reaction instrument used in step 3) is 50-80 ℃, the temperature of the electrostatic chuck is 20-70 ℃, the pressure of the cavity is 5-30 mT, the source power of 13mHz is 500-1500W, and the pulsed bias power of 13mHz is 100-1000W.
Optionally, in step 3), the duty ratio of the pulsed bias power output is between 10% and 60%.
Specifically, the uniformity of the etching depth of the shallow trench 120 can be improved by adjusting the duty ratio. The smaller the duty cycle, the better the uniformity of the etch depth of the shallow trench 120. Preferably, the duty cycle of the pulsed bias power output is between 10% and 60%.
Optionally, the reaction gas introduced for removing the bottom etching by-products 111 in step 3) includes carbon tetrafluoride (CF)4) And argon (Ar).
Specifically, the fluorine-based gas can easily remove the bottom etch by-products 111 and be carried out by the gas in the reaction apparatus.
Continuing to execute step 4), performing a trench wall protection step of circular etching, including forming a sidewall oxide layer 112 on the sidewall of the trench structure 110, as shown in fig. 10.
In particular, the sidewall oxide layer 112 can protect the sidewalls of the trench structure 110, improving the flaring phenomenon during the main etching step of the cyclic etching.
Optionally, the reaction gas introduced to form the sidewall oxide layer 112 on the sidewall of the trench structure 110 in step 4) includes oxygen (O)2) And argon (Ar).
Specifically, in forming the sidewall oxide layer 112, the gas introduced into the reaction apparatus includes oxygen (O)2) And argon (Ar), oxygen (O)2) The following reaction occurs with the sidewalls of the trench structure 110:
Si(s)+O2(g)→SiO2(s)
silicon dioxide (SiO)2) The sidewall oxide layer 112 is formed on the sidewall of the trench structure 110 to protect the sidewall of the trench structure 110, improve the flaring during the main etching step of the circular etching, and adjust the introduction of oxygen (O)2) The amount of the adjustment adjusts the angle of the sidewalls of the trench structure 110.
Optionally, the temperature of the cavity of the reaction instrument used in the step 4) is 50-80 ℃, the temperature of the electrostatic chuck is 20-70 ℃, the pressure of the cavity is 5-30 mT, and the power of the 13mHz source is 2000-3000W.
In step 5), step 2) to step 4) are performed in a loop until the depth of the trench structure 110 reaches a predetermined depth, so as to form the shallow trench 120 in the semiconductor substrate 100, as shown in fig. 11.
Specifically, in order to simultaneously improve the flaring of the shallow trench 120 caused by insufficient protection of the sidewall of the shallow trench 120, and the etching termination and the depth non-uniformity of the shallow trench 120 caused by the deposition of the bottom etching byproduct 111, it is required to control the etching and the trench wall protection more precisely, and as the critical dimension is reduced, the single-step etching has reached the limit of controlling the shallow trench 120. The etching step is divided into three steps of main etching, bottom penetration and groove wall protection, so that the shallow trench 120 can be controlled more accurately, the flaring phenomenon is improved, the depth of the shallow trench 120 reaches the target etching depth, and the uniformity of the depth of the shallow trench 120 is improved.
Optionally, the number of execution times of step 5) is between 4 and 19.
Specifically, the three steps of main etching, bottom penetration and groove wall protection are circularly performed for 4-19 times, the depth of the groove structure 110 can reach the target depth, the shallow groove 120 is formed, and the depth uniformity of the shallow groove 120 is good.
Optionally, when the shallow trench 120 is formed in the semiconductor substrate 100, the reaction apparatus used in the steps 2) to 5) is the same reaction apparatus.
Specifically, the same reaction instrument is used in the three steps of main etching, bottom penetration and groove wall protection, and the shallow groove 120 with good depth uniformity and proper angle and reaching the target etching depth can be etched in a short time by changing the working parameters of the reaction instrument and the gas introduced into the reaction instrument and switching between different steps.
Optionally, the shallow trenches 120 include a first shallow trench 121 and a second shallow trench 122, a width ratio of the second shallow trench 122 to the first shallow trench 121 is between 2 and 7, and a depth ratio of the second shallow trench 122 to the first shallow trench 121 is between 0.7 and 1.3.
Specifically, the shallow trenches 120 with different widths can be manufactured by the method for manufacturing the semiconductor substrate shallow trenches provided by the present application, wherein the shallow trenches 120 include a first shallow trench 121 and a second shallow trench 122, a width ratio of the second shallow trench 122 to the first shallow trench 121 is between 2 and 7, and a depth ratio of the second shallow trench 122 to the first shallow trench 121 is between 0.7 and 1.3, as shown in fig. 12.
As shown in fig. 13, the present application further provides another method for manufacturing a shallow trench in a semiconductor substrate, which includes the following steps: 1) providing a semiconductor substrate, wherein a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the shape and the position of a shallow groove are defined by the first etching window; 2) performing a main etching step, including performing deep etching on the semiconductor substrate through the first etching window to form a trench structure in the semiconductor substrate and a bottom etching byproduct at the bottom of the trench structure; 3) performing a bottom breakthrough step comprising removing the bottom etch byproducts; 4) performing a trench wall protection step, including forming a sidewall oxide layer on the sidewall of the trench structure to form the shallow trench in the semiconductor substrate; 5) and performing a second main etching step, including performing deep etching on the semiconductor substrate through the first etching window.
Another method for fabricating a shallow trench in a semiconductor substrate provided by the present application will be described in detail below with reference to the accompanying drawings.
First, step 1) is performed, a semiconductor substrate 100 is provided, a mask layer 200 is formed on the semiconductor substrate 100, the mask layer 200 has a first etching window 210, and the first etching window 210 defines the shape and the position of the shallow trench 120, as shown in fig. 14.
Specifically, a semiconductor substrate 100 is first provided, and the material of the semiconductor substrate 100 includes, but is not limited to, a single crystal or polycrystalline semiconductor material, and may be an intrinsic single crystal silicon substrate or a lightly doped silicon substrate, and further may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate. A mask layer 200 is formed on the semiconductor substrate 100, and the material of the mask layer 200 includes, but is not limited to, silicon nitride, silicon oxide, and carbon, which have a high selectivity with respect to other materials of the semiconductor substrate 100. The mask layer 200 has a first etch window 210, and the first etch window 210 may define the shape and location of the shallow trench 120.
Optionally, in step 1), a surface protection layer 300 is further formed on the semiconductor substrate 100, the surface protection layer 300 is located between the mask layer 200 and the semiconductor substrate 100, and the surface protection layer 300 has a second etching window 310 corresponding to the first etching window 210, as shown in fig. 15.
Specifically, a surface protection layer 300 is further formed between the mask layer 200 and the semiconductor substrate 100 for protecting the surface of the semiconductor substrate 100, and the material of the surface protection layer 300 includes, but is not limited to, silicon nitride, silicon oxide, carbon, and other materials having a high selectivity ratio with the materials of the semiconductor substrate 100 and the mask layer 200. The surface protection layer 300 has a second etch window 310 coinciding with the first etch window 210.
Next, step 2) is performed, and a first main etching step is performed, including performing a deep etching on the semiconductor substrate 100 through the first etching window 210, so as to form the trench structure 110 in the semiconductor substrate 100 and the bottom etching by-products 111 at the bottom of the trench structure 110, as shown in fig. 16.
Specifically, the semiconductor substrate 100 is etched back downward through the first etching window 210, and the trench structure 110 is formed in the semiconductor substrate 100, and during the etching back, non-volatile or difficult-to-remove etching byproducts are generated and accumulated at the bottom of the trench structure 110 and the surface of the mask layer 200.
Optionally, in step 2), the semiconductor substrate 100 is deeply etched in a pulsed bias power output mode.
Specifically, referring to fig. 6A, in fig. 6A, the X-axis direction is the etching time, the Y-axis direction is the depth of the shallow trench, the triangle is marked as the continuous bias power output mode, and the circle is marked as the pulsed bias power output mode. It can be found from the experimental results that with increasing time, the shallow trench depth does not increase rapidly any more after the 4 th moment of the etching time using the continuous bias power output mode, indicating that the etching has terminated. And the use of the pulsed bias power output mode, the etching time is continuously increased from the shallow trench depth from the 1 st to the 6 th, which shows that the use of the pulsed bias power output mode can improve the etching termination.
Referring to fig. 6B, it can be seen from the experimental results that the load of the shallow trench depth continuously increases with the increase of time by using the continuous bias power output mode, which indicates that the non-uniformity of the depth continuously deteriorates, and the load of the shallow trench depth exceeds 6 units when the etching time reaches the 6 th time point in fig. 6B. And by using a pulse bias power output mode, the depth load of the shallow trench is obviously increased and is not obvious, and when the etching time reaches the 6 th moment, the depth load is about 2 units, so that the shallow trench depth load is obviously improved. Therefore, according to the experimental result, the pulse type bias power output mode is selected in the shallow trench main etching step.
Because the shallow trench 120 needs to be etched for a long time due to the increase of the aspect ratio, if the bias power is continuously output, the selection ratio of the mask layer 200 to silicon is insufficient, and the mask layer 200 is etched while the semiconductor substrate 100 is etched, thereby causing a flaring phenomenon. In the embodiment of the present application, a pulse bias power output mode may be adopted to improve the flaring phenomenon, and the pulse bias power output mode may rapidly switch the bias power between the output mode and the close mode at a certain frequency, so that in the close mode, the consumption of the mask layer 200 may be reduced, the flaring phenomenon may be improved, and the selection ratio of the mask layer 200 to silicon may be increased.
Optionally, in step 2), the duty ratio of the pulsed bias power output is between 10% and 60%.
Specifically, referring to fig. 7A, the duty ratio refers to the proportion of the time that the bias power is in the output mode relative to the total time in one pulse cycle, and the whole etching process is composed of a plurality of pulse cycles. The longer the output pattern time, the larger the duty ratio, and the shorter the output pattern time, the smaller the duty ratio. If the bias power is always output, it means that the duty ratio is 100%, and it is regarded as continuous bias power output. Referring to fig. 7B, the duty ratio of the pulsed bias power output is shown in the X-axis direction, and the depth load is shown in the Y-axis direction. From the experimental results, it can be found that the smaller the duty ratio, the better the depth load can be obtained, and thus the effect of improving the depth load can be achieved by optimizing the duty ratio. According to the technical scheme of the application, the longer the time in the output mode is, the larger the duty ratio is. The uniformity of the etching depth of the shallow trench 120 can be improved by adjusting the duty ratio, wherein the smaller the duty ratio, the better the uniformity of the etching depth of the shallow trench 120. Preferably, in the embodiment of the present application, the duty cycle of the pulsed bias power output is between 10% and 60%.
Optionally, in the step 2), the semiconductor substrate 100 is deeply etched in a low-frequency pulse bias power output mode, the 13mHz source power of the reaction instrument used in the step 2) is 2000W-3000W, and the 2mHz pulse bias power is 500W-1500W.
Specifically, referring to fig. 8A, the X-axis direction is the ion energy, and the Y-axis direction is the ion energy distribution, it is obvious that most of the ion energy is greater than 1000eV at low frequency (2mHz), and most of the ion energy is lower than 500eV at high frequency (13.56 mHz). Referring to FIG. 8B, the X-axis direction is 2mHz and 13mHz, the main Y-axis direction (left) is the depth of the shallow trench, and the sub Y-axis direction (right) is the bottom width of the shallow trench. From the experimental results, it can be found that under the same etching time, the depth of the shallow trench can be obtained at 2mHz, the depth of the shallow trench corresponding to 2mHz is about 2.5 units, and the depth of the shallow trench corresponding to 13mHz is about 2.2 units. Under the same etching time, 2mHz can obtain larger bottom width, the bottom width corresponding to 2mHz is about 12 units, and the bottom width corresponding to 13mHz is about 6 units. Experimental results prove that the lower frequency has higher ion energy, and the ions can reach deeper shallow trench etching silicon substrates. Therefore, according to the experimental result, the shallow trench main etching step selects a low-frequency bias power output mode. Preferably, a 2mHz pulse bias power output mode can be adopted, the bias power is between 500W and 1500W, the cavity temperature of a reaction instrument used in the deepening etching is between 50 ℃ and 80 ℃, the temperature of the electrostatic chuck is between 20 ℃ and 70 ℃, the cavity pressure is between 5mT and 30mT, and the source power of 13mHz is between 2000W and 3000W.
Optionally, the reaction gas introduced for performing the deep etching on the semiconductor substrate 100 in step 2) includes chlorine (Cl)2) Oxygen (O)2) And helium (He).
Specifically, in the embodiment of the present application, the reaction gas introduced during the deep etching includes chlorine (Cl)2) Oxygen (O)2) And helium (He), in which chlorine (Cl) gas2) Which is the main etching gas, reacts with the semiconductor substrate 100 and the resulting product is carried away by the gas in the reaction apparatus.
Continuing with step 3), a bottom punch-through step is performed, including removing the bottom etch byproducts 111, as shown in FIG. 17.
Specifically, when the semiconductor substrate 100 is deeply etched, a bottom etching byproduct 111 is generated at the bottom of the trench structure 110, and due to the reduction of the critical dimension, the bottom etching byproduct 111 is not easily discharged, which affects the etching rate, and as the etching time increases, a large amount of the bottom etching byproduct 111 accumulates, and the etching reactant cannot contact with the bottom of the trench structure 110, so that the etching is ended in advance, and the trench structure 110 cannot reach the target etching depth. Therefore, after performing the etch-back, the bottom etch byproducts 111 need to be removed to ensure that the reactants can contact the bottom of the trench structure 110, and to ensure the etch rate and the etch depth of the trench structure 110.
Optionally, the bottom etching by-products 111 are removed in step 3) by using a pulsed bias power output mode.
Specifically, the pulse bias power output mode can rapidly switch the bias power between the output mode and the off mode at a certain frequency, and the off mode does not generate the bottom etching by-product 111, thereby facilitating the discharge of the bottom etching by-product 111, avoiding the termination of etching, improving the etching rate and ensuring the etching depth.
Optionally, in step 2), while performing deep etching on the semiconductor substrate 100, a surface etching byproduct 220 is formed on the surface of the mask layer 200; removing the bottom etching by-products 111 and simultaneously removing the surface etching by-products 220 on the surface of the mask layer 200 in step 3), as shown in fig. 16 and 17.
Specifically, during the deep etching process, when the bottom etching by-product 111 is discharged from the bottom of the trench structure 110, a part of the bottom etching by-product 111 may accumulate on the surface of the mask layer 200 to form a surface etching by-product 220, for the trench structure 110 with a small critical dimension, a reactant for etching the semiconductor substrate 100 is not easy to enter from the opening of the trench structure 110, which may cause a decrease in etching rate, and as the etching time increases, a large amount of accumulated surface etching by-product 220 may block the opening of the trench structure 110 to stop etching, while for the trench structure 110 with a large critical dimension, the influence of the surface etching by-product 220 on the etching depth is small, and the reactant for etching the semiconductor substrate 100 may enter the trench structure 110, which may cause poor uniformity of the etching depth. Thus, the bottom etch byproducts 111 are removed along with the surface etch byproducts 220 on the surface of the mask layer 200. The etching termination can be avoided, the etching rate is further improved, the etching depth is ensured, and the uniformity of the etching depth is improved.
Optionally, the temperature of the cavity of the reaction instrument used in step 3) is 50-80 ℃, the temperature of the electrostatic chuck is 20-70 ℃, the pressure of the cavity is 5-30 mT, the source power of 13mHz is 500-1500W, and the pulsed bias power of 13mHz is 100-1000W.
Optionally, in step 3), the duty ratio of the pulsed bias power output is between 10% and 60%.
Specifically, the uniformity of the etching depth of the shallow trench 120 can be improved by adjusting the duty ratio. The smaller the duty cycle, the better the uniformity of the etch depth of the shallow trench 120. Preferably, the duty cycle of the pulsed bias power output is between 10% and 60%.
Optionally, the reaction gas introduced for removing the bottom etching by-products 111 in step 3) includes carbon tetrafluoride (CF)4) And argon (Ar).
Specifically, the fluorine-based gas can easily remove the bottom etch by-products 111 and be carried out by the gas in the reaction apparatus.
Continuing to perform step 4), a trench wall protection step is performed, including forming a sidewall oxide layer 112 on the sidewalls of the trench structure 110 to form the shallow trench 120 in the semiconductor substrate 100, as shown in fig. 18.
Specifically, after removing the bottom etching by-products 111, the sidewalls of the trench structure 110 are oxidized, and a sidewall oxide layer 112 is formed on the sidewalls, so as to form the shallow trench 120, wherein the sidewall oxide layer 112 can protect the sidewalls of the shallow trench 120.
Optionally, the reaction gas introduced to form the sidewall oxide layer 112 on the sidewall of the trench structure 110 in step 4) includes oxygen (O)2) And argon (Ar).
Specifically, in forming the sidewall oxide layer 112, the gas introduced into the reaction apparatus includes oxygen (O)2) And argon (Ar), oxygen (O)2) The following reaction occurs with the sidewalls of the trench structure 110:
Si(s)+O2(g)→SiO2(s)
silicon dioxide (SiO)2) The sidewall oxide layer 112 is formed on the sidewall of the trench structure 110 to protect the sidewall of the shallow trench 120 and to adjust the flow of oxygen (O)2) The amount of the adjustment adjusts the angle of the sidewalls of the trench structure 110.
Optionally, the temperature of the cavity of the reaction instrument used in the step 4) is 50-80 ℃, the temperature of the electrostatic chuck is 20-70 ℃, the pressure of the cavity is 5-30 mT, and the power of the 13mHz source is 2000-3000W.
And then, executing the step 5), and executing a second main etching step, wherein the second main etching step comprises the step of carrying out deepening etching on the semiconductor substrate through the first etching window.
Specifically, the second main etching step in step 5) is the same as the first main etching step in step 2), and therefore is not described in detail herein. The etching can be performed by using the existing etching technique after performing step 5), or step 3) and step 4) are not required to be performed after the depth of the shallow trench 120 reaches the design requirement.
Optionally, when the shallow trench 120 is formed in the semiconductor substrate 100, the reaction apparatus used in performing the steps 2) to 5) is the same reaction apparatus.
Specifically, the same reaction instrument is used in the three steps of main etching, bottom penetration and groove wall protection, and the shallow groove 120 with good depth uniformity and proper angle and reaching the target etching depth can be etched in a short time by changing the working parameters of the reaction instrument and the gas introduced into the reaction instrument and switching between different steps.
Optionally, the shallow trenches 120 include a first shallow trench 121 and a second shallow trench 122, a width ratio of the second shallow trench 122 to the first shallow trench 121 is between 2 and 7, and a depth ratio of the second shallow trench 122 to the first shallow trench 121 is between 0.7 and 1.3, as shown in fig. 19.
Specifically, the shallow trenches 120 with different widths can be manufactured by the method for manufacturing the semiconductor substrate shallow trench, wherein the ratio of the widths of the second shallow trench 122 to the first shallow trench 121 is 2-7, and the ratio of the depths of the second shallow trench 122 to the first shallow trench 121 is 0.7-1.3.
As shown in fig. 12, the present application further provides a semiconductor substrate shallow trench structure, which is formed by using the method for manufacturing a semiconductor substrate shallow trench provided by the present application, and the semiconductor substrate shallow trench structure includes: the mask layer 200 is formed on the semiconductor substrate, and the depth ratio of the second shallow trench 122 to the first shallow trench 121 is 0.7-1.3.
Optionally, a surface protection layer 300 is further formed on the semiconductor substrate 100, and the surface protection layer 300 is located between the mask layer 200 and the semiconductor substrate 100, as shown in fig. 12.
It should be noted that, the steps of the semiconductor substrate shallow trench fabrication method described in the above embodiments are all necessary steps for reflecting the technical solution of the present application as a whole and solving the technical problems of the present application, but are not limited to the above steps, and those skilled in the art can understand that other known steps may also be included in the semiconductor substrate shallow trench fabrication method, and for conciseness and conciseness of the description of the present application, these conventionally known steps are not described in detail in the present application, but should be regarded as belonging to the protection scope of the present application.
The preferred embodiments of the present application have been described in detail with reference to the accompanying drawings, however, the present application is not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the present application within the technical idea of the present application, and these simple modifications are all within the protection scope of the present application.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, various possible combinations are not described separately in this application.
In addition, any combination of the various embodiments of the present application is also possible, and the same should be considered as disclosed in the present application as long as it does not depart from the idea of the present application.
Claims (18)
1. A method for manufacturing a semiconductor substrate shallow trench is characterized by comprising the following steps:
1) providing a semiconductor substrate, wherein a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the shape and the position of a shallow groove are defined by the first etching window;
2) performing a main etching step of cyclic etching, including performing deep etching on the semiconductor substrate through the first etching window to form a trench structure in the semiconductor substrate and a bottom etching byproduct at the bottom of the trench structure;
3) a bottom breakthrough step of cyclic etching comprising removing the bottom etch by-product;
4) performing a groove wall protection step of circular etching, wherein a side wall oxide layer is formed on the side wall of the groove structure;
5) and circularly executing the step 2) to the step 4) until the depth of the groove structure reaches a preset depth so as to form the shallow groove in the semiconductor substrate.
2. The method for manufacturing the shallow trench in the semiconductor substrate as claimed in claim 1, wherein in the step 1), a surface protection layer is further formed on the semiconductor substrate, the surface protection layer is located between the mask layer and the semiconductor substrate, and the surface protection layer has a second etching window corresponding to the first etching window.
3. The method for manufacturing the shallow trench of the semiconductor substrate as claimed in claim 2, wherein in the step 2), a surface etching byproduct is formed on the surface of the mask layer while the semiconductor substrate is deeply etched;
and 3) removing the surface etching by-products on the surface of the mask layer while removing the bottom etching by-products.
4. The method for manufacturing the shallow trench of the semiconductor substrate as claimed in claim 2, wherein in the step 2), the semiconductor substrate is deeply etched in a pulse bias power output mode, and the duty ratio of the pulse bias power output is 10% -60%; and 3) removing the bottom etching byproducts in a pulse bias power output mode, wherein the duty ratio of pulse bias power output is 10-60%.
5. The method for manufacturing the shallow trench of the semiconductor substrate as claimed in claim 2, wherein in the step 2), the semiconductor substrate is deeply etched by using a low-frequency pulse type bias power output mode, the 13mHz source power of the reaction instrument used in the step 2) is 2000W-3000W, and the 2mHz pulse type bias power is 500W-1500W; the power of a 13mHz source of the reaction instrument used in the step 3) is 500-1500W, and the pulse type bias power of the 13mHz source is 100-1000W; the power of the 13mHz source of the reaction instrument used in the step 4) is 2000-3000W.
6. The method for manufacturing the shallow trench of the semiconductor substrate as claimed in claim 2, wherein the reaction gas introduced for the deep etching of the semiconductor substrate in the step 2) comprises chlorine (Cl)2) Oxygen (O)2) And helium (He); the reaction gas introduced for removing the bottom etching by-products in the step 3) comprises carbon tetrafluoride (CF)4) And argon (Ar); forming the sidewall oxide layer on the sidewall of the trench structure in the step 4), and introducing a reaction gas including oxygen (O)2) And argon (Ar).
7. The method as claimed in claim 2, wherein the step 5) is performed for 4 to 19 times.
8. The method for fabricating the shallow trench in the semiconductor substrate according to any one of claims 1 to 7, wherein the reaction apparatus used in the steps 2) to 5) is the same reaction apparatus when the shallow trench is formed in the semiconductor substrate.
9. The method as claimed in claim 2, wherein the shallow trench includes a first shallow trench and a second shallow trench, a ratio of a width of the second shallow trench to a width of the first shallow trench is between 2 and 7, and a ratio of a depth of the second shallow trench to a depth of the first shallow trench is between 0.7 and 1.3.
10. A method for manufacturing a semiconductor substrate shallow trench is characterized by comprising the following steps:
1) providing a semiconductor substrate, wherein a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the shape and the position of a shallow groove are defined by the first etching window;
2) performing a first main etching step, including performing deep etching on the semiconductor substrate through the first etching window to form a trench structure in the semiconductor substrate and a bottom etching byproduct at the bottom of the trench structure;
3) performing a bottom breakthrough step comprising removing the bottom etch byproducts;
4) performing a trench wall protection step, including forming a sidewall oxide layer on the sidewall of the trench structure to form the shallow trench in the semiconductor substrate;
5) and performing a second main etching step, including performing deep etching on the semiconductor substrate through the first etching window.
11. The method for manufacturing the shallow trench in the semiconductor substrate as claimed in claim 10, wherein in the step 1), a surface protection layer is further formed on the semiconductor substrate, the surface protection layer is located between the mask layer and the semiconductor substrate, and the surface protection layer has a second etching window corresponding to the first etching window.
12. The method for manufacturing the shallow trench of the semiconductor substrate as claimed in claim 11, wherein in the steps 2) and 5), surface etching byproducts are formed on the surface of the mask layer while the semiconductor substrate is deeply etched;
and 3) removing the surface etching by-products on the surface of the mask layer while removing the bottom etching by-products.
13. The method for manufacturing the shallow trench in the semiconductor substrate as claimed in claim 11, wherein in the step 2) and the step 5), the semiconductor substrate is deeply etched in a pulse bias power output mode, and the duty ratio of the pulse bias power output is 10% -60%; and 3) removing the bottom etching byproducts in a pulse bias power output mode, wherein the duty ratio of pulse bias power output is 10-60%.
14. The method for manufacturing the shallow trench in the semiconductor substrate as claimed in claim 11, wherein the semiconductor substrate is deeply etched in the step 2) and the step 5) by using a low-frequency pulse type bias power output mode, the 13mHz source power of the reaction instrument used in the step 2) and the step 5) is 2000W-3000W, and the 2mHz pulse type bias power is 500W-1500W; the power of a 13mHz source of the reaction instrument used in the step 3) is 500-1500W, and the pulse type bias power of the 13mHz source is 100-1000W; the power of the 13mHz source of the reaction instrument used in the step 4) is 2000-3000W.
15. The method for manufacturing the shallow trench in the semiconductor substrate as claimed in claim 11, wherein the reaction gas introduced for deep etching the semiconductor substrate in the steps 2) and 5) includes chlorine (Cl)2) Oxygen (O)2) And helium (He), wherein the reaction gas introduced for removing the bottom etching by-product in the step 3) comprises carbon tetrafluoride (CF)4) And argon (Ar), wherein the reaction gas introduced by forming the side wall oxide layer on the side wall of the groove structure in the step 4) comprises oxygen (O)2) And argon (Ar).
16. The method for fabricating the shallow trench in the semiconductor substrate according to any one of claims 10 to 15, wherein the reaction apparatus used in the steps 2) to 5) is the same reaction apparatus when the shallow trench is formed in the semiconductor substrate.
17. A semiconductor substrate shallow trench structure manufactured by the method for manufacturing a semiconductor substrate shallow trench according to claim 1, comprising:
the mask layer is formed on the semiconductor substrate, the width ratio of the second shallow trench to the first shallow trench is 2-7, and the depth ratio of the second shallow trench to the first shallow trench is 0.7-1.3.
18. The semiconductor substrate shallow trench structure of claim 17 wherein a surface protection layer is further formed on the semiconductor substrate, the surface protection layer being located between the mask layer and the semiconductor substrate.
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| WO2022057337A1 (en) * | 2020-09-18 | 2022-03-24 | 长鑫存储技术有限公司 | Manufacturing method for semiconductor structure |
| CN114628323A (en) * | 2022-05-05 | 2022-06-14 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| US11915933B2 (en) | 2020-09-18 | 2024-02-27 | Changxin Memory Technologies, Inc. | Manufacturing method of semiconductor structure |
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| US11915933B2 (en) | 2020-09-18 | 2024-02-27 | Changxin Memory Technologies, Inc. | Manufacturing method of semiconductor structure |
| CN114628323A (en) * | 2022-05-05 | 2022-06-14 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
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