WO2015074621A1 - Etching method for controlling micro-loading effect of depth of shallow trenches - Google Patents

Etching method for controlling micro-loading effect of depth of shallow trenches Download PDF

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WO2015074621A1
WO2015074621A1 PCT/CN2014/092156 CN2014092156W WO2015074621A1 WO 2015074621 A1 WO2015074621 A1 WO 2015074621A1 CN 2014092156 W CN2014092156 W CN 2014092156W WO 2015074621 A1 WO2015074621 A1 WO 2015074621A1
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wafer
etching
polymer
film layer
gas
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PCT/CN2014/092156
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French (fr)
Chinese (zh)
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符雅丽
李国荣
杨盟
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北京北方微电子基地设备工艺研究中心有限责任公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Definitions

  • the present invention relates to the field of semiconductor device manufacturing, and more particularly to an etching method for controlling the shallow micro-load effect of shallow trenches.
  • the micro load effect is as shown in FIG. 1 , wherein in the wafer 100, the photoresist 101, the mask layer 102, and the silicon oxide layer are sequentially in order from top to bottom. 103, the base silicon 104, and the wafer 100 further includes a small opening area 110 and a large opening area 120.
  • An etching method for controlling shallow trench depth micro-loading effect includes the following steps: mask etching a wafer entering a process chamber until an opening on the wafer contacts Substrate silicon to the wafer; depositing a deposition gas into the process chamber to perform a deposition reaction, depositing a polymer-like film layer on the wafer that blocks the subsequent etching; The inert gas is introduced into the process chamber, and the polymer film layer is processed under plasma excitation conditions; the wafer is subjected to a shallow trench etching process to a predetermined depth.
  • the polymer-like film layer which blocks the subsequent etching is a polymer-like film layer having carbon and hydrogen components.
  • the polymer-like film layer which blocks the subsequent etching is a SiO 2 -based film layer.
  • the polymer is from 10 angstroms to 300 angstroms.
  • the method further comprises the step of: removing the photoresist remaining in the wafer by ashing.
  • the deposition gas is CH 4 or a combination of SiH 4 and O 2 .
  • the inert gas is Ar and/or He.
  • the thickness of the polymer-like film layer is controlled by the deposition time.
  • the inert gas is introduced into the process chamber, and the polymer film layer is treated under plasma excitation conditions, including the steps of: introducing an inert gas into the process chamber; Treating the polymer film layer under excitation conditions;
  • the point detection method captures the moment when the small-sized open area of the wafer exposes the base silicon, ends the current step, and completes the step of processing the polymer-like film layer.
  • the process condition of performing a mask etching process on the wafer entering the process chamber until the opening on the wafer contacts the base silicon of the wafer is: source power It is 400-700W, the bias power is 100-300W, the air pressure is 3mt ⁇ 10mt, the etching time is 10 ⁇ 40s per step, the main gas is CF 4 and CH 2 F 2 , the flow rate is 50-350sccm, and the auxiliary gas is O. 2 , Ar, He, the auxiliary gas flow rate other than oxygen is 50 ⁇ 150sccm, oxygen flow rate is 5 ⁇ 30scc;
  • the process condition of the process step of depositing a deposition gas into the process chamber to perform a deposition reaction and depositing a polymer-like film layer for blocking the subsequent etching on the wafer is: source power 100 to 1000W, bias power is 0W ⁇ 50W, deposition gas flow is 10 ⁇ 500sccm, process pressure is 1 ⁇ 100mT, process time is 10 ⁇ 60s;
  • the process conditions for introducing the inert gas into the process chamber and treating the polymer film layer under plasma excitation conditions are: source power is 100-1000 W, bias power is 50 W ⁇ 300W, Ar flow rate is 10 ⁇ 500sccm, He flow is 10 ⁇ 500sccm, process pressure is 1 ⁇ 100mT, process time is 10-60s;
  • the process conditions for performing the shallow trench etching process on the wafer to a predetermined depth are: source power is 700-1200 W, bias power is 100-200 W, air pressure is 10 mt ⁇ 25 mt, etching time It is 70 to 100 s, the main gas is HBr, the flow rate is 300-500 sccm, and the auxiliary gas is at least one of Cl 2 , NF 3 , SF 6 , N 2 , O 2 , and HeO 2 , and the flow rate is 5-50 sccm.
  • the process conditions of the process step of depositing a deposition gas into the process chamber, performing a deposition reaction, and depositing a polymer-like film layer for blocking the subsequent etching on the wafer are:
  • the source power is 300-700W
  • the bias power is 0W
  • the deposition gas flow rate is 100-200sccm
  • the process gas pressure is 10-30mT
  • the process time is 10-30s;
  • the process condition of the process step of injecting an inert gas into the process chamber to treat the polymer-like film layer under plasma excitation conditions is: source power is 300 to 700 W, bias power is 100 W to 200 W, Ar flow rate is 100 to 200 sccm, He flow rate is 100 to 200 sccm, process gas pressure is 5 to 20 mT, and process time is 10-20 s.
  • the process conditions of the process step of removing the photoresist from the wafer by the ashing process are: source power is 700-1200 W, bias power is 0 W, air pressure is 10 mt to 30 mt, and etching time is 80 ⁇ . At 120 s, the gas is O 2 and the flow rate is 200 to 500 sccm.
  • the invention provides an etching method for controlling the micro-load effect of shallow trench depth, which can be used to form a trench by adding a deposition step of a polymer-like film layer and a modification step of the deposited polymer-like film layer. Etching the opposite effect of the microloading effect effectively reduces or eliminates the etch depth microloading effect in the trench etch.
  • the etching method for controlling the micro-load effect of shallow trench depth provided by the invention does not need to add an additional process, is simple in operation, and has a short time; and can be adjusted and controlled by process parameters such as time for specific equipment processing, and has high flexibility. . At the same time, this method can help balance the difference in critical dimensions of different opening areas of the wafer to a certain extent.
  • FIG. 1 is a schematic view of a wafer after conventional trench etching
  • FIG. 2 is a flow chart of a specific embodiment of an etching method for controlling a micro-load effect of a shallow trench depth according to the present invention
  • step S100 is performed by the method shown in FIG. 2;
  • step S200 is performed by the method shown in FIG. 2;
  • FIG. 5 is a schematic structural view of a wafer when step S300 is performed by using the method shown in FIG. 2;
  • step S400 is performed by the method shown in FIG. 2;
  • FIG. 7 is a flow chart of another embodiment of an etching method for controlling shallow trench depth microloading effects of the present invention.
  • the etching method for controlling the shallow trench depth micro-load effect provided by the embodiment of the present invention, as described in FIG. 2, includes the following steps:
  • the mask layer 102 of the wafer 100 entering the process chamber is etched, and the opening on the wafer 100 is etched to contact the base silicon to complete the etching of the mask layer 100.
  • the wafer 100 from top to bottom, there are a photoresist layer 101, a mask layer 102, a silicon oxide layer 103, and a base silicon 104, wherein the mask layer 102 is a SIN type hard mask layer. .
  • the wafer 100 further includes a small opening area 110 and a large opening area 120.
  • a deposition gas is introduced into the process chamber to perform a deposition reaction, and a polymer-like film layer that blocks the subsequent etching is deposited on the wafer.
  • a deposition gas is introduced into the process chamber to perform a deposition reaction, and a polymer-like film layer that blocks the subsequent etching is deposited on the wafer.
  • a deposition gas is introduced into the process chamber to perform a deposition reaction, and a polymer-like film layer that blocks the subsequent etching is deposited on the wafer.
  • a deposition gas is introduced into the process chamber to perform a deposition reaction, and a polymer-like film layer that blocks the subsequent etching is deposited on the wafer.
  • the total contact area of the small opening area 110 ie, all the small opening areas in the small opening area 110 and the large opening area 120 of the same opening area during the deposition of the polymer-like film layer 105 (ie, all small opening areas)
  • the sum of the areas of the bottom of the layer 110 and the sidewalls of the polymer-depositable polymer film layer 105 is greater than the total contact area of the large opening region 120 (i.e., the bottom of the large opening region 120 and the sidewalls of the depositable polymer)
  • the sum of the areas of the film layers 105 causes
  • the thickness of the polymer-like film layer 105 deposited in the large opening region 120 is greater than the thickness of the polymer-like film layer 105 deposited by the small opening region 110.
  • the deposition does not occur only at the bottom of the opening.
  • the sidewalls of the opening are also deposited with a polymer film layer 105 of different thickness.
  • the larger the opening area the side wall thereof The thicker the deposited polymer-like film layer 105 will be. This difference also balances the loading effect of the opening size of the trench etching process to some extent.
  • an inert gas is introduced into the process chamber, and the polymer-like film layer is treated under plasma excitation conditions.
  • the polymer-like film layer 105 at all positions of the wafer 100 is thinned or disappears.
  • the treatment is to modify the polymer-like film layer 105 to make the film layer thin or disappear. It is primarily a physical bombardment where the rate of consumption of the deposited polymer-like film layer 105 is approximately the same at different openings.
  • the thickness of the polymer-like film layer 105 deposited in the large opening region 120 is still greater than the thickness of the polymer-like film layer 105 deposited in the small opening region 110. And after the treatment of this step, the thickness of the deposited deposit is proportional to the size of the opening.
  • a small amount of other auxiliary gas may be added in the step for processing, such as O 2 , N 2 , H 2 and the like.
  • the preset depth is an etch depth set according to actual needs of the semiconductor device. It should be noted here that due to the blocking of the polymer-like film layer 105, the etching speed of the large opening region 120 may be slowed relative to the original state, so that the small opening region 110 and the large opening region 120 may be etched. The depth is the same or similar, as shown in Figure 6.
  • the etching method for controlling the micro-load effect of the shallow trench depth provided by the embodiment of the present invention can be performed by adding a deposition step of the polymer-like film layer and a step of modifying the deposited layer.
  • the etching method for controlling the shallow micro-load effect of the shallow trench provided by the embodiment of the invention does not need to add an additional process, is simple in operation, has a short time, and can be adjusted and controlled by time and other process parameters for specific equipment processing, and flexibility. Big. At the same time, this method can help balance the difference in key dimensions of different opening areas of the wafer to a certain extent.
  • the polymer-like film layer that blocks the subsequent etching is a polymer-like film layer having carbon and hydrogen components.
  • the polymer-like film layer 105 whose main component is carbon and hydrogen is equivalent to a photoresist, which acts as a barrier to subsequent etching, thereby equivalent to a slowing of the etching rate, and a polymer film deposited due to the large opening region 120.
  • the thickness of the layer is large, so the effect of slowing down the etching speed of the large opening region 120 is more pronounced.
  • the polymer-like film layer which has a certain blocking effect on the subsequent etching is a SiO 2 -based film layer.
  • the SiO 2 -type film layer can also play a role in relatively slowing the etching speed of the large opening region 120.
  • the polymer-like film layer 105 has a thickness of 10 angstroms to 300 angstroms.
  • the etching method for controlling the shallow trench depth micro-loading effect further includes the following steps: S500, removing the photoresist remaining in the wafer by ashing.
  • the deposition gas is CH 4 or a combination of SiH 4 and O 2 .
  • the gas CH 4 is used for deposition, a polymer-like film layer mainly composed of carbon and hydrogen can be formed.
  • a combination of SiH 4 and O 2 gas is used as a deposition gas, a SiO 2 -type film layer can be formed, which can be relatively reduced. The effect of the etch rate in the slow open area.
  • other gas combinations which can produce a similar deposited film layer are also applicable in other embodiments of the invention, such as other carbon and hydrogen containing gases.
  • the inert gas is Ar and/or He.
  • the thickness of the polymer-like film layer is controlled by deposition time.
  • the deposition time of the polymer-like polymer can be obtained through preliminary experiments.
  • the TEM slice analysis can be performed after the trench etching is completed by presetting a short deposition time to verify the difference in depth at different opening sizes. If the difference is still large, the deposition time needs to be increased. This is repeated until the depth difference is reduced to an acceptable range. This is a simple process test that can be directly performed by a person skilled in the art according to the description, and will not be described in detail herein.
  • the thickness of the polymer-like film layer can also be adjusted and controlled by other parameters of the processing process or a combination of parameters, such as source power, gas pressure, and gas flow rate.
  • the treatment of the polymer-like polymer can also be controlled by other parameters or combinations of parameters of the processing process, such as process time, source power, gas pressure, and gas flow rate.
  • step S300 includes the following steps:
  • the embodiment of the invention can accurately grasp the time of the polymer-like treatment, make the process processing more accurate, and at the same time reduce the cost and improve the production efficiency.
  • the etching process for mask etching of a wafer entering a process chamber until the opening on the wafer contacts the base silicon of the wafer
  • the process conditions of the step are: source power is 400-700 W, bias power is 100-300 W, air pressure is 3 mt to 10 mt, etching time is 10-40 s, and main gas is CF 4 and CH. 2 F 2 , the flow rate is 50-350 sccm, the auxiliary gas is O 2 , Ar, He, the auxiliary gas flow rate other than oxygen is 50-150 sccm, and the oxygen flow rate is 5-30 sccm.
  • Performing a process step of depositing a deposition gas into the process chamber to perform a deposition reaction, depositing a polymer-like film layer blocking the subsequent etching on the wafer ie, step S200
  • the process conditions are: the source power is 100-1000W, and the bias power is 0W-50W.
  • the deposition gas flow rate is 10 to 500 sccm, the process gas pressure is 1 to 100 mT, and the process time is 10 to 60 s.
  • step S300 The process step of introducing an inert gas into the process chamber to process the polymer-like film layer under plasma excitation conditions (ie, step S300) is: source power is 100-1000W
  • the bias power is 50W to 300W
  • the Ar flow rate is 10 to 500 sccm
  • the He flow rate is 10 to 500 sccm
  • the process gas pressure is 1 to 100 mT
  • the process time is 10-60 s.
  • step S400 The process conditions for performing the shallow trench etching process on the wafer to a predetermined depth (ie, step S400) are: source power is 700-1200 W, bias power is 100-200 W, and air pressure is 10 mt. ⁇ 25mt, etching time is 70-100s, main gas is HBr, flow rate is 300-500sccm, auxiliary gas is at least one of Cl 2 , NF 3 , SF 6 , N 2 , O 2 , HeO 2 , flow rate is 5-50 sccm.
  • the deposition gas is introduced into the process chamber to perform a deposition reaction, and a polymer-like film layer for blocking subsequent etching is deposited on the wafer.
  • the process conditions of the process step are: source power is 300-700 W, bias power is 0 W, deposition gas flow is 100-200 sccm, process gas pressure is 10-30 mT, and process time is 10-30 s.
  • the process condition that the inert gas is introduced into the process chamber to process the polymer-like film layer under plasma excitation conditions is: source power is 300-700W
  • the bias power is 100 W to 200 W
  • the Ar flow rate is 100 to 200 sccm
  • the He flow rate is 100 to 200 sccm
  • the process gas pressure is 5 to 20 mT
  • the process time is 10-20 s.
  • the process condition of removing the photoresist ashing removal of the wafer is as follows: the source power is 700-1200 W, and the bias power is 0W, the gas pressure is 10 mt to 30 mt, the etching time is 80 to 120 s, the gas is oxygen, and the flow rate is 200 to 500 sccm.

Abstract

An etching method for controlling the micro-loading effect of the depth of shallow trenches comprises the following steps: etching the mask layers on the wafer entering a process chamber, until the openings on the wafer contact with the Si substrate of the wafer; feeding deposition gases into the process chamber to carry out deposition reaction, in order to deposit a layer of polymer-like film preventing from thickness etching; feeding inert gases into the process chamber and processing the polymer-like film under the condition of plasma excitation; carrying out a shallow trenching etching process on the wafer till the predetermined depth. It can effectively reduce or eliminate the micro-loading effect of etching depth during the etching of the trenches, need no additional processes with simple operation and relatively short elapsed-time, and furthermore can adjust with great flexibility by controlling the process parameter, such as time, for special equipment process.

Description

控制浅沟槽深度微负载效应的刻蚀方法Etching method for controlling micro-load effect of shallow trench depth 技术领域Technical field
本发明涉及半导体设备制造领域,尤其涉及一种控制浅沟槽深度微负载效应的刻蚀方法。The present invention relates to the field of semiconductor device manufacturing, and more particularly to an etching method for controlling the shallow micro-load effect of shallow trenches.
背景技术Background technique
一般的,对于晶圆上不同开口尺寸的沟槽刻蚀,刻蚀完成后的深度是存在一定差异的,这种微负载效应(Micro-loading effect)是和刻蚀过程的副产物挥发速度随着刻蚀深宽比的不同而导致的。近年来,随着半导体工艺节点的递进,对于沟槽刻蚀的深度负载效应的控制要求越来越高。特别对于浅沟槽隔离刻蚀(Shallow Trench Isolation-ETching,STI-ET),这种负载效应会影响到半导体器件的电性结果。由于反应物消耗和扩散的基本物理原理的存在,这种负载效应很难通过普通的刻蚀过程的工艺参数的简单调节来根除,特别当节点继续微缩时,该负载效应也持续增大,给刻蚀工艺带来很大的挑战。传统技术中对晶圆进行沟槽刻蚀之后,产生的微负载效应如图1所示,其中,在晶圆100中,自上到下依次为光阻101,掩膜层102,氧化硅层103,基底硅104,并且晶圆100还包括小开口区域110和大开口区域120。Generally, for the trench etching of different opening sizes on the wafer, there is a certain difference in the depth after the etching is completed. The micro-loading effect is the rate of volatilization of the by-product of the etching process. Caused by the difference in etching aspect ratio. In recent years, with the advancement of semiconductor process nodes, the control requirements for the deep load effect of trench etching have become higher and higher. Especially for Shallow Trench Isolation-ETching (STI-ET), this loading effect affects the electrical results of semiconductor devices. Due to the existence of the basic physical principles of reactant consumption and diffusion, this loading effect is difficult to eradicate by simple adjustment of the process parameters of the ordinary etching process, especially when the node continues to shrink, the load effect continues to increase, giving The etching process poses great challenges. After the trench etching of the wafer in the conventional technology, the micro load effect is as shown in FIG. 1 , wherein in the wafer 100, the photoresist 101, the mask layer 102, and the silicon oxide layer are sequentially in order from top to bottom. 103, the base silicon 104, and the wafer 100 further includes a small opening area 110 and a large opening area 120.
针对传统工艺中的上述问题,有人提出了改进方案。在浅沟槽刻蚀进行到一定深度之后,通过选择性地在大开口区域120生长硅来实现负载效应的弥补,后续再进行浅沟槽刻蚀,达到目标深度。但此改进方案工序繁杂,不仅包括刻蚀工序,而且包括外延生长等一系列工序,特别是其需要选择性进行外延生长的方法过于繁冗。这样,大大延长了加工生产周期,增加了生产成本。In response to the above problems in the conventional process, an improvement scheme has been proposed. After the shallow trench etching is performed to a certain depth, the load effect is compensated by selectively growing silicon in the large opening region 120, and then shallow trench etching is performed to reach the target depth. However, this modification scheme is complicated, and includes not only an etching process but also a series of processes such as epitaxial growth, and in particular, the method of selectively performing epitaxial growth is too cumbersome. In this way, the processing cycle is greatly extended and the production cost is increased.
综上所述,如何提供一种简单有效的减小沟槽刻蚀微负载效应的刻 蚀方法是一个亟待解决的问题。In summary, how to provide a simple and effective way to reduce the micro-loading effect of trench etching The eclipse method is an urgent problem to be solved.
发明内容Summary of the invention
基于此,有必要提供一种能够有效降低晶圆沟槽刻蚀深度微负载效应的刻蚀方法。Based on this, it is necessary to provide an etching method capable of effectively reducing the micro-loading effect of the wafer trench etching depth.
为实现本发明目的提供的一种控制浅沟槽深度微负载效应的刻蚀方法,包括以下步骤:对进入工艺腔室的晶圆进行掩膜层刻蚀,直至所述晶圆上的开口接触到所述晶圆的基底硅;向所述工艺腔室中通入沉积气体,进行沉积反应,在所述晶圆上沉积一层对后续刻蚀起阻挡作用的类聚合物膜层;向所述工艺腔室中通入惰性气体,在等离子体激发条件下对所述类聚合物膜层进行处理;对所述晶圆进行浅沟槽刻蚀工艺直至预设深度。An etching method for controlling shallow trench depth micro-loading effect provided for the purpose of the present invention includes the following steps: mask etching a wafer entering a process chamber until an opening on the wafer contacts Substrate silicon to the wafer; depositing a deposition gas into the process chamber to perform a deposition reaction, depositing a polymer-like film layer on the wafer that blocks the subsequent etching; The inert gas is introduced into the process chamber, and the polymer film layer is processed under plasma excitation conditions; the wafer is subjected to a shallow trench etching process to a predetermined depth.
其中,所述对后续刻蚀起阻挡作用的类聚合物膜层为具有碳和氢成分的类聚合物膜层。Wherein, the polymer-like film layer which blocks the subsequent etching is a polymer-like film layer having carbon and hydrogen components.
其中,所述对后续刻蚀起阻挡作用的类聚合物膜层为SiO2类膜层。Wherein, the polymer-like film layer which blocks the subsequent etching is a SiO 2 -based film layer.
其中,在向所述工艺腔室中通入沉积气体,进行沉积反应,在所述晶圆上沉积一层对后续刻蚀起阻挡作用的类聚合物膜层的步骤中,所述类聚合物膜层的厚度为10埃~300埃。Wherein, in the step of depositing a deposition gas into the process chamber, performing a deposition reaction, and depositing a polymer-like film layer for blocking the subsequent etching on the wafer, the polymer The thickness of the film layer is from 10 angstroms to 300 angstroms.
其中,在对所述晶圆进行浅沟槽刻蚀工艺直至预设深度的步骤之后还包括以下步骤:将残留在所述晶圆的光阻灰化去除。Wherein, after the step of performing the shallow trench etching process on the wafer up to the preset depth, the method further comprises the step of: removing the photoresist remaining in the wafer by ashing.
其中,所述沉积气体为CH4或者为SiH4和O2的组合。Wherein, the deposition gas is CH 4 or a combination of SiH 4 and O 2 .
其中,所述惰性气体为Ar和/或He。Wherein, the inert gas is Ar and/or He.
其中,所述类聚合物膜层的厚度通过沉积时间进行控制。Wherein, the thickness of the polymer-like film layer is controlled by the deposition time.
其中,向所述工艺腔室中通入惰性气体,在等离子体激发条件下对所述类聚合物膜层进行处理,包括以下步骤:向所述工艺腔室中通入惰性气体;在等离子体激发条件下对所述类聚合物膜层进行处理;利用终 点检测法抓取所述晶圆的小尺寸开口区域暴露基底硅的瞬间,结束当前步骤,完成对所述类聚合物膜层处理的步骤。Wherein the inert gas is introduced into the process chamber, and the polymer film layer is treated under plasma excitation conditions, including the steps of: introducing an inert gas into the process chamber; Treating the polymer film layer under excitation conditions; The point detection method captures the moment when the small-sized open area of the wafer exposes the base silicon, ends the current step, and completes the step of processing the polymer-like film layer.
其中,所述对进入工艺腔室的晶圆进行掩膜层刻蚀的刻蚀工艺,直至所述晶圆上的开口接触到所述晶圆的基底硅的工艺步骤的工艺条件为:源功率为400~700W,偏压功率为100~300W,气压为3mt~10mt,刻蚀时间每步为10~40s,主气体为CF4和CH2F2,流量为50~350sccm,辅气体为O2、Ar、He,除氧气外的辅气体流量为50~150sccm,氧气流量为5~30scc;The process condition of performing a mask etching process on the wafer entering the process chamber until the opening on the wafer contacts the base silicon of the wafer is: source power It is 400-700W, the bias power is 100-300W, the air pressure is 3mt~10mt, the etching time is 10~40s per step, the main gas is CF 4 and CH 2 F 2 , the flow rate is 50-350sccm, and the auxiliary gas is O. 2 , Ar, He, the auxiliary gas flow rate other than oxygen is 50 ~ 150sccm, oxygen flow rate is 5 ~ 30scc;
所述向所述工艺腔室中通入沉积气体,进行沉积反应,在所述晶圆上沉积一层对后续刻蚀起阻挡作用的类聚合物膜层的工艺步骤的工艺条件为:源功率为100~1000W,偏压功率为0W~50W,沉积气体流量为10~500sccm,工艺气压为1~100mT,工艺时间为10~60s;The process condition of the process step of depositing a deposition gas into the process chamber to perform a deposition reaction and depositing a polymer-like film layer for blocking the subsequent etching on the wafer is: source power 100 to 1000W, bias power is 0W ~ 50W, deposition gas flow is 10 ~ 500sccm, process pressure is 1 ~ 100mT, process time is 10 ~ 60s;
所述向所述工艺腔室中通入惰性气体,在等离子体激发条件下对所述类聚合物膜层进行处理的工艺步骤的工艺条件为:源功率为100~1000W,偏压功率为50W~300W,Ar流量为10~500sccm,He流量为10~500sccm,工艺气压为1~100mT,工艺时间为10-60s;The process conditions for introducing the inert gas into the process chamber and treating the polymer film layer under plasma excitation conditions are: source power is 100-1000 W, bias power is 50 W ~300W, Ar flow rate is 10 ~ 500sccm, He flow is 10 ~ 500sccm, process pressure is 1 ~ 100mT, process time is 10-60s;
所述对所述晶圆进行浅沟槽刻蚀工艺直至预设深度的工艺步骤的工艺条件为:源功率为700~1200W,偏压功率为100~200W,气压为10mt~25mt,刻蚀时间为70~100s,主气体为HBr,流量为300-500sccm,辅气体为Cl2、NF3、SF6、N2、O2、HeO2中的至少一种,流量为5-50sccm。The process conditions for performing the shallow trench etching process on the wafer to a predetermined depth are: source power is 700-1200 W, bias power is 100-200 W, air pressure is 10 mt ~ 25 mt, etching time It is 70 to 100 s, the main gas is HBr, the flow rate is 300-500 sccm, and the auxiliary gas is at least one of Cl 2 , NF 3 , SF 6 , N 2 , O 2 , and HeO 2 , and the flow rate is 5-50 sccm.
其中,所述向所述工艺腔室中通入沉积气体,进行沉积反应,在所述晶圆上沉积一层对后续刻蚀起阻挡作用的类聚合物膜层的工艺步骤的工艺条件为:源功率为300~700W,偏压功率为0W,沉积气体流量为100~200sccm,工艺气压为10~30mT,工艺时间为10~30s;Wherein, the process conditions of the process step of depositing a deposition gas into the process chamber, performing a deposition reaction, and depositing a polymer-like film layer for blocking the subsequent etching on the wafer are: The source power is 300-700W, the bias power is 0W, the deposition gas flow rate is 100-200sccm, the process gas pressure is 10-30mT, and the process time is 10-30s;
所述向所述工艺腔室中通入惰性气体,在等离子体激发条件下对所述类聚合物膜层进行处理的工艺步骤的工艺条件为:源功率为 300~700W,偏压功率为100W~200W,Ar流量为100~200sccm,He流量为100~200sccm,工艺气压为5~20mT,工艺时间为10-20s。The process condition of the process step of injecting an inert gas into the process chamber to treat the polymer-like film layer under plasma excitation conditions is: source power is 300 to 700 W, bias power is 100 W to 200 W, Ar flow rate is 100 to 200 sccm, He flow rate is 100 to 200 sccm, process gas pressure is 5 to 20 mT, and process time is 10-20 s.
其中,所述将残留在所述晶圆的光阻灰化去除的工艺步骤的工艺条件为:源功率为700~1200W,偏压功率为0W,气压为10mt~30mt,刻蚀时间为80~120s,气体为O2,流量为200~500sccm。The process conditions of the process step of removing the photoresist from the wafer by the ashing process are: source power is 700-1200 W, bias power is 0 W, air pressure is 10 mt to 30 mt, and etching time is 80 ~. At 120 s, the gas is O 2 and the flow rate is 200 to 500 sccm.
本发明的有益效果包括:Advantageous effects of the present invention include:
本发明提供的一种控制浅沟槽深度微负载效应的刻蚀方法,通过增加类聚合物膜层的沉积步骤、以及对所沉积的类聚合物膜层的修饰步骤,可以起到与沟槽刻蚀微负载效应相反的结果,从而有效减小或者消除沟槽刻蚀中刻蚀深度微负载效应。而且,本发明提供的控制浅沟槽深度微负载效应的刻蚀方法,不用增加额外工序,操作简单,用时较短;且能够针对具体设备加工可通过时间等工艺参数进行调节控制,灵活性大。同时,采用该方法可以在一定程度上帮助平衡减轻晶圆不同开口区域的关键尺寸的差异。The invention provides an etching method for controlling the micro-load effect of shallow trench depth, which can be used to form a trench by adding a deposition step of a polymer-like film layer and a modification step of the deposited polymer-like film layer. Etching the opposite effect of the microloading effect effectively reduces or eliminates the etch depth microloading effect in the trench etch. Moreover, the etching method for controlling the micro-load effect of shallow trench depth provided by the invention does not need to add an additional process, is simple in operation, and has a short time; and can be adjusted and controlled by process parameters such as time for specific equipment processing, and has high flexibility. . At the same time, this method can help balance the difference in critical dimensions of different opening areas of the wafer to a certain extent.
附图说明DRAWINGS
图1为传统工艺沟槽刻蚀后的晶圆示意图;1 is a schematic view of a wafer after conventional trench etching;
图2为本发明一种控制浅沟槽深度微负载效应的刻蚀方法的一具体实施例的流程图;2 is a flow chart of a specific embodiment of an etching method for controlling a micro-load effect of a shallow trench depth according to the present invention;
图3为采用图2所示方法进行步骤S100时的晶圆结构示意图;3 is a schematic view showing the structure of a wafer when step S100 is performed by the method shown in FIG. 2;
图4为采用图2所示方法进行步骤S200时的晶圆结构示意图;4 is a schematic structural view of a wafer when step S200 is performed by the method shown in FIG. 2;
图5为采用图2所示方法进行步骤S300时的晶圆结构示意图;FIG. 5 is a schematic structural view of a wafer when step S300 is performed by using the method shown in FIG. 2;
图6为采用图2所示方法进行步骤S400时的晶圆结构示意图;6 is a schematic structural view of a wafer when step S400 is performed by the method shown in FIG. 2;
图7为本发明一种控制浅沟槽深度微负载效应的刻蚀方法的另一具体实施例的流程图。 7 is a flow chart of another embodiment of an etching method for controlling shallow trench depth microloading effects of the present invention.
具体实施方式detailed description
为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图对本发明实施例提供的控制浅沟槽深度微负载效应的刻蚀方法进行说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。In order to make the object, the technical solution and the advantages of the present invention more clearly, the etching method for controlling the shallow groove depth micro-load effect provided by the embodiment of the present invention will be described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
本发明实施例提供的控制浅沟槽深度微负载效应的刻蚀方法,如图2所述,包括以下步骤:The etching method for controlling the shallow trench depth micro-load effect provided by the embodiment of the present invention, as described in FIG. 2, includes the following steps:
S100,对进入工艺腔室的晶圆进行掩膜层刻蚀,直至所述晶圆上的开口接触到所述晶圆的基底硅。如图3所示,对进入工艺腔室的晶圆100的掩膜层102进行刻蚀,晶圆100上的开口被刻蚀至接触到基底硅,则完成掩膜层100的刻蚀。如图所示,在晶圆100中,自上到下依次为光阻层101,掩膜层102,氧化硅层103,基底硅104,其中所述掩膜层102为SIN类硬掩膜层。所述晶圆100还包括小开口区域110和大开口区域120。S100, performing mask etching on the wafer entering the process chamber until the opening on the wafer contacts the base silicon of the wafer. As shown in FIG. 3, the mask layer 102 of the wafer 100 entering the process chamber is etched, and the opening on the wafer 100 is etched to contact the base silicon to complete the etching of the mask layer 100. As shown in the figure, in the wafer 100, from top to bottom, there are a photoresist layer 101, a mask layer 102, a silicon oxide layer 103, and a base silicon 104, wherein the mask layer 102 is a SIN type hard mask layer. . The wafer 100 further includes a small opening area 110 and a large opening area 120.
S200,向所述工艺腔室中通入沉积气体,进行沉积反应,在所述晶圆上沉积一层对后续刻蚀起阻挡作用的类聚合物膜层。如图4所示,在晶圆100表面的光阻层101上方、掩膜层102刻蚀后在开口区域(小开口区域110和大开口区域120)露出的基底硅上方、以及开口侧壁上都沉积上一层类聚合物膜层105,所述类聚合物膜层105是对后续刻蚀具有一定阻挡作用的类聚合物膜层。S200, a deposition gas is introduced into the process chamber to perform a deposition reaction, and a polymer-like film layer that blocks the subsequent etching is deposited on the wafer. As shown in FIG. 4, above the photoresist layer 101 on the surface of the wafer 100, after the mask layer 102 is etched, over the exposed regions (the small opening regions 110 and the large opening regions 120) are exposed above the base silicon, and on the opening sidewalls. A layer of polymer-like film 105 is deposited on the polymer film layer 105, which is a polymer-like film layer which has a certain barrier effect on subsequent etching.
此处需说明的是,所述类聚合物膜层105的沉积过程中,同样开口面积的小开口区域110和大开口区域120中,小开口区域110的接触总面积(即,所有小开口区域110的底部和侧壁的可供沉积类聚合物膜层105的面积之和)大于大开口区域120的接触总面积(即,所有大开口区域120的底部和侧壁的可供沉积类聚合物膜层105的面积之和)。因 此,在大开口区域120所沉积的所述类聚合物膜层105的厚度大于小开口区域110所沉积的所述类聚合物膜层105的厚度。从而在后续沟槽刻蚀中起到互补的作用。而且沉积不仅发生在开口底部,根据沉积过程的等离子反应条件的偏压值的不同,开口侧壁也会沉积上不同厚度的类聚合物膜层105,一般地,开口区域越大,其侧壁所沉积的类聚合物膜层105会越厚。该差异也会一定程度上平衡沟槽刻蚀过程的开口尺寸的负载效应。Here, the total contact area of the small opening area 110 (ie, all the small opening areas) in the small opening area 110 and the large opening area 120 of the same opening area during the deposition of the polymer-like film layer 105 (ie, all small opening areas) The sum of the areas of the bottom of the layer 110 and the sidewalls of the polymer-depositable polymer film layer 105 is greater than the total contact area of the large opening region 120 (i.e., the bottom of the large opening region 120 and the sidewalls of the depositable polymer) The sum of the areas of the film layers 105). Cause Thus, the thickness of the polymer-like film layer 105 deposited in the large opening region 120 is greater than the thickness of the polymer-like film layer 105 deposited by the small opening region 110. Thereby playing a complementary role in the subsequent trench etching. Moreover, the deposition does not occur only at the bottom of the opening. According to the bias value of the plasma reaction conditions during the deposition process, the sidewalls of the opening are also deposited with a polymer film layer 105 of different thickness. Generally, the larger the opening area, the side wall thereof The thicker the deposited polymer-like film layer 105 will be. This difference also balances the loading effect of the opening size of the trench etching process to some extent.
S300,向所述工艺腔室中通入惰性气体,在等离子体激发条件下对所述类聚合物膜层进行处理。如图5所示,利用惰性气体在等离子体激发条件下对所述类聚合物膜层105进行处理后,在晶圆100所有位置的所述类聚合物膜层105都变薄或者消失。此处需要说明的是,所述处理为对类聚合物膜层105进行修饰处理,使膜层变薄或者消失。其主要为物理性轰击,在不同开口处其对沉积的类聚合物膜层105的消耗速度几近相同。因此,进行本步骤的处理后,大开口区域120沉积的类聚合物膜层105厚度依然大于小开口区域110沉积的类聚合物膜层105的厚度。且经本步骤的处理后,所保留下来的沉积厚度与开口的大小成正比。同时,本步骤中也可以加入少量的其他辅助气体进行工艺加工,如O2,N2,H2等。S300, an inert gas is introduced into the process chamber, and the polymer-like film layer is treated under plasma excitation conditions. As shown in FIG. 5, after the polymer-based film layer 105 is treated under an inert gas atmosphere under plasma excitation conditions, the polymer-like film layer 105 at all positions of the wafer 100 is thinned or disappears. It should be noted here that the treatment is to modify the polymer-like film layer 105 to make the film layer thin or disappear. It is primarily a physical bombardment where the rate of consumption of the deposited polymer-like film layer 105 is approximately the same at different openings. Therefore, after the treatment of this step, the thickness of the polymer-like film layer 105 deposited in the large opening region 120 is still greater than the thickness of the polymer-like film layer 105 deposited in the small opening region 110. And after the treatment of this step, the thickness of the deposited deposit is proportional to the size of the opening. At the same time, a small amount of other auxiliary gas may be added in the step for processing, such as O 2 , N 2 , H 2 and the like.
S400,对所述晶圆进行浅沟槽刻蚀工艺直至预设深度。对经过上述S300和S400两步工艺之后,继续对晶圆100进行浅沟槽刻蚀的工艺,直至到预设深度。所述预设深度,是根据半导体设备的实际需求设定的刻蚀深度。此处需要说明的是,由于有类聚合物膜层105的阻挡,大开口区域120的刻蚀速度相对原始状态会有所放慢,这样可以使小开口区域110与大开口区域120的刻蚀深度相同或者相差不多,如图6所示。S400, performing a shallow trench etching process on the wafer to a preset depth. After the two-step process of S300 and S400 described above, the process of shallow trench etching of the wafer 100 is continued until a predetermined depth is reached. The preset depth is an etch depth set according to actual needs of the semiconductor device. It should be noted here that due to the blocking of the polymer-like film layer 105, the etching speed of the large opening region 120 may be slowed relative to the original state, so that the small opening region 110 and the large opening region 120 may be etched. The depth is the same or similar, as shown in Figure 6.
本发明实施例提供的控制浅沟槽深度微负载效应的刻蚀方法,通过增加类聚合物膜层的沉积步骤,以及对该沉积层修饰的步骤,可以起到 与沟槽刻蚀微负载效应相反的结果,从而有效减小或者消除沟槽刻蚀中刻蚀深度微负载效应。而且,本发明实施例提供的控制浅沟槽深度微负载效应的刻蚀方法,不用增加额外工序,操作简单,用时较短,且针对具体设备加工可通过时间等工艺参数进行调节控制,灵活性大。同时,利用该方法可以在一定程度上帮助平衡减轻晶圆不同开口区域的关键尺寸的差异。The etching method for controlling the micro-load effect of the shallow trench depth provided by the embodiment of the present invention can be performed by adding a deposition step of the polymer-like film layer and a step of modifying the deposited layer. The opposite result of the trench etch microloading effect, thereby effectively reducing or eliminating the etch depth microloading effect in the trench etch. Moreover, the etching method for controlling the shallow micro-load effect of the shallow trench provided by the embodiment of the invention does not need to add an additional process, is simple in operation, has a short time, and can be adjusted and controlled by time and other process parameters for specific equipment processing, and flexibility. Big. At the same time, this method can help balance the difference in key dimensions of different opening areas of the wafer to a certain extent.
在其中一个实施例中,所述对后续刻蚀起阻挡作用的类聚合物膜层为具有碳和氢成分的类聚合物膜层。主要成分为碳和氢的类聚合物膜层105相当于光阻,对后续的刻蚀起到阻挡作用,从而相当于减慢了刻蚀速度,又由于大开口区域120沉积的类聚合物膜层的厚度较大,因此对大开口区域120刻蚀速度的减慢效果更加明显。In one embodiment, the polymer-like film layer that blocks the subsequent etching is a polymer-like film layer having carbon and hydrogen components. The polymer-like film layer 105 whose main component is carbon and hydrogen is equivalent to a photoresist, which acts as a barrier to subsequent etching, thereby equivalent to a slowing of the etching rate, and a polymer film deposited due to the large opening region 120. The thickness of the layer is large, so the effect of slowing down the etching speed of the large opening region 120 is more pronounced.
在本发明的一个实施例中,所述对后续刻蚀起一定阻挡作用的类聚合物膜层为SiO2类膜层。与主要成分为碳和氢的类聚合物膜层作用相同,SiO2类膜层也能起到相对减缓大开口区域120刻蚀速度的作用。In an embodiment of the invention, the polymer-like film layer which has a certain blocking effect on the subsequent etching is a SiO 2 -based film layer. Like the polymer-like film layer whose main components are carbon and hydrogen, the SiO 2 -type film layer can also play a role in relatively slowing the etching speed of the large opening region 120.
在其中一个实施例中,所述类聚合物膜层105的厚度为10埃~300埃。在其中一个实施例的控制浅沟槽深度微负载效应的刻蚀方法,如图7所示,还包括以下步骤:S500,将残留在所述晶圆的光阻灰化去除。In one embodiment, the polymer-like film layer 105 has a thickness of 10 angstroms to 300 angstroms. In one embodiment, the etching method for controlling the shallow trench depth micro-loading effect, as shown in FIG. 7, further includes the following steps: S500, removing the photoresist remaining in the wafer by ashing.
在其中一个实施例中,所述沉积气体为CH4或者为SiH4和O2的组合。使用气体CH4进行沉积,则可生成主要成分为碳和氢的类聚合物膜层,使用SiH4和O2气体组合作为沉积气体,则可生成SiO2类膜层,都可以起到相对减慢大开口区域刻蚀速度的效果。此处需要说明的是,其他可生成类似沉积膜层的气体组合在本发明其他实施例中也适用,如其他含碳和氢的气体。In one embodiment, the deposition gas is CH 4 or a combination of SiH 4 and O 2 . When the gas CH 4 is used for deposition, a polymer-like film layer mainly composed of carbon and hydrogen can be formed. When a combination of SiH 4 and O 2 gas is used as a deposition gas, a SiO 2 -type film layer can be formed, which can be relatively reduced. The effect of the etch rate in the slow open area. It should be noted here that other gas combinations which can produce a similar deposited film layer are also applicable in other embodiments of the invention, such as other carbon and hydrogen containing gases.
在其中一个实施例中,所述惰性气体为Ar和/或He。In one embodiment, the inert gas is Ar and/or He.
在其中一个实施例中,所述类聚合物膜层的厚度通过沉积时间进行控制。此处需要说明的是,所述类聚合物沉积时间可通过前期实验获得, 可通过先预设一个较短的沉积时间,在沟槽刻蚀完成后进行TEM切片分析,验证不同开口尺寸处的深度差异,如果差异仍较大,需增加沉积时间。如此反复进行,直至深度差异缩小至可接受的范围。此为本领域技术人员可直接根据描述进行的简单工艺试验,此处不再详细说明。In one embodiment, the thickness of the polymer-like film layer is controlled by deposition time. It should be noted here that the deposition time of the polymer-like polymer can be obtained through preliminary experiments. The TEM slice analysis can be performed after the trench etching is completed by presetting a short deposition time to verify the difference in depth at different opening sizes. If the difference is still large, the deposition time needs to be increased. This is repeated until the depth difference is reduced to an acceptable range. This is a simple process test that can be directly performed by a person skilled in the art according to the description, and will not be described in detail herein.
在本发明的其他实施例中,所述类聚合物膜层的厚度也可通过加工工艺的其他参数或者参数组合进行调节控制,如源功率、气压、以及气体流量等。In other embodiments of the invention, the thickness of the polymer-like film layer can also be adjusted and controlled by other parameters of the processing process or a combination of parameters, such as source power, gas pressure, and gas flow rate.
在本发明的其他实施例中,所述类聚合物的处理也可通过加工工艺的其他参数或者参数组合进行调节控制,如工艺加工时间、源功率、气压、以及气体流量等。In other embodiments of the invention, the treatment of the polymer-like polymer can also be controlled by other parameters or combinations of parameters of the processing process, such as process time, source power, gas pressure, and gas flow rate.
较佳地,在其中一个实施例中,步骤S300,包括以下步骤:Preferably, in one embodiment, step S300 includes the following steps:
S310,向所述工艺腔室中通入惰性气体;S310, introducing an inert gas into the process chamber;
S320,在等离子体激发条件下对所述类聚合物膜层进行处理;S320, treating the polymer film layer under plasma excitation conditions;
S330,利用终点检测法抓取所述晶圆的小尺寸开口区域暴露基底硅的瞬间,结束当前步骤,完成对所述类聚合物膜层处理的步骤。S330, using an endpoint detection method to capture the instant that the small-sized open area of the wafer exposes the base silicon, ending the current step, and completing the step of processing the polymer-like film layer.
本发明实施例可准确掌握类聚合物处理的时间,使工艺加工更加准确,同时也可减小成本,提高生产效率。The embodiment of the invention can accurately grasp the time of the polymer-like treatment, make the process processing more accurate, and at the same time reduce the cost and improve the production efficiency.
在本发明的其中一个实施例中,所述对进入工艺腔室的晶圆进行掩膜层刻蚀的刻蚀工艺,直至所述晶圆上的开口接触到所述晶圆的基底硅的工艺步骤(即,步骤S100)的工艺条件为:源功率为400~700W,偏压功率为100~300W,气压为3mt~10mt,刻蚀时间每步为10~40s,主气体为CF4和CH2F2,流量为50~350sccm,辅气体为O2、Ar、He,除氧气外的辅气体流量为50~150sccm,氧气流量为5~30sccm。In one embodiment of the present invention, the etching process for mask etching of a wafer entering a process chamber until the opening on the wafer contacts the base silicon of the wafer The process conditions of the step (ie, step S100) are: source power is 400-700 W, bias power is 100-300 W, air pressure is 3 mt to 10 mt, etching time is 10-40 s, and main gas is CF 4 and CH. 2 F 2 , the flow rate is 50-350 sccm, the auxiliary gas is O 2 , Ar, He, the auxiliary gas flow rate other than oxygen is 50-150 sccm, and the oxygen flow rate is 5-30 sccm.
所述向所述工艺腔室中通入沉积气体,进行沉积反应,在所述晶圆上沉积一层对后续刻蚀起阻挡作用的类聚合物膜层的工艺步骤(即,步骤S200)的工艺条件为:源功率为100~1000W,偏压功率为0W~50W, 沉积气体流量为10~500sccm,工艺气压为1~100mT,工艺时间为10~60s。Performing a process step of depositing a deposition gas into the process chamber to perform a deposition reaction, depositing a polymer-like film layer blocking the subsequent etching on the wafer (ie, step S200) The process conditions are: the source power is 100-1000W, and the bias power is 0W-50W. The deposition gas flow rate is 10 to 500 sccm, the process gas pressure is 1 to 100 mT, and the process time is 10 to 60 s.
所述向所述工艺腔室中通入惰性气体,在等离子体激发条件下对所述类聚合物膜层进行处理的工艺步骤(即,步骤S300)的工艺条件为:源功率为100~1000W,偏压功率为50W~300W,Ar流量为10~500sccm,He流量为10~500sccm,工艺气压为1~100mT,工艺时间为10-60s。The process step of introducing an inert gas into the process chamber to process the polymer-like film layer under plasma excitation conditions (ie, step S300) is: source power is 100-1000W The bias power is 50W to 300W, the Ar flow rate is 10 to 500 sccm, the He flow rate is 10 to 500 sccm, the process gas pressure is 1 to 100 mT, and the process time is 10-60 s.
所述对所述晶圆进行浅沟槽刻蚀工艺直至预设深度的工艺步骤(即,步骤S400)的工艺条件为:源功率为700~1200W,偏压功率为100~200W,气压为10mt~25mt,刻蚀时间为70~100s,主气体为HBr,流量为300-500sccm,辅气体为Cl2、NF3、SF6、N2、O2、HeO2中的至少一种,流量为5-50sccm。The process conditions for performing the shallow trench etching process on the wafer to a predetermined depth (ie, step S400) are: source power is 700-1200 W, bias power is 100-200 W, and air pressure is 10 mt. ~25mt, etching time is 70-100s, main gas is HBr, flow rate is 300-500sccm, auxiliary gas is at least one of Cl 2 , NF 3 , SF 6 , N 2 , O 2 , HeO 2 , flow rate is 5-50 sccm.
在本发明的其中一个实施例中,所述向所述工艺腔室中通入沉积气体,进行沉积反应,在所述晶圆上沉积一层对后续刻蚀起阻挡作用的类聚合物膜层的工艺步骤(即,步骤S200)的工艺条件为:源功率为300~700W,偏压功率为0W,沉积气体流量为100~200sccm,工艺气压为10~30mT,工艺时间为10~30s。In one embodiment of the present invention, the deposition gas is introduced into the process chamber to perform a deposition reaction, and a polymer-like film layer for blocking subsequent etching is deposited on the wafer. The process conditions of the process step (ie, step S200) are: source power is 300-700 W, bias power is 0 W, deposition gas flow is 100-200 sccm, process gas pressure is 10-30 mT, and process time is 10-30 s.
所述向所述工艺腔室中通入惰性气体,在等离子体激发条件下对所述类聚合物膜层进行处理的工艺步骤(即,步骤S300)的工艺条件为:源功率为300~700W,偏压功率为100W~200W,Ar流量为100~200sccm,He流量为100~200sccm,工艺气压为5~20mT,工艺时间为10-20s。The process condition that the inert gas is introduced into the process chamber to process the polymer-like film layer under plasma excitation conditions (ie, step S300) is: source power is 300-700W The bias power is 100 W to 200 W, the Ar flow rate is 100 to 200 sccm, the He flow rate is 100 to 200 sccm, the process gas pressure is 5 to 20 mT, and the process time is 10-20 s.
在本发明的其中一个实施例中,所述将残留在所述晶圆的光阻灰化去除的工艺步骤(即,步骤S500)的工艺条件为:源功率为700~1200W,偏压功率为0W,气压为10mt~30mt,刻蚀时间为80~120s,气体为氧气,流量为200~500sccm。In one embodiment of the present invention, the process condition of removing the photoresist ashing removal of the wafer (ie, step S500) is as follows: the source power is 700-1200 W, and the bias power is 0W, the gas pressure is 10 mt to 30 mt, the etching time is 80 to 120 s, the gas is oxygen, and the flow rate is 200 to 500 sccm.
以上所述实施例仅表达了本发明的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对本发明专利范围的限制。应当指出的 是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。 The above-mentioned embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. Should be pointed out It is to be understood that those skilled in the art can make various modifications and improvements without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims (12)

  1. 一种控制浅沟槽深度微负载效应的刻蚀方法,其特征在于,包括以下步骤:An etching method for controlling a micro-load effect of a shallow trench depth, comprising the steps of:
    对进入工艺腔室的晶圆进行掩膜层刻蚀,直至所述晶圆上的开口接触到所述晶圆的基底硅;Performing mask etching on the wafer entering the process chamber until the opening on the wafer contacts the base silicon of the wafer;
    向所述工艺腔室中通入沉积气体,进行沉积反应,在所述晶圆上沉积一层对后续刻蚀起阻挡作用的类聚合物膜层;Depositing a deposition gas into the process chamber to perform a deposition reaction, depositing on the wafer a layer of a polymer-like film that blocks the subsequent etching;
    向所述工艺腔室中通入惰性气体,在等离子体激发条件下对所述类聚合物膜层进行处理;Introducing an inert gas into the process chamber to treat the polymer-like film layer under plasma excitation conditions;
    对所述晶圆进行浅沟槽刻蚀工艺直至预设深度。The wafer is subjected to a shallow trench etch process up to a predetermined depth.
  2. 根据权利要求1所述的控制浅沟槽深度微负载效应的刻蚀方法,其特征在于,所述对后续刻蚀起阻挡作用的类聚合物膜层为具有碳和氢成分的类聚合物膜层。The etching method for controlling shallow trench depth micro-loading effect according to claim 1, wherein the polymer-like film layer which blocks the subsequent etching is a polymer film having carbon and hydrogen components. Floor.
  3. 根据权利要求1所述的控制浅沟槽深度微负载效应的刻蚀方法,其特征在于,所述对后续刻蚀起阻挡作用的类聚合物膜层为SiO2类膜层。The etching method for controlling the shallow trench depth micro-loading effect according to claim 1, wherein the polymer-like film layer that blocks the subsequent etching is a SiO 2 -based film layer.
  4. 根据权利要求2或3所述的控制浅沟槽深度微负载效应的刻蚀方法,其特征在于,在向所述工艺腔室中通入沉积气体,进行沉积反应,在所述晶圆上沉积一层对后续刻蚀起阻挡作用的类聚合物膜层的步骤中,所述类聚合物膜层的厚度为10埃~300埃。The etching method for controlling the shallow trench depth micro-loading effect according to claim 2 or 3, wherein a deposition gas is introduced into the process chamber, a deposition reaction is performed, and deposition is performed on the wafer. In the step of a polymer-like film layer which blocks the subsequent etching, the polymer-like film layer has a thickness of 10 angstroms to 300 angstroms.
  5. 根据权利要求4所述的控制浅沟槽深度微负载效应的刻蚀方法,其特征在于,在对所述晶圆进行浅沟槽刻蚀工艺直至预设深度的步骤之后还包括以下步骤: The etching method for controlling shallow trench depth micro-loading effect according to claim 4, wherein the step of performing a shallow trench etching process on the wafer up to a preset depth further comprises the following steps:
    将残留在所述晶圆的光阻灰化去除。The photoresist remaining in the wafer is removed by ashing.
  6. 根据权利要求4所述的控制浅沟槽深度微负载效应的刻蚀方法,其特征在于,所述沉积气体为CH4或者为SiH4和O2的组合。The etching method for controlling shallow trench depth micro-loading effect according to claim 4, wherein the deposition gas is CH 4 or a combination of SiH 4 and O 2 .
  7. 根据权利要求4所述的控制浅沟槽深度微负载效应的刻蚀方法,其特征在于,所述惰性气体为Ar和/或He。The etching method for controlling shallow trench depth microloading effect according to claim 4, wherein the inert gas is Ar and/or He.
  8. 根据权利要求4所述的控制浅沟槽深度微负载效应的刻蚀方法,其特征在于,所述类聚合物膜层的厚度通过沉积时间进行控制。The etching method for controlling shallow trench depth micro-loading effect according to claim 4, wherein the thickness of the polymer-like film layer is controlled by deposition time.
  9. 根据权利要求4所述的控制浅沟槽深度微负载效应的刻蚀方法,其特征在于,向所述工艺腔室中通入惰性气体,在等离子体激发条件下对所述类聚合物膜层进行处理,包括以下步骤:The etching method for controlling shallow trench depth micro-loading effect according to claim 4, wherein an inert gas is introduced into the process chamber, and the polymer film layer is applied under plasma excitation conditions. Processing, including the following steps:
    向所述工艺腔室中通入惰性气体;Introducing an inert gas into the process chamber;
    在等离子体激发条件下对所述类聚合物膜层进行处理;Treating the polymer-like film layer under plasma excitation conditions;
    利用终点检测法抓取所述晶圆的小尺寸开口区域暴露基底硅的瞬间,结束当前步骤,完成对所述类聚合物膜层处理的步骤。The end point detection method is used to grab the instant that the small-sized open area of the wafer exposes the base silicon, and the current step is completed to complete the step of treating the polymer-like film layer.
  10. 根据权利要求7所述的控制浅沟槽深度微负载效应的刻蚀方法,其特征在于,The etching method for controlling the shallow trench depth microloading effect according to claim 7, wherein
    所述对进入工艺腔室的晶圆进行掩膜层刻蚀的刻蚀工艺,直至所述晶圆上的开口接触到所述晶圆的基底硅的工艺步骤的工艺条件为:The process conditions for performing a mask etch process on the wafer entering the process chamber until the opening on the wafer contacts the base silicon of the wafer are:
    源功率为400~700W,偏压功率为100~300W,气压为3mt~10mt,刻蚀时间每步为10~40s,主气体为CF4和CH2F2,流量为50~350sccm,辅气体为O2、Ar、He,除氧气外的辅气体流量为50~150sccm,氧气流量为5~30scc;The source power is 400-700W, the bias power is 100-300W, the air pressure is 3mt~10mt, the etching time is 10~40s per step, the main gas is CF 4 and CH 2 F 2 , the flow rate is 50-350sccm, auxiliary gas O 2 , Ar, He, the auxiliary gas flow rate other than oxygen is 50 ~ 150sccm, oxygen flow rate is 5 ~ 30scc;
    所述向所述工艺腔室中通入沉积气体,进行沉积反应,在所述晶圆上沉 积一层对后续刻蚀起阻挡作用的类聚合物膜层的工艺步骤的工艺条件为:Depositing a deposition gas into the process chamber, performing a deposition reaction, sinking on the wafer The process conditions for the process steps of stacking a polymer-like film layer that blocks the subsequent etching are:
    源功率为100~1000W,偏压功率为0W~50W,沉积气体流量为10~500sccm,工艺气压为1~100mT,工艺时间为10~60s;The source power is 100-1000W, the bias power is 0W-50W, the deposition gas flow rate is 10-500sccm, the process gas pressure is 1-100mT, and the process time is 10-60s;
    所述向所述工艺腔室中通入惰性气体,在等离子体激发条件下对所述类聚合物膜层进行处理的工艺步骤的工艺条件为:The process conditions of the process step of introducing an inert gas into the process chamber and treating the polymer-like film layer under plasma excitation conditions are:
    源功率为100~1000W,偏压功率为50W~300W,Ar流量为10~500sccm,He流量为10~500sccm,工艺气压为1~100mT,工艺时间为10-60s;The source power is 100-1000W, the bias power is 50W-300W, the Ar flow rate is 10-500sccm, the He flow rate is 10-500sccm, the process air pressure is 1-100mT, and the process time is 10-60s;
    所述对所述晶圆进行浅沟槽刻蚀工艺直至预设深度的工艺步骤的工艺条件为:The process conditions for performing the shallow trench etching process on the wafer up to a preset depth are:
    源功率为700~1200W,偏压功率为100~200W,气压为10mt~25mt,刻蚀时间为70~100s,主气体为HBr,流量为300-500sccm,辅气体为Cl2、NF3、SF6、N2、O2、HeO2中的至少一种,流量为5-50sccm。The source power is 700-1200W, the bias power is 100-200W, the air pressure is 10mt~25mt, the etching time is 70-100s, the main gas is HBr, the flow rate is 300-500sccm, and the auxiliary gas is Cl 2 , NF 3 , SF. 6. At least one of N 2 , O 2 , and HeO 2 having a flow rate of 5 to 50 sccm.
  11. 根据权利要求10所述的控制浅沟槽深度微负载效应的刻蚀方法,其特征在于,The etching method for controlling the shallow trench depth micro-load effect according to claim 10, wherein
    所述向所述工艺腔室中通入沉积气体,进行沉积反应,在所述晶圆上沉积一层对后续刻蚀起阻挡作用的类聚合物膜层的工艺步骤的工艺条件为:The process conditions for introducing a deposition gas into the process chamber to perform a deposition reaction and depositing a polymer-like film layer for blocking the subsequent etching on the wafer are:
    源功率为300~700W,偏压功率为0W,沉积气体流量为100~200sccm,工艺气压为10~30mT,工艺时间为10~30s;The source power is 300-700W, the bias power is 0W, the deposition gas flow rate is 100-200sccm, the process gas pressure is 10-30mT, and the process time is 10-30s;
    所述向所述工艺腔室中通入惰性气体,在等离子体激发条件下对所述类聚合物膜层进行处理的工艺步骤的工艺条件为:The process conditions of the process step of introducing an inert gas into the process chamber and treating the polymer-like film layer under plasma excitation conditions are:
    源功率为300~700W,偏压功率为100W~200W,Ar流量为100~200sccm,He流量为100~200sccm,工艺气压为5~20mT,工艺时间为10-20s。The source power is 300-700 W, the bias power is 100 W-200 W, the Ar flow rate is 100-200 sccm, the He flow rate is 100-200 sccm, the process gas pressure is 5-20 mT, and the process time is 10-20 s.
  12. 根据权利要求5所述的控制浅沟槽深度微负载效应的刻蚀方法,其特征在于,所述将残留在所述晶圆的光阻灰化去除的工艺步骤的工艺条件 为:The etching method for controlling shallow trench depth micro-loading effect according to claim 5, wherein the process condition of the process step of removing the photoresist from the wafer is removed for:
    源功率为700~1200W,偏压功率为0W,气压为10mt~30mt,刻蚀时间为80~120s,气体为O2,流量为200~500sccm。 The source power is 700-1200 W, the bias power is 0 W, the air pressure is 10 mt to 30 mt, the etching time is 80-120 s, the gas is O 2 , and the flow rate is 200-500 sccm.
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