CN111834204B - Preparation method of semiconductor structure - Google Patents
Preparation method of semiconductor structure Download PDFInfo
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- CN111834204B CN111834204B CN202010884286.XA CN202010884286A CN111834204B CN 111834204 B CN111834204 B CN 111834204B CN 202010884286 A CN202010884286 A CN 202010884286A CN 111834204 B CN111834204 B CN 111834204B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 103
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 47
- 238000005530 etching Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 72
- 230000008569 process Effects 0.000 claims description 59
- 239000007789 gas Substances 0.000 claims description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 31
- 229920005591 polysilicon Polymers 0.000 claims description 29
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- 230000003667 anti-reflective effect Effects 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 5
- 229910001882 dioxygen Inorganic materials 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052684 Cerium Inorganic materials 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052735 hafnium Inorganic materials 0.000 claims description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 289
- 230000007547 defect Effects 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 2
- CPELXLSAUQHCOX-UHFFFAOYSA-M Bromide Chemical compound [Br-] CPELXLSAUQHCOX-UHFFFAOYSA-M 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- -1 hydrogen ions Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000005049 silicon tetrachloride Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Abstract
The invention provides a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate, forming a shallow trench isolation structure in the substrate, and sequentially forming a polycrystalline silicon layer, a hard mask layer, an anti-reflection layer and a graphical photoresist layer on the substrate; hardening the surface of the patterned photoresist layer; forming an oxide layer on the surface of the patterned photoresist layer, hardening the oxide layer, and repeating the steps for a plurality of times; etching the anti-reflection layer by taking the patterned photoresist layer as a mask to form a patterned anti-reflection layer; etching the hard mask layer by taking the patterned photoresist layer as a mask to form a patterned hard mask layer, and removing the patterned photoresist layer; and etching the polycrystalline silicon layer by taking the patterned hard mask layer as a mask. The invention ensures that the hard mask layer has a certain thickness and a complete top appearance.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor structure.
Background
In CMOS graphic sensor platform technology, ion implantation, which is a method of introducing a controllable amount of impurities into a substrate to change its electrical properties, is required after etching a polysilicon layer. When the substrate is subjected to ion implantation, a thick hard mask layer needs to be reserved on the polycrystalline silicon layer to serve as a barrier layer so as to prevent the polycrystalline silicon layer from being influenced by the ion implantation, and therefore the hard mask layer needs to be ensured to have certain thickness and complete top appearance after the polycrystalline silicon layer is etched.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor structure, which is used for ensuring that a hard mask layer has a certain thickness and a complete top appearance.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor structure, comprising:
providing a substrate, forming a shallow trench isolation structure in the substrate, and sequentially forming a polycrystalline silicon layer, a hard mask layer, an anti-reflection layer and a graphical photoresist layer on the substrate;
hardening the surface of the patterned photoresist layer;
forming an oxide layer on the surface of the patterned photoresist layer, hardening the oxide layer, and repeating the steps for a plurality of times;
etching the anti-reflection layer by using the patterned photoresist layer as a mask to form a patterned anti-reflection layer;
carrying out hardening treatment on the surface of the patterned photoresist layer and the surface of the patterned anti-reflection layer;
forming an oxidation layer on the surface of the patterned photoresist layer and the surface of the patterned anti-reflection layer, carrying out hardening treatment, and repeating the steps for a plurality of times;
etching the hard mask layer by taking the patterned photoresist layer as a mask to form a patterned hard mask layer, and removing the patterned photoresist layer;
and etching the polycrystalline silicon layer by taking the graphical hard mask layer as a mask.
Optionally, after the hard mask layer is etched, the patterned hard mask layer is laterally etched to narrow the patterned hard mask layer.
Optionally, the etching gas for performing lateral etching on the hard mask layer includes carbon tetrafluoride and trifluoromethane.
Optionally, the hard mask layer is a stack of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.
Optionally, a plasma process is used for hardening.
Optionally, the process gas of the plasma process is hydrogen bromide gas.
Optionally, the material of the oxide layer includes silicon dioxide.
Optionally, the polysilicon layer is etched by a dry etching process, and process gases of the dry etching process include hydrogen bromide gas and oxygen gas.
Optionally, a dry plasma photoresist removing process is used to remove the patterned photoresist layer.
Optionally, the material of the anti-reflection layer includes one or more of silicon, carbon, nitrogen, zirconium, titanium, cerium, and hafnium.
The preparation method of the semiconductor structure provided by the invention comprises the steps of firstly, carrying out primary hardening on the surface of the patterned photoresist layer to enhance the etching resistance of the patterned photoresist layer and prevent the patterned photoresist layer from being excessively etched; secondly, forming an oxide layer on the surface of the patterned photoresist layer, hardening the oxide layer, and repeating the hardening treatment for a plurality of times to further enhance the etching resistance of the patterned photoresist layer and further prevent the patterned photoresist layer from being excessively etched; and after the anti-reflection layer is etched, repeatedly hardening and forming an oxide layer, enhancing the etching resistance of the patterned photoresist layer and the patterned anti-reflection layer, and ensuring that no defect exists on the top appearance of the hard mask layer after the polycrystalline silicon layer is etched and no polycrystalline silicon residue is generated on the substrate.
And after the hard mask layer is etched, the hard mask layer is transversely etched, so that the pattern of the etched polycrystalline silicon layer is consistent with the pattern of the graphical photoresist layer which is not cured, the integral structure is not changed in the process, and the process consistency is ensured.
Drawings
FIG. 1 is a schematic cross-sectional view of a top profile of a hard mask layer with defects after etching a polysilicon layer;
FIG. 2 is a schematic cross-sectional view of residues generated on a substrate after etching a polysilicon layer;
FIG. 3 is a flow chart illustrating the fabrication of a semiconductor structure according to one embodiment of the present invention;
FIG. 4A is a schematic cross-sectional view illustrating a hardened layer is not formed on the surface of the patterned photoresist layer according to an embodiment of the present invention;
FIG. 4B is a schematic cross-sectional view of a patterned photoresist layer after hardening and oxide layer formation according to an embodiment of the present invention;
FIG. 4C is a schematic cross-sectional view of the patterned photoresist layer and the patterned anti-reflective layer after hardening and forming an oxide layer according to an embodiment of the present invention;
FIG. 4D is a schematic cross-sectional view illustrating the formation of a patterned hard mask layer according to one embodiment of the present invention;
FIG. 4E is a schematic cross-sectional view illustrating the polysilicon layer etched according to an embodiment of the present invention;
wherein the reference numerals are:
101' -a substrate; 102' -shallow trench isolation structures; 103' -a patterned polysilicon layer; 104' -a patterned first silicon oxide layer; 105' -a patterned silicon nitride layer; 201' -residue; 101-a substrate; 102-shallow trench isolation structures; 103-a patterned polysilicon layer; 104-a patterned first silicon oxide layer; 105-a patterned silicon nitride layer; 401-a polysilicon layer; 402-a first silicon oxide layer; 403-a silicon nitride layer; 404-a second silicon dioxide layer; 405-an anti-reflection layer; 406-a patterned photoresist layer; 407-a hardened layer; 404A-a patterned second silicon oxide layer; 405A-a patterned anti-reflective layer.
Detailed Description
Referring to fig. 1, in the prior art, a polysilicon layer, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, an anti-reflection layer and a patterned photoresist layer are sequentially formed on a substrate 101', and the top of the patterned silicon nitride layer 105' has a defect after etching. Because there is a height difference between the shallow trench isolation structure 102 'in the substrate 101' and the plane of the substrate 101', there is a thickness difference in the coating thickness of the anti-reflective layer, and a large amount of etching of the anti-reflective layer is often required to ensure sufficient etching of the anti-reflective layer, which may cause defects in the top appearance of the patterned silicon nitride layer 105' after the patterned polysilicon layer 103 'and the patterned first silicon oxide layer 104' are formed.
Referring to fig. 2, in the prior art, when the etching amount of the anti-reflective layer is small, a residue 201 'is formed on the substrate 101' after the patterned polysilicon layer 103 'is formed, and the residue 201' is prone to cause electrical performance problems.
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 3 is a flowchart illustrating a manufacturing process of the semiconductor structure according to the present embodiment, and fig. 4A is a schematic cross-sectional view illustrating a hardened layer not formed on the surface of the patterned photoresist layer according to the present embodiment; fig. 4B is a schematic cross-sectional view of the patterned photoresist layer provided in this embodiment after the surface of the patterned photoresist layer is subjected to a hardening process and an oxide layer is formed, fig. 4C is a schematic cross-sectional view of the patterned photoresist layer provided in this embodiment and the surface of the patterned anti-reflection layer after the surface of the patterned anti-reflection layer is subjected to a hardening process and an oxide layer is formed, fig. 4D is a schematic cross-sectional view of the patterned hard mask layer provided in this embodiment after the patterned hard mask layer is formed, and fig. 4E is a schematic cross-sectional view of the polysilicon layer etched provided in this embodiment.
The invention provides a preparation method of a semiconductor structure, which is used for ensuring that a hard mask layer has a certain thickness and a complete top appearance. Please refer to fig. 3, which includes:
step S1: providing a substrate, forming a shallow trench isolation structure in the substrate, and sequentially forming a polycrystalline silicon layer, a hard mask layer, an anti-reflection layer and a graphical photoresist layer on the substrate;
step S2: hardening the surface of the patterned photoresist layer;
and step S3: forming an oxide layer on the surface of the patterned photoresist layer, hardening the oxide layer, and repeating the steps for a plurality of times;
and step S4: etching the anti-reflection layer by using the patterned photoresist layer as a mask to form a patterned anti-reflection layer;
step S5: carrying out hardening treatment on the surface of the patterned photoresist layer and the surface of the patterned anti-reflection layer;
step S6: forming an oxide layer on the surface of the patterned photoresist layer and the surface of the patterned anti-reflection layer, performing hardening treatment, and repeating the steps for a plurality of times;
step S7: etching the hard mask layer by taking the patterned photoresist layer as a mask to form a patterned hard mask layer, and removing the patterned photoresist layer;
step S8: and etching the polysilicon layer by using the patterned hard mask layer as a mask.
The method of fabricating the semiconductor structure of the present invention is described in more detail below with reference to schematic cross-sectional views, in which preferred embodiments of the invention are illustrated.
Referring to fig. 4A, step S1 is performed to provide a substrate 101, form a shallow trench isolation structure 102 in the substrate 101, and sequentially form a polysilicon layer 401, a hard mask layer, an anti-reflection layer 405, and a patterned photoresist layer 406 on the substrate 101. Shallow trench isolation structures 102 are formed in the substrate 101, a certain height difference exists between the shallow trench isolation structures 102 and the surface of the substrate 101, and the shallow trench isolation structures 102 are used for isolating different active regions in the substrate 101. A polysilicon layer 401 is formed on the substrate 101 and the shallow trench isolation structure 102, and the polysilicon layer 401 is used to form a high voltage region of the semiconductor device. A hard mask layer is formed on the polysilicon layer 401, the hard mask layer is a lamination of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer, specifically, a first silicon oxide layer 402, a silicon nitride layer 403 and a second silicon oxide layer 404 are sequentially formed on the polysilicon layer 401, and the hard mask layer is used as a barrier layer in the ion implantation in the subsequent etching process. An anti-reflection layer 405 is formed on the second silicon oxide layer 404, during exposure, due to the vertical sidewall surface formed by etching, reflected light enters the patterned photoresist layer 406 that does not need to be exposed, and a reflective cut is formed, the anti-reflection layer 405 is used for reducing the damage of the reflected light to the patterned photoresist layer 406, and the material of the anti-reflection layer 405 includes one or more of silicon, carbon, nitrogen, zirconium, titanium, cerium and hafnium. The patterned photoresist layer 406 is patterned by an exposure and development process, and the patterned photoresist layer 406 causes the antireflective layer 405 and the hard mask layer to form the same pattern after etching.
In the present embodiment, the shallow trench isolation structure 102 has a depth of
The polysilicon layer 401 has a thickness of
Hard maskLayer thickness of
The anti-reflective layer 405 has a thickness of
The patterned photoresist layer 406 has a thickness of
The shallow trench isolation structure 102 and the substrate 101 have defects at the height, and the difference between the heights is about
So that the anti-reflection layer 405 is applied to a thickness of about
The above-mentioned thickness, depth and height differences are practical.
Referring to fig. 4B, step S2 is performed: the surface of the patterned photoresist layer 406 is hardened by a plasma process. In the embodiment, the process gas of the plasma process adopts hydrogen bromide, and the flow rate of the hydrogen bromide gas is 50-150 SCCM, wherein SCCM is a flow unit and represents that the gas flow rate in 1 minute is 50-150 ml. Converting hydrogen bromide gas into bromide ions and hydrogen ions under the power of 800-1200W provided by an energy source of a plasma process, bombarding the surface of the patterned photoresist layer 406 with the bromide ions and the hydrogen ions, and performing initial hardening treatment on the surface of the patterned photoresist layer 406 for 5-10S to harden the surface of the patterned photoresist layer 406. The gas flow, the power of the energy source and the curing time are related to the thickness and height difference of the patterned photoresist layer 406, and the curing time can be reduced by adjusting the parameters of the energy source to be greater than 1200W.
Referring to fig. 4B, step S3 is performed: after the initial hardening treatment, an oxide layer is formed on the surface of the patterned photoresist layer 406 by using a plasma process, in this embodiment, the process gas of the plasma process uses silicon tetrachloride gas of 50SCCM to 100SCCM and oxygen gas of 100SCCM to 150SCCM, and under the power of 800W to 1200W provided by the energy source of the plasma process, an oxide is deposited on the surface of the patterned photoresist layer 406 subjected to the primary hardening treatment to form the oxide layer, and the time for depositing the oxide is 5S to 10S. The oxide is silicon dioxide, and since the polysilicon layer 401 is mainly silicon, silicon oxide or silicon nitride, the oxide is silicon dioxide, so that the introduction of other oxides can be avoided and unnecessary byproducts are generated. The gas flow, power of the energy source, and time for depositing the oxide are related to the thickness and height difference of the patterned photoresist layer 406, and the specific parameters are related to actual conditions.
Further, after the oxide layer is formed, hardening the oxide layer, specifically, hardening the oxide layer by adopting a plasma process, wherein the process gas of the plasma process adopts 50-150 SCCM hydrogen bromide, and the surface of the oxide layer is hardened by 5-10S under the power of 800-1200W provided by an energy source of the plasma process. Since the hydrogen bromide gas only hardens the surface of the patterned photoresist layer 406, it is difficult to harden the patterned photoresist layer 406 deeply, and the surface hardening alone has low etching resistance of the patterned photoresist layer 406, so that forming an oxide layer on the surface of the patterned photoresist layer 406 and hardening the oxide layer can enhance the etching resistance of the patterned photoresist layer 406 to prevent the patterned photoresist layer 406 from being excessively etched.
Further, after a first oxide layer is deposited on the surface of the patterned photoresist layer 406 for a first time and is hardened, in order to further enhance the hardening effect of the patterned photoresist layer 406, the oxide layer is formed on the surface of the patterned photoresist layer 406 and the hardening process is repeated several times. Specifically, a second oxide layer is formed on the first oxide layer after hardening by adopting a plasma process, the process gas of the plasma process adopts silicon tetrachloride gas of 50-100 SCCM and oxygen of 100-150 SCCM, and under the power of 800-1200W provided by an energy source of the plasma process, oxidation is deposited on the surface of the first oxide layerForming a second oxide layer, and depositing the oxide for 5-10S. In this embodiment, the thickness of the patterned photoresist layer 406 is
In order to ensure the etching resistance of the patterned photoresist layer 406 and the thickness of the hard mask layer after polysilicon etching, in this embodiment, the forming of the oxide layer and the hardening process are selected to be repeated 3 to 5 times, each time the oxide layer is formed on the previous hardened oxide layer, and the new oxide layer is formed and then needs to be hardened, wherein the deposition condition and the hardening condition of each time are the same until the hardening of the last oxide layer is finished, and a thicker hardened layer 407 is formed on the surface of the patterned photoresist layer 406, i.e., the hardening process of the patterned photoresist layer 406 is completed. In this embodiment, the steps of forming the oxide layer and performing the hardening treatment are repeated 3 to 5 times, but not limited thereto, the number of times of the repetition is related to the height difference and the thickness of the patterned photoresist layer, and the number of times of the repetition is determined according to the actual situation.
Referring to fig. 4C, step S4 is executed: after the patterned photoresist layer 406 is hardened, the anti-reflective layer is etched using the patterned photoresist layer 406 as a mask to form a patterned anti-reflective layer 405A.
Referring to fig. 4C, step S5 is executed: after the anti-reflective coating layer is etched, the hardened layer 407 on the surface of the patterned photoresist layer 406 is affected, the thickness of the patterned photoresist layer 406 is reduced, and the surface of the patterned photoresist layer 406 and the surface of the patterned anti-reflective coating layer 405A are hardened. Specifically, the embodiment of step 2 is repeated to perform a hardening process on the surface of the patterned photoresist layer 406 and the surface of the patterned anti-reflective layer 405A, and the adopted process conditions, the type of process gas, the gas flow rate and the power of the energy source are the same as those in step 2, so as to enhance the etching resistance of the surface of the patterned photoresist layer 406 and the surface of the patterned anti-reflective layer 405A.
Referring to fig. 4C, step S6 is executed: forming an oxide layer on the surface of the hardened patterned photoresist layer 406 and the surface of the patterned anti-reflection layer 405A, performing a hardening process, and repeating the steps several times to form a hardened layer 407 on the surface of the patterned photoresist layer 406 and the surface of the patterned anti-reflection layer 405A, specifically, repeating the step S3 to form an oxide layer on the surface of the patterned photoresist layer 406 and the surface of the patterned anti-reflection layer 405A, and performing a hardening process several times, wherein the adopted process conditions, process gas types, gas flow rates, and energy source powers are the same as those in step S3, so as to further enhance the etching resistance of the surface of the patterned photoresist layer 406 and the surface of the patterned anti-reflection layer 405A.
Referring to fig. 4D, step S7 is executed: the hard mask layer is etched using the patterned photoresist layer as a mask to form a patterned hard mask layer including a patterned first silicon oxide layer 104, a patterned silicon nitride layer 105, and a patterned second silicon oxide layer 404A. And after the etching of the hard mask layer is finished, removing the residual patterned photoresist layer by adopting a dry plasma photoresist removing process.
Further, since the thick hardened layer 407 is formed on the surface of the patterned photoresist layer and the patterned anti-reflection layer, the widths of the patterned photoresist layer and the patterned anti-reflection layer are widened, and the width of the patterned hard mask layer is widened after etching, the patterned hard mask layer needs to be laterally etched to be narrowed in conformity with the width of the uncured patterned photoresist layer. And adopting a plasma process to perform transverse etching on the patterned hard mask layer, wherein the process gas of the plasma process adopts carbon tetrafluoride gas of 50-100 SCCM and trifluoromethane gas of 10-30 SCCM, and the patterned hard mask layer is subjected to transverse etching under the power of an energy source of 400-800W of the plasma process. In this embodiment, the gas flow and the energy source power are related to the width of the patterned hard mask layer and the energy source power, and the magnitude of the gas flow and the magnitude of the energy source power are related to the actual situation.
Referring to fig. 4E, step S8 is executed: and etching the polysilicon layer by using the patterned hard mask layer as a mask to form a patterned polysilicon layer 103, etching the patterned second silicon oxide layer 404A after forming the patterned polysilicon layer 103, and finally sequentially forming the patterned polysilicon layer 103, the patterned first silicon oxide layer 104 and the patterned silicon nitride layer 105 on the substrate 101. The method is characterized in that the polycrystalline silicon layer is etched by adopting a dry plasma process, the process gas of the dry plasma process adopts hydrogen bromide gas of 50-100 SCCM and oxygen gas of 2-10 SCCM, and the energy source of the dry plasma process converts the hydrogen bromide gas and the oxygen gas into plasma to etch the polycrystalline silicon layer. In this embodiment, in order to prevent the ion implantation in the subsequent etching process from affecting the etched polysilicon layer, the hard mask layer after the etching of the polysilicon layer has a thickness of 1200SCCM to 1500 SCCM. In the present embodiment, the gas flow rate is related to the thickness of the polysilicon layer and the power of the energy source, and the gas flow rate and the power of the energy source are determined according to actual conditions.
In summary, the present invention provides a method for fabricating a semiconductor structure, which comprises performing a primary hardening on a surface of a patterned photoresist layer to enhance the etching resistance of the patterned photoresist layer and prevent the patterned photoresist layer from being excessively etched; secondly, forming an oxide layer on the surface of the patterned photoresist layer, hardening the oxide layer, and repeating the hardening treatment for a plurality of times to further enhance the etching resistance of the patterned photoresist layer and further prevent the patterned photoresist layer from being excessively etched; after the anti-reflection layer is etched, repeatedly hardening and forming an oxide layer, enhancing the etching resistance of the patterned photoresist layer and the patterned anti-reflection layer, and finally ensuring that no defect exists on the top appearance of the hard mask layer after the polycrystalline silicon layer is etched and no polycrystalline silicon residue is generated on the substrate; and after the hard mask layer is etched, the hard mask layer is transversely etched, so that the pattern of the etched polycrystalline silicon layer is consistent with the pattern of the graphical photoresist layer which is not cured, the integral structure is not changed in the process, and the process consistency is ensured.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate, forming a shallow trench isolation structure in the substrate, and sequentially forming a polycrystalline silicon layer, a hard mask layer, an anti-reflection layer and a graphical photoresist layer on the substrate, wherein the shallow trench isolation structure has a height difference with the surface of the substrate, the top surface of the anti-reflection layer is flat, and the thickness of the anti-reflection layer has a thickness difference;
hardening the surface of the patterned photoresist layer;
forming an oxide layer on the surface of the patterned photoresist layer, hardening the oxide layer, and repeating the steps for a plurality of times;
etching the anti-reflection layer by taking the patterned photoresist layer as a mask to form a patterned anti-reflection layer;
carrying out hardening treatment on the surface of the patterned photoresist layer and the surface of the patterned anti-reflection layer;
forming an oxide layer on the surface of the patterned photoresist layer and the surface of the patterned anti-reflection layer, carrying out hardening treatment, and repeating for a plurality of times;
etching the hard mask layer by taking the patterned photoresist layer as a mask to form a patterned hard mask layer, and removing the patterned photoresist layer;
and etching the polycrystalline silicon layer by taking the graphical hard mask layer as a mask.
2. The method of claim 1, wherein after the hard mask layer is etched, the patterned hard mask layer is laterally etched to narrow the patterned hard mask layer.
3. The method of claim 2, wherein an etching gas used to laterally etch the hard mask layer comprises carbon tetrafluoride and trifluoromethane.
4. The method of manufacturing a semiconductor structure according to claim 1, wherein the hard mask layer is a stacked layer of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.
5. The method of fabricating a semiconductor structure according to claim 1, wherein the hardening process is performed using a plasma process.
6. The method of claim 5, wherein a process gas of the plasma process is hydrogen bromide gas.
7. The method of claim 1, wherein a material of the oxide layer comprises silicon dioxide.
8. The method of claim 1, wherein the polysilicon layer is etched using a dry etching process, wherein process gases of the dry etching process comprise hydrogen bromide gas and oxygen gas.
9. The method of claim 1, wherein the patterned photoresist layer is removed using a dry plasma strip process.
10. The method according to claim 1, wherein the anti-reflective layer comprises one or more of silicon, carbon, nitrogen, zirconium, titanium, cerium, and hafnium.
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