CN108630526B - Method for improving cavity of interlayer dielectric layer - Google Patents
Method for improving cavity of interlayer dielectric layer Download PDFInfo
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- CN108630526B CN108630526B CN201810416000.8A CN201810416000A CN108630526B CN 108630526 B CN108630526 B CN 108630526B CN 201810416000 A CN201810416000 A CN 201810416000A CN 108630526 B CN108630526 B CN 108630526B
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- oxide layer
- interlayer dielectric
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- 239000010410 layer Substances 0.000 title claims abstract description 70
- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000011229 interlayer Substances 0.000 title claims abstract description 25
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000001301 oxygen Substances 0.000 claims abstract description 16
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 239000002131 composite material Substances 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 238000002360 preparation method Methods 0.000 claims abstract description 7
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 239000012535 impurity Substances 0.000 abstract description 14
- 230000000694 effects Effects 0.000 abstract description 4
- 238000004140 cleaning Methods 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract description 3
- 238000009751 slip forming Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000001556 precipitation Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02334—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment in-situ cleaning after layer formation, e.g. removing process residues
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a method for solving a cavity of an interlayer dielectric layer, which is applied to a semiconductor manufacturing process, wherein a side wall and a silicide interlayer dielectric layer composite film are formed on the outer side of a grid structure, a first oxide layer with a first preset thickness is formed on the outer surface of the composite film, the first oxide layer is etched back, oxygen is introduced into the surface of the first oxide layer for a preset time not less than 15 seconds, and the oxide layer is continuously formed on the surface of the first oxide layer, so that the preparation process of the oxide interlayer dielectric layer is completed. According to the technical scheme, through the oxygen treatment process, impurities in the control grid gaps can be taken away by oxygen airflow so as to achieve the effect of cleaning the control grid gaps, the impurities are removed, the generation of cavities of the interlayer dielectric layer is avoided, the product defects are reduced, and the product yield is improved.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for improving cavities of an interlayer dielectric layer.
Background
In the conventional manufacturing process of the nonvolatile semiconductor memory, an interlayer dielectric deposition process is included in the process of preparing the control gate, and is used for depositing an interlayer dielectric on the spacing region and the top of the control gate. In the existing interlayer dielectric deposition process, impurities are easy to remain between control gates, the existing process cannot completely clean the impurities in the grooves, and the impurities can form cavities in the subsequent process, so that defects appear in the interlayer dielectric film. The impurities remaining between the control gates may cause the contact holes to be connected, thereby forming a short circuit of the circuit and reducing the yield.
Meanwhile, as the size of the device is reduced, the control gate gap is also gradually reduced, so that the aspect ratio of the gap becomes larger, and further impurities in the control gate gap are more difficult to remove. Therefore, in the continuously advanced memory manufacturing process, the product yield is greatly influenced.
Disclosure of Invention
In view of the above problems in the prior art, a method for improving voids in an interlayer dielectric layer is provided.
The specific technical scheme is as follows:
a method for improving the cavity of an interlayer dielectric layer is applied to a semiconductor manufacturing process and comprises the following steps:
step S1: providing a semiconductor structure for completing the preparation process of the grid structure with the control grid;
step S2: forming a side wall and a silicide interlayer dielectric layer composite film on the outer side of the grid structure;
step S3: forming a first oxide layer with a first preset thickness on the outer surface of the composite film;
step S4: etching back the first oxide layer to remove a second predetermined thickness of the first oxide layer;
step S5: introducing oxygen to the surface of the first oxide layer for a preset time not less than 15 seconds to remove residues between the gate structures when the first oxide layer is etched back;
step S6: and continuously forming an oxide layer on the surface of the first oxide layer to finish the preparation process of the oxide interlayer dielectric layer.
Preferably, in step S5, the predetermined time is 15 to 30 seconds.
Preferably, in step S5, the predetermined time is 20 seconds.
Preferably, in the step S3, the first predetermined thickness is
Preferably, in the step S4, the second predetermined thickness is
Preferably, in step S3, the first oxide layer is made of silicon oxide.
Preferably, in step S4, the first oxide layer is etched back using nitrogen trifluoride gas.
Preferably, in step S3, the first oxide layer is formed by a chemical vapor deposition process.
Preferably, the chemical vapor deposition process deposits the first oxide layer by a mixed gas of monosilane and oxygen.
Preferably, in the step S6, the oxide layer deposited continuously is silicon oxide; and/or the thickness of the oxide layer deposited in step S6 is
The technical scheme has the following advantages or beneficial effects:
the silicon oxide precipitation process is divided into two parts to be carried out in the interlayer dielectric layer precipitation process, and oxygen is introduced into the surface of the semiconductor structure in the intermediate process, so that impurities in the control gate gaps can be taken away by oxygen airflow to achieve the effect of cleaning the control gate gaps, the impurities are removed, the cavity of the interlayer dielectric layer is avoided, the product defects are reduced, and the product yield is improved.
Drawings
Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.
FIG. 1 is a flowchart illustrating a method for improving voids in an interlayer dielectric layer according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
In a preferred embodiment of the present invention, as shown in fig. 1, a method for improving voids in an interlayer dielectric layer applied in a semiconductor manufacturing process comprises the following steps:
step S1: providing a semiconductor structure for completing the preparation process of the grid structure with the control grid;
step S2: forming a side wall and a silicide interlayer dielectric layer composite film on the outer side of the grid structure;
step S3: forming a first oxide layer with a first preset thickness on the outer surface of the composite film;
step S4: etching back the first oxide layer to remove a second predetermined thickness of the first oxide layer;
step S5: introducing oxygen into the surface of the first oxide layer for a preset time not less than 15 seconds to remove residues between the gate structures when the first oxide layer is etched back;
step S6: and continuously forming an oxide layer on the surface of the first oxide layer to finish the preparation process of the oxide interlayer dielectric layer.
Specifically, in this embodiment, the silicon oxide precipitation process is divided into two parts to be carried out, and the intermediate process is carried out by introducing oxygen to the surface of the first oxide layer, so that the impurities in the control gate gap can be taken away by the oxygen flow to achieve the effect of cleaning the control gate gap.
By carrying out etching back treatment on the first oxide layer, impurities on the surface of the first oxide layer can be removed, and existing pores in the first oxide layer are opened, so that impurities in the pores and the surface of the first oxide layer can be cleaned by a subsequent oxygen treatment process.
And sequentially depositing silicon oxide, silicon nitride, silicon oxide, silicon oxynitride and silicon nitride on the outer side of the control gate by a chemical vapor deposition method to form a side wall and silicide interlayer dielectric layer composite film, namely a SPACER + ILD SIN composite film.
In a preferred embodiment of the present invention, in step S5, the predetermined time is 15-30 seconds.
Specifically, in this embodiment, the above-mentioned long oxygen treatment process is adopted, so that impurities in the trench and the gap of the semiconductor structure can be effectively blown away, and the effect of avoiding impurities is achieved.
In a preferred embodiment of the present invention, in step S5, the predetermined time is 20 seconds.
In a preferred embodiment of the present invention, in step S3, the first predetermined thickness is
In a preferred embodiment of the present invention, in step S4, the second predetermined thickness is
In a preferred embodiment of the present invention, in step S3, the first oxide layer is made of silicon oxide.
In a preferred embodiment of the present invention, in step S4, the first oxide layer is etched back by using nitrogen trifluoride gas.
Specifically, in this embodiment, fluorine gas (F) remains in the trench of the semiconductor structure after the etching back process of the nitrogen trifluoride gas2) And removing the gas by adopting subsequent oxygen treatment.
In a preferred embodiment of the present invention, in step S3, a chemical vapor deposition process is used to form the first oxide layer.
In a preferred embodiment of the present invention, the chemical vapor deposition process deposits the first oxide layer by a mixture gas of monosilane and oxygen.
In a preferred embodiment of the present invention, in step S6, the oxide layer to be deposited is silicon oxide; and/or in step S6, the oxide layer deposited continuously has a thickness of
In a preferred embodiment of the present invention, the semiconductor structure is fabricated by the following process steps: providing a silicon wafer with a formed floating gate structure, and sequentially depositing silicon oxide, silicon nitride and silicon oxide on the surface of the silicon wafer to form an ONO film; and depositing polysilicon on the surface of the silicon wafer, and performing photoetching and chemical etching on the polysilicon to form a control gate.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (10)
1. A method for improving the cavity of an interlayer dielectric layer is applied to a semiconductor manufacturing process and is characterized by comprising the following steps:
step S1: providing a semiconductor structure for completing the preparation process of the grid structure with the control grid;
step S2: forming a side wall and a silicide interlayer dielectric layer composite film on the outer side of the grid structure;
step S3: forming a first oxide layer with a first preset thickness on the outer surface of the composite film;
step S4: etching back the first oxide layer to remove a second predetermined thickness of the first oxide layer;
step S5: introducing oxygen to the surface of the first oxide layer for a preset time not less than 15 seconds to remove residues between the gate structures when the first oxide layer is etched back;
step S6: and continuously forming an oxide layer on the surface of the first oxide layer to finish the preparation process of the oxide interlayer dielectric layer.
2. The method of claim 1, wherein the predetermined time is 15-30 seconds in step S5.
3. The method of claim 1, wherein the predetermined time is 20 seconds in the step S5.
4. The method of claim 1, wherein in step S3, the first predetermined thickness is
5. The method of claim 1, wherein in step S4, the second predetermined thickness is
6. The method of claim 1, wherein in step S3, the first oxide layer is made of silicon oxide.
7. The method of claim 6, wherein in step S4, the first oxide layer is etched back by using nitrogen trifluoride gas.
8. The method of claim 6, wherein in step S3, the first oxide layer is formed by a chemical vapor deposition process.
9. The method of claim 8, wherein the chemical vapor deposition process deposits the first oxide layer by a mixture of monosilane and oxygen.
10. The method of claim 1, wherein in step S6, the oxide layer deposited continuously is silicon oxide; and/or the thickness of the oxide layer deposited in step S6 is
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| KR100374642B1 (en) * | 2000-11-27 | 2003-03-04 | 삼성전자주식회사 | Forming method for interlayer dielectric of semiconductor device |
| KR100571658B1 (en) * | 2003-11-21 | 2006-04-17 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device |
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- 2018-05-03 CN CN201810416000.8A patent/CN108630526B/en active Active
Patent Citations (9)
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|---|---|---|---|---|
| CN1271179A (en) * | 1999-04-16 | 2000-10-25 | 国际商业机器公司 | Process for oxide corroding of high selective neck ring |
| CN1577751A (en) * | 2003-07-10 | 2005-02-09 | 应用材料有限公司 | Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |