CN111681961B - Method for manufacturing semiconductor device - Google Patents
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- CN111681961B CN111681961B CN202010734076.2A CN202010734076A CN111681961B CN 111681961 B CN111681961 B CN 111681961B CN 202010734076 A CN202010734076 A CN 202010734076A CN 111681961 B CN111681961 B CN 111681961B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 133
- 238000000034 method Methods 0.000 title claims abstract description 95
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 92
- 229910052751 metal Inorganic materials 0.000 claims abstract description 83
- 239000002184 metal Substances 0.000 claims abstract description 83
- 230000008569 process Effects 0.000 claims abstract description 62
- 238000005530 etching Methods 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims abstract description 46
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 40
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 40
- 238000001312 dry etching Methods 0.000 claims abstract description 16
- 239000007789 gas Substances 0.000 claims description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 12
- 238000004140 cleaning Methods 0.000 claims description 11
- 230000008439 repair process Effects 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 229910052715 tantalum Inorganic materials 0.000 claims description 7
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 claims description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 4
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 3
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 3
- 229910002090 carbon oxide Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910052727 yttrium Inorganic materials 0.000 claims description 3
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 119
- 150000004767 nitrides Chemical class 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 150000002431 hydrogen Chemical class 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000002194 synthesizing effect Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 150000003608 titanium Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor device, which comprises the steps of forming a side wall material layer on the surface of a semiconductor substrate and the top and side surfaces of a grid structure; then, etching the side wall material layer by adopting a dry etching process until the top surface of the grid structure and the surface of the semiconductor substrate are exposed, so as to form a side wall structure on the side surface of the grid structure; and then, forming metal silicide on the exposed surface of the semiconductor substrate and the top surface of the gate structure. The side wall material layer is etched through the dry etching process and stopped on the top surface of the grid structure and the surface of the semiconductor substrate, so that the side wall material layer can be prevented from remaining on the semiconductor substrate, and the surface morphology of the metal silicide can be leveled when the metal silicide is formed subsequently. Thus, the concave-convex defect of the metal silicide surface can be avoided, thereby improving the uniformity of the metal silicide surface.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a semiconductor device.
Background
In the current semiconductor device manufacturing process, it is required to form a metal silicide in a specific region for reducing contact resistance. The existing manufacturing process flow of semiconductor devices generally includes: firstly, providing a semiconductor substrate, wherein a grid electrode is formed on the semiconductor substrate; then, depositing a side wall material layer on the semiconductor substrate and the grid electrode; etching the side wall material layer to form a grid side wall; and then, performing a wet etching process to remove the residual side wall material layers on the semiconductor substrate and the grid electrode.
However, in the manufacturing process flow of the semiconductor device, when the wet etching process is performed, the etching solution is less (if the etching solution or the etching amount is too much, damage is caused to the morphology of the gate sidewall, and when the source and drain ion implantation is performed subsequently, the ion implantation breaks down the gate sidewall, so that the conductive channel is shortened), so that the etching effect is not achieved, the surface of the semiconductor substrate and the surface of the gate electrode can remain with the sidewall material layer, and when the metal silicide is formed subsequently, the remaining sidewall material layer can cause concave-convex defects on the surface of the metal silicide, that is, the surface uniformity of the metal silicide can be affected, the contact between the metal silicide and the source region, the drain region and the gate structure can be affected, and further the failure such as short circuit or open circuit of the semiconductor device can be caused.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which is used for solving the problem of concave-convex defects on the surface of metal silicide, so as to improve the surface uniformity of the metal silicide.
In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, including:
providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate;
forming a side wall material layer on the surface of the semiconductor substrate and the top surface and the side surface of the grid electrode structure;
etching the side wall material layer by adopting a dry etching process until the top surface of the grid structure and the surface of the semiconductor substrate are exposed, so as to form a side wall structure on the side surface of the grid structure;
and forming metal silicide on the exposed surface of the semiconductor substrate and the top surface of the gate structure.
Optionally, in the method for manufacturing a semiconductor device, the sidewall material layer includes a first oxide layer, a nitride layer and a second oxide layer that are sequentially stacked, where the first oxide layer covers the surface of the semiconductor substrate and the top and side surfaces of the gate structure.
Optionally, in the method for manufacturing a semiconductor device, the method for dry etching the sidewall material layer includes:
etching the first oxide layer by adopting a first etching gas until the surface of the nitride layer is exposed;
and etching the nitride layer and the second oxide layer by adopting second etching gas until the top surface of the gate structure and the surface of the semiconductor substrate are exposed.
Optionally, in the method for manufacturing a semiconductor device, the flow rates of the first etching gas and the second etching gas are both 5 sccm-600 sccm; the first etching gas is one or a mixture of more of nitrogen, fluorine and carbon oxide; the second etching gas is a mixed gas of one or more of hydrogen, oxygen and carbon fluoride.
Optionally, in the method for manufacturing a semiconductor device, after forming the sidewall structure, before forming the metal silicide, the method for manufacturing a semiconductor device further includes:
performing ion implantation on the exposed semiconductor to form a source region and a drain region, wherein the source region and the drain region are respectively positioned at two sides of the grid structure; the method comprises the steps of,
and repairing the surface of the semiconductor substrate after the ion implantation process is carried out.
Optionally, in the method for manufacturing a semiconductor device, the repair process includes at least one of an annealing process, an oxidation process, and a oxynitride process.
Optionally, in the method for manufacturing a semiconductor device, the method for forming the metal silicide includes:
forming a metal layer on the exposed top surface of the grid electrode structure, the semiconductor substrate and the surface of the side wall structure;
performing an annealing process on the semiconductor substrate to react the metal in the metal layer with the gate structure and silicon in the semiconductor substrate and form a metal silicide;
and performing a cleaning process on the semiconductor substrate to remove the unreacted metal layers on the top surface of the gate structure, the semiconductor substrate and the surface of the side wall structure.
Optionally, in the method for manufacturing a semiconductor device, the material in the metal layer is at least one of titanium, zirconium, tantalum, tungsten, manganese, nickel and yttrium.
Optionally, in the method for manufacturing a semiconductor device, before forming the metal layer, the method for manufacturing a semiconductor device further includes forming an adhesion layer, wherein the adhesion layer covers the exposed surface of the semiconductor substrate, and after forming the metal layer, the metal layer covers the adhesion layer.
Optionally, in the method for manufacturing a semiconductor device, the adhesion layer includes at least one layer of a titanium layer, a titanium nitride layer, a tantalum layer, and a tantalum nitride layer.
In the method for manufacturing the semiconductor device, a side wall material layer is formed on the surface of the semiconductor substrate and the top surface and the side surface of the grid structure; then, etching the side wall material layer by adopting a dry etching process until the top surface of the grid structure and the surface of the semiconductor substrate are exposed, so as to form a side wall structure on the side surface of the grid structure; and then, forming metal silicide on the exposed surface of the semiconductor substrate and the top surface of the gate structure. And etching the side wall material layer through the dry etching process, stopping the side wall material layer on the top surface of the grid structure and the surface of the semiconductor substrate, so that the side wall material layer can be prevented from remaining on the semiconductor substrate, and the appearance of the surface of the metal silicide can be leveled when the metal silicide is formed subsequently. Thus, the concave-convex defect of the metal silicide surface can be avoided, thereby improving the uniformity of the metal silicide surface. Furthermore, as the dry etching process is adopted to etch the side wall material layer, compared with the prior art, the appearance of the side wall structure is not damaged.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2 to 6 are schematic structural views formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
wherein reference numerals are as follows:
100-a semiconductor substrate; 110-gate structure; 120-a side wall material layer; 130-a side wall structure; 140-source region; 150-drain region; 160-a metal layer; 170-metal silicide.
Detailed Description
The method for manufacturing the semiconductor device according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the invention. As shown in fig. 1, the method for manufacturing the semiconductor device includes:
step S1: providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate;
step S2: forming a side wall material layer on the surface of the semiconductor substrate and the top surface and the side surface of the grid electrode structure;
step S3: dry etching the side wall material layer until the top surface of the grid structure and the surface of the semiconductor substrate are exposed, so as to form a side wall structure on the side surface of the grid structure;
step S4: and forming metal silicide on the exposed surface of the semiconductor substrate and the top surface of the gate structure.
Fig. 2 to 6 are schematic structural views of a semiconductor device according to an embodiment of the invention. Next, the above steps will be described in more detail with reference to fig. 2 to 6.
As shown in fig. 2, first, step S1 is performed to provide a semiconductor substrate 100, and a gate structure 110 is formed on the semiconductor substrate 100. Shallow trench isolation structures (not shown) are formed in the semiconductor substrate 100. In addition, the surface of the semiconductor substrate 100 has exposed silicon regions, which may be source regions 140 and drain regions 150 formed in the semiconductor substrate 100 to serve as semiconductor devices, and the silicon regions may be monocrystalline silicon, amorphous silicon, polycrystalline silicon, or microcrystalline silicon.
The gate structure 110 includes a gate dielectric layer and a gate electrode on the gate dielectric layer, where the gate dielectric layer is silicon oxide and/or silicon nitride, and may also be a high-K dielectric such as aluminum oxide, hafnium oxide, or a combination of the high-K dielectric and silicon oxide or silicon nitride; the gate may be a polysilicon gate, and in other embodiments of the invention, the gate may be a metal gate.
Then, as shown in fig. 3, step S2 is performed to form a sidewall material layer 120 on the surface of the semiconductor substrate 100 and the top and side surfaces of the gate structure 110. Specifically, the sidewall material layer 120 includes a first oxide layer, a nitride layer, and a second oxide layer that are sequentially stacked, where the first oxide layer covers the surface of the semiconductor substrate 100 and the top and side surfaces of the gate structure 110. The first oxide layer and the second oxide layer may be, for example, silicon dioxide layers, and the nitride layer may be a silicon nitride layer. More specifically, the sidewall material layer 120 may be formed by one or more of a plasma chemical vapor deposition process, an atomic layer deposition process, a low pressure chemical vapor deposition process, and an atmospheric pressure chemical vapor deposition process. In this embodiment, the sidewall material layer 120 is preferably formed by using a low-pressure vapor deposition process and an atomic layer deposition process, so that the thickness uniformity of the first sidewall material layer 120 is better. For example, the first oxide layer and the second oxide layer may be formed using a low pressure vapor deposition (LPCVD) process using tetraethyl orthosilicate (TEOS), and the nitride layer may be formed using an atomic layer deposition process.
In addition, after the sidewall material layer 120 is formed, the semiconductor substrate 100 may be rapidly annealed to improve the compactness of the sidewall material layer. In this embodiment, the process temperature for forming the sidewall material layer 120 may be 200 ℃ to 900 ℃, the annealing temperature may be 500 ℃ to 1300 ℃, the annealing time may be 30s to 100s, and the annealing temperature in this embodiment is 1150 ℃.
Next, as shown in fig. 4, step S3 is performed, where the sidewall material layer 120 is etched by a dry etching process until the top surface of the gate structure 110 and the surface of the semiconductor substrate 100 are exposed, so as to form a sidewall structure 130 on the side surface of the gate structure 110. That is, the sidewall structure 130 includes at least a portion of the sidewall material layer 120. The dry etching process may be, for example, an anisotropic plasma etching process or a reactive ion etching process.
Specifically, the method for etching the sidewall material layer 120 includes: etching the first oxide layer by adopting a first etching gas until the surface of the nitride layer is exposed (i.e. the surface of the nitride layer positioned on the top surface of the gate structure and the surface of the semiconductor substrate is exposed), and immediately stopping etching on the surface of the nitride layer; and etching the nitride layer and the second oxide layer by adopting a second etching gas until the top surface of the gate structure 110 and the surface of the semiconductor substrate 100 are exposed, and immediately stopping etching on the top surface of the gate structure 110 and the surface of the semiconductor substrate 100. Therefore, the sidewall material layer 120 on the top surface of the gate structure 110 and the surface of the semiconductor substrate 100 can be thoroughly removed, and the residue of the sidewall material layer 120 is avoided, so that the uniformity of the subsequently formed metal silicide 170 can be prevented from being affected. In addition, since the sidewall material layer 120 is etched by dry etching, damage to the appearance of the etched first nitride layer can be avoided when the nitride layer and the second oxide layer are etched, so that the sidewall structure 130 formed later has a better appearance, and breakdown of the subsequent ion implantation process can be avoided.
The flow rates of the first etching gas and the second etching gas are 5 sccm-600 sccm. If the gas flow rates of the first etching gas and the second etching gas are too small, the etching is easy to be too slow, the etching time is increased, and if the gas flow rates are too large, the stability and uniformity of the etching rate are easy to be poor. Therefore, in this embodiment, the gas flow rates of the first etching gas and the second etching gas are preferably set to be 5sccm to 600sccm. The first etching gas is at least one of nitrogen, fluorine and carbon oxide gas, such as C 4 F 8 Or CO, etc.; the second etching gas is at least one of hydrogen, oxygen and fluorocarbon gas, for example, CF 4 Or CHF 3 。
Next, as shown in fig. 5, an ion implantation process is performed on the exposed semiconductor to form a source region 140 and a drain region 150, the source region 140 and the drain region 150 being located at both sides of the gate structure 110, respectively. Further, after the ion implantation process is performed, the ions implanted by the ion implantation process may be activated by an annealing process, so that the ions implanted by the ion implantation process are diffused into the semiconductor substrate 100 under the gate structure 110, and at the same time, lattice damage caused by the ion implantation process on the surface of the semiconductor substrate 100 is repaired, thereby forming the source region 140 or the drain region 150. Next, a repair process is performed on the surface of the semiconductor substrate 100 after the ion implantation process is performed. The repair process is mainly to repair dry etching damage of the surface of the semiconductor substrate 100. Specifically, the dry etching damage is mainly that, in the process of etching the sidewall material layer 120, a certain over etching is required to thoroughly remove the top surface of the gate structure 110 and the sidewall material layer 120 on the surface of the semiconductor substrate 100, so that damage to the surface of the semiconductor substrate 100, that is, a recess, is formed in the etching process. Thereby, damage to the surface of the semiconductor substrate 100 can be repaired using the repair process.
Further, the repair treatment includes at least one of a thermal oxidation process, an in-situ steam production process, and a nitrogen oxidation process. Specifically, the thermal oxidation process may perform a thermal oxidation process of 600 ℃ to 1100 ℃ on the semiconductor substrate 100 in an oxygen gas through an oxidation furnace or a rapid thermal annealing chamber; the in-situ vapor generation (ISSG) process is a process of introducing hydrogen and oxygen into a rapid thermal annealing chamber, in-situ synthesizing water vapor on the surface of the semiconductor substrate 100, and then synthesizing silicon and the like on the surface of the semiconductor substrate 100 to form an oxide; the rapid thermal nitrogen oxidation process adopts process gas nitrous oxide, and the process temperature is 800-1300 ℃. For example 1000 c, for an annealing time of 20s to 160s, for example 70s, to repair the surface of the semiconductor substrate 100. Among them, the repair treatment of the present embodiment preferably employs a thermal oxidation process.
Next, as shown in fig. 6, step S4 is performed to form a metal silicide 170 on the exposed surface of the semiconductor substrate 100 and the top surface of the gate structure 110. Specifically, the method for forming the metal silicide 170 includes: forming a metal layer 160 on the exposed top surface of the gate structure 110, the semiconductor substrate 100 and the surface of the sidewall structure 130; annealing the semiconductor substrate 100 to react the metal in the metal layer 160 with the silicon in the gate structure 110 and the semiconductor substrate 100 and form a metal silicide 170; and performing a cleaning process on the semiconductor substrate 100 to remove the unreacted metal layer 160 on the top surface of the gate structure 110, the semiconductor substrate 100 and the surface of the sidewall structure 130. Since the top surface of the gate structure 110 and the sidewall material layer 120 on the surface of the semiconductor substrate 100 are completely removed in step S3, the metal layer 160 with a smoother surface can be formed on the top surface of the gate structure 110 and the surface of the semiconductor substrate 100, so that a metal silicide with a smoother surface can be formed in the subsequent process.
Specifically, the metal layer 160 may be formed by a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, or the like, and the metal layer 160 may be made of at least one of titanium, zirconium, tantalum, tungsten, manganese, nickel, and yttrium. The metal layer 160 of the present embodiment is preferably an alloy of two or more metals. Finally, preferably, an adhesion layer covering the exposed surface of the semiconductor substrate 100 may be formed before the metal layer 160 is formed, and the metal layer 160 covers the adhesion layer after the metal layer 160 is formed. The adhesion layer may enhance adhesion of the subsequently deposited metal layer 160 to the surface of the semiconductor substrate 100 (here, the source region 140 and the drain region 150), increase the flatness of the surface of the metal layer 160, and may serve to limit diffusion of metal in the subsequently deposited metal layer 160 to places other than the source region 140 and the drain region 150. The adhesion layer includes at least one of a titanium layer, a titanium nitride layer, a tantalum layer, and a tantalum nitride layer. That is, the adhesion layer may be any one of a single layer structure or a multi-layered stacked composite structure of a titanium layer, a titanium nitride layer, a tantalum layer, and a tantalum nitride layer.
Next, the semiconductor substrate 100 may be annealed using a low temperature rapid annealing process to react the metal in the metal layer 160 with the gate structure 110 and the silicon in the semiconductor substrate 100 (i.e., silicon in the silicon region of the semiconductor substrate) and form a metal silicide 170. In this embodiment, it is preferable to perform the annealing treatment using a gas containing hydrogen or nitrogen. To eliminate the trace oxygen in the annealing environment and prevent the metal in the metal layer 160 from being oxidized, so that the formation of defects on the surface of the metal silicide 170 can be further avoided or reduced, and the flatness of the surface morphology of the metal silicide 170 can be increased, thereby further improving the surface uniformity of the metal silicide 170.
It should be noted that, in other embodiments of the present invention, since the gate of the gate structure 110 is not a silicon gate made of polysilicon, monocrystalline silicon, amorphous silicon, or the like, for example, a metal gate, the metal silicide 170 formed in the subsequent step S4 is not formed on the surface of the gate structure 110.
Then, a cleaning process is performed on the semiconductor substrate 100 to remove the unreacted metal layer 160 on the top surface of the gate structure 110, the semiconductor substrate 100 and the surface of the sidewall structure 130. Here, the metal layer 160 unreacted on the surface of the sidewall 130 is mainly removed. The cleaning process may be performed on the semiconductor substrate 100 using a wet cleaning solution, for example, a mixed solution of one or more of sulfuric acid, hydrogen peroxide, phosphoric acid, a strong acid, and a hydrogen oxidizing agent, or the cleaning process may be performed on the semiconductor substrate 100 using the heated cleaning solution after the cleaning solution is heated to a high temperature of 100 ℃ to increase a cleaning rate so as to rapidly remove the unreacted metal layer 160. Here, the cleaning time may be more than 20s to thoroughly remove the unreacted metal layer 160, thereby avoiding the residue thereof.
In summary, in the method for manufacturing a semiconductor device provided by the invention, the sidewall material layer is etched by adopting a dry method, so that the sidewall material layer is prevented from remaining on the semiconductor substrate, and the morphology of the metal silicide surface can be leveled when the metal silicide is formed subsequently. Thus, the concave-convex defect of the metal silicide surface can be avoided, thereby improving the uniformity of the metal silicide surface. Furthermore, as the dry etching process is adopted to etch the side wall material layer, compared with the prior art, the appearance of the side wall is not damaged.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (7)
1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate;
forming a side wall material layer on the surface of the semiconductor substrate and the top and side surfaces of the gate structure, wherein the side wall material layer comprises a first silicon dioxide layer, a silicon nitride layer and a second silicon dioxide layer which are sequentially stacked, and the first silicon dioxide layer covers the surface of the semiconductor substrate and the top and side surfaces of the gate structure;
etching the side wall material layer by adopting a dry etching process until the top surface of the grid electrode structure and the surface of the semiconductor substrate are exposed to form a side wall structure on the side surface of the grid electrode structure, wherein the first silicon dioxide layer is etched by adopting a first etching gas until the surface of the silicon nitride layer is exposed; etching the silicon nitride layer and the second silicon dioxide layer by adopting second etching gas until the top surface of the grid structure and the surface of the semiconductor substrate are exposed, wherein the second etching gas is different from the first etching gas;
performing an ion implantation process on the exposed semiconductor to form a source region and a drain region, wherein the source region and the drain region are respectively positioned at two sides of the gate structure;
repairing the surface of the semiconductor substrate after the ion implantation process is carried out so as to repair dry etching damage of the surface of the semiconductor substrate;
and forming metal silicide on the exposed surface of the semiconductor substrate and the top surface of the gate structure.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the flow rates of the first etching gas and the second etching gas are each 5sccm to 600sccm; wherein the first etching gas is nitrogen, fluorine and carbon oxide gas; the second etching gas is hydrogen, oxygen and carbon fluoride.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the repair process includes at least one of a thermal oxidation process, an in-situ steam production process, and a oxynitride process.
4. The method of manufacturing a semiconductor device according to claim 1, wherein the method of forming the metal silicide comprises:
forming a metal layer on the exposed top surface of the grid electrode structure, the semiconductor substrate and the surface of the side wall structure;
annealing the semiconductor substrate to enable metal in the metal layer to react with silicon in the gate structure and the semiconductor substrate and form metal silicide;
and performing a cleaning process on the semiconductor substrate to remove the unreacted metal layers on the top surface of the gate structure, the semiconductor substrate and the surface of the side wall structure.
5. The method for manufacturing a semiconductor device according to claim 4, wherein the metal layer is made of at least one of titanium, zirconium, tantalum, tungsten, manganese, nickel, and yttrium.
6. The method of manufacturing a semiconductor device according to claim 4, wherein before forming the metal layer, the method further comprises forming an adhesion layer covering the exposed surface of the semiconductor substrate, the metal layer covering the adhesion layer after forming the metal layer.
7. The method for manufacturing a semiconductor device according to claim 6, wherein the adhesion layer includes at least one of a titanium layer, a titanium nitride layer, a tantalum layer, and a tantalum nitride layer.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102122639A (en) * | 2010-01-08 | 2011-07-13 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of non-volatile memory |
| CN102569089A (en) * | 2010-12-30 | 2012-07-11 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device forming method |
| CN102983075A (en) * | 2011-09-07 | 2013-03-20 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device applying stress approaching technology |
| CN104465351A (en) * | 2014-11-28 | 2015-03-25 | 上海华力微电子有限公司 | Method for improving metal silicide |
| CN104979292A (en) * | 2015-05-15 | 2015-10-14 | 上海华力微电子有限公司 | Method for forming different sidewall structures |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102122639A (en) * | 2010-01-08 | 2011-07-13 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of non-volatile memory |
| CN102569089A (en) * | 2010-12-30 | 2012-07-11 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device forming method |
| CN102983075A (en) * | 2011-09-07 | 2013-03-20 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device applying stress approaching technology |
| CN104465351A (en) * | 2014-11-28 | 2015-03-25 | 上海华力微电子有限公司 | Method for improving metal silicide |
| CN104979292A (en) * | 2015-05-15 | 2015-10-14 | 上海华力微电子有限公司 | Method for forming different sidewall structures |
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