CN111681961B - Method for manufacturing semiconductor device - Google Patents

Abstract

The invention provides a manufacturing method of a semiconductor device, which comprises the steps of forming a side wall material layer on the surface of a semiconductor substrate and the top and side surfaces of a grid structure; then, etching the side wall material layer by adopting a dry etching process until the top surface of the grid structure and the surface of the semiconductor substrate are exposed, so as to form a side wall structure on the side surface of the grid structure; and then, forming metal silicide on the exposed surface of the semiconductor substrate and the top surface of the gate structure. The side wall material layer is etched through the dry etching process and stopped on the top surface of the grid structure and the surface of the semiconductor substrate, so that the side wall material layer can be prevented from remaining on the semiconductor substrate, and the surface morphology of the metal silicide can be leveled when the metal silicide is formed subsequently. Thus, the concave-convex defect of the metal silicide surface can be avoided, thereby improving the uniformity of the metal silicide surface.

Description

Semiconductor device manufacturing method

Technical field

The present invention relates to the technical field of semiconductor manufacturing, and in particular to a manufacturing method of a semiconductor device.

Background technique

Today, in the manufacturing process of semiconductor devices, metal silicide needs to be formed in specific areas to reduce contact resistance. The existing manufacturing process flow of semiconductor devices usually includes: first, providing a semiconductor substrate with a gate electrode formed on the semiconductor substrate; then, depositing a spacer material layer on the semiconductor substrate and the gate electrode; and then, forming a gate electrode on the semiconductor substrate. The spacer material layer is etched to form the gate spacer; then, a wet etching process is performed to remove the remaining spacer material layer on the semiconductor substrate and the gate.

However, in the manufacturing process of the above-mentioned semiconductor device, when performing the wet etching process, less etching liquid is used (if the etching liquid or the amount of etching is too much, it will cause damage to the morphology of the gate sidewalls. Damage, during subsequent source and drain ion implantation, the ion implantation will break down the gate sidewalls, resulting in a shortening of the conductive channel). Therefore, the etching effect cannot be achieved, and residues will remain on the surface of the semiconductor substrate and the gate electrode. When the sidewall material layer and the remaining sidewall material layer are subsequently formed into metal silicide, they will cause uneven defects on the surface of the metal silicide, which will affect the surface uniformity of the metal silicide, thereby affecting the connection between the metal silicide and the source area. The contact between the drain region and the gate structure may cause short circuit or open circuit failure of the semiconductor device.

Contents of the invention

The object of the present invention is to provide a method for manufacturing a semiconductor device to solve the problem of uneven defects on the surface of metal silicide, thereby improving the surface uniformity of metal silicide.

In order to solve the above technical problems, the present invention provides a manufacturing method of a semiconductor device. The manufacturing method of a semiconductor device includes:

Provide a semiconductor substrate with a gate structure formed on the semiconductor substrate;

Forming a spacer material layer on the surface of the semiconductor substrate and the top and side surfaces of the gate structure;

Use a dry etching process to etch the sidewall material layer until the top surface of the gate structure and the surface of the semiconductor substrate are exposed to form a sidewall structure on the side of the gate structure;

Metal silicide is formed on the exposed surface of the semiconductor substrate and the top surface of the gate structure.

Optionally, in the manufacturing method of a semiconductor device, the spacer material layer includes a first oxide layer, a nitride layer and a second oxide layer stacked in sequence, and the first oxide layer covers the semiconductor liner. bottom surface as well as top and side surfaces of the gate structure.

Optionally, in the manufacturing method of a semiconductor device, a method of dry etching the spacer material layer includes:

Use a first etching gas to etch the first oxide layer until the surface of the nitride layer is exposed;

The second etching gas is used to etch the nitride layer and the second oxide layer until the top surface of the gate structure and the surface of the semiconductor substrate are exposed.

Optionally, in the manufacturing method of a semiconductor device, the flow rates of the first etching gas and the second etching gas are both 5 sccm to 600 sccm; the first etching gas is nitrogen or fluorine. and a mixed gas of one or more combinations of carbon oxide gas; the second etching gas is a mixed gas of one or more combinations of hydrogen, oxygen, and fluorocarbon gas.

Optionally, in the manufacturing method of a semiconductor device, after forming the spacer structure and before forming the metal silicide, the manufacturing method of the semiconductor device further includes:

Perform ion implantation on the exposed semiconductor to form source regions and drain regions, which are respectively located on both sides of the gate structure; and,

The surface of the semiconductor substrate after performing the ion implantation process is repaired.

Optionally, in the manufacturing method of a semiconductor device, the repair process includes at least one of an annealing process, an oxidation process, and an oxynitride process.

Optionally, in the manufacturing method of a semiconductor device, the method of forming the metal silicide includes:

Form a metal layer on the exposed top surface of the gate structure, the semiconductor substrate and the spacer structure;

Perform an annealing process on the semiconductor substrate to cause metal in the metal layer to react with silicon in the gate structure and the semiconductor substrate and form metal silicide;

A cleaning process is performed on the semiconductor substrate to remove the unreacted metal layer on the top surface of the gate structure, the semiconductor substrate and the spacer structure surface.

Optionally, in the manufacturing method of a semiconductor device, the material in the metal layer is at least one of titanium, zirconium, tantalum, tungsten, manganese, nickel and yttrium.

Optionally, in the manufacturing method of the semiconductor device, before forming the metal layer, the manufacturing method of the semiconductor device further includes forming an adhesion layer, the adhesion layer covering the exposed portion of the semiconductor device. On the surface of the semiconductor substrate, after the metal layer is formed, the metal layer covers the adhesion layer.

Optionally, in the manufacturing method of a semiconductor device, the adhesion layer includes at least one layer among a titanium layer, a titanium nitride layer, a tantalum layer and a tantalum nitride layer.

In the manufacturing method of a semiconductor device provided by the present invention, a layer of spacer material is formed on the surface of the semiconductor substrate and the top and side surfaces of the gate structure; and then, a dry etching process is used to etch the sidewall. material layer until the top surface of the gate structure and the surface of the semiconductor substrate are exposed to form a spacer structure on the side of the gate structure; then, on the exposed surface of the semiconductor substrate and the gate Metal silicide is formed on the top surface of the pole structure. By etching the sidewall material layer through the dry etching process and stopping on the top surface of the gate structure and the surface of the semiconductor substrate, it is possible to avoid the sidewall material layer remaining on the semiconductor substrate. When the metal silicide is subsequently formed, the surface morphology of the metal silicide can be smoothed. As a result, uneven defects on the surface of the metal silicide can be avoided, thereby improving the uniformity of the surface of the metal silicide. Furthermore, since the dry etching process is used to etch the sidewall material layer, compared with the existing technology, the morphology of the sidewall structure will not be damaged.

Description of the drawings

Figure 1 is a schematic flow chart of a manufacturing method of a semiconductor device provided by an embodiment of the present invention;

2 to 6 are schematic structural diagrams formed in the manufacturing method of a semiconductor device provided by embodiments of the present invention;

Among them, the reference symbols are explained as follows:

100-semiconductor substrate; 110-gate structure; 120-sidewall material layer; 130-sidewall structure; 140-source region; 150-drain region; 160-metal layer; 170-metal silicide.

Detailed ways

The manufacturing method of the semiconductor device proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use imprecise proportions, and are only used to conveniently and clearly assist in explaining the embodiments of the present invention.

Please refer to FIG. 1 , which is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. As shown in Figure 1, the manufacturing method of the semiconductor device includes:

Step S1: Provide a semiconductor substrate with a gate structure formed on the semiconductor substrate;

Step S2: Form a spacer material layer on the surface of the semiconductor substrate and the top and side surfaces of the gate structure;

Step S3: Dry-etch the spacer material layer until the top surface of the gate structure and the surface of the semiconductor substrate are exposed to form a spacer structure on the side of the gate structure;

Step S4: Form metal silicide on the exposed surface of the semiconductor substrate and the top surface of the gate structure.

Please refer to FIGS. 2 to 6 , which are schematic structural diagrams formed in the manufacturing method of a semiconductor device provided by embodiments of the present invention. Next, the above steps will be described in more detail with reference to FIGS. 2 to 6 .

As shown in FIG. 2 , first, step S1 is performed to provide a semiconductor substrate 100 with a gate structure 110 formed on the semiconductor substrate 100 . A shallow trench isolation structure (not shown) is formed in the semiconductor substrate 100 . In addition, the surface of the semiconductor substrate 100 has an exposed silicon region. The exposed silicon region may be the source region 140 and the drain region 150 formed in the semiconductor substrate 100 and used as a semiconductor device. The silicon region may be single crystal silicon, Amorphous silicon, polycrystalline silicon or microcrystalline silicon.

The gate structure 110 includes a gate dielectric layer and a gate electrode located on the gate dielectric layer. The gate dielectric layer is silicon oxide and/or silicon nitride, and may also be a high-K dielectric such as aluminum oxide or hafnium oxide. Or include a combination of high-K dielectric and silicon oxide or silicon nitride; the gate may be a polysilicon gate, and in other embodiments of the present invention, the gate may be a metal gate.

Then, as shown in FIG. 3 , step S2 is performed to form a spacer material layer 120 on the surface of the semiconductor substrate 100 and the top and side surfaces of the gate structure 110 . Specifically, the spacer material layer 120 includes a first oxide layer, a nitride layer and a second oxide layer stacked in sequence. The first oxide layer covers the surface of the semiconductor substrate 100 and the top of the gate structure 110 . face and sides. Wherein, the first oxide layer and the second oxide layer may be, for example, silicon dioxide layers, and the nitride layer may be a silicon nitride layer. More specifically, the sidewall material layer 120 may be formed by one or more combinations of a plasma chemical vapor deposition process, an atomic layer deposition process, a low pressure chemical vapor deposition process, and an atmospheric pressure chemical vapor deposition process. In this embodiment, a low-pressure vapor deposition process and an atomic layer deposition process are preferably used to form the sidewall material layer 120, so that the thickness uniformity of the first sidewall material layer 120 is better. For example, the first oxide layer and the second oxide layer may be formed using a tetraethyl orthosilicate (TEOS) low pressure vapor deposition (LPCVD) process, and the nitride layer may be formed using an atomic layer deposition process.

In addition, after the spacer material layer 120 is formed, the semiconductor substrate 100 may be rapidly annealed to improve the density of the spacer material layer. In this embodiment, the process temperature for forming the sidewall material layer 120 can be 200°C to 900°C, the annealing temperature can be 500°C to 1300°C, and the annealing time can be 30s to 100s. The annealing temperature in this embodiment is 1150°C. ℃.

Next, as shown in FIG. 4 , step S3 is performed, using a dry etching process to etch the spacer material layer 120 until the top surface of the gate structure 110 and the surface of the semiconductor substrate 100 are exposed. Sidewall structures 130 are formed on the side of the gate structure 110 . That is, the sidewall structure 130 includes at least a part of the sidewall material layer 120 . The dry etching process may be, for example, an anisotropic plasma etching process or a reactive ion etching process.

Specifically, the method of etching the sidewall material layer 120 includes: using a first etching gas to etch the first oxide layer until the surface of the nitride layer is exposed (that is, the surface of the nitride layer located on the gate structure is exposed). The surface of the nitride layer on the top surface and the surface of the semiconductor substrate), that is, the etching stops on the surface of the nitride layer; use the second etching gas to etch the nitride layer and the second oxide layer until all the surfaces are exposed. The top surface of the gate structure 110 and the surface of the semiconductor substrate 100 , that is, the etching stops at the top surface of the gate structure 110 and the surface of the semiconductor substrate 100 . As a result, the spacer material layer 120 on the top surface of the gate structure 110 and the surface of the semiconductor substrate 100 can be completely removed to prevent the spacer material layer 120 from remaining, thereby avoiding affecting the subsequent formation of the metal silicide 170 uniformity. In addition, since the sidewall material layer 120 is all dry etched, when etching the nitride layer and the second oxide layer, it is possible to avoid changing the morphology of the etched first nitride layer. Damage is caused, so that the subsequently formed sidewall structure 130 can have a better morphology, and breakdown of the subsequent ion implantation process can be avoided.

Wherein, the flow rates of the first etching gas and the second etching gas are both 5 sccm to 600 sccm. If the gas flow rate of the first etching gas and the second etching gas is too small, it will easily cause the etching to be too slow, which will increase the etching time. If the gas flow rate is too large, it will easily cause the etching rate to decrease. Stability and uniformity deteriorate. Therefore, in this embodiment, it is preferable to set the gas flow rate of the first etching gas and the second etching gas to 5 sccm to 600 sccm. The first etching gas is at least one of nitrogen, fluorine and oxycarbon gas, such as C ₄ F ₈ or CO, etc.; the second etching gas is at least one of hydrogen, oxygen and fluorocarbon gas. One, for example, CF ₄ or CHF ₃ .

Next, as shown in FIG. 5 , an ion implantation process is performed on the exposed semiconductor to form a source region 140 and a drain region 150 . The source region 140 and the drain region 150 are respectively located on both sides of the gate structure 110 . Further, after the ion implantation process is performed, the ions injected by the ion implantation process can be activated through an annealing process, so that the ions injected by the ion implantation process diffuse into the semiconductor substrate 100 below the gate structure 110, and at the same time, repair The ion implantation process causes lattice damage to the surface of the semiconductor substrate 100, thereby forming the source region 140 or the drain region 150. Next, a repair process is performed on the surface of the semiconductor substrate 100 after the ion implantation process is performed. The repair process mainly repairs dry etching damage on the surface of the semiconductor substrate 100 . Specifically, the dry etching damage is mainly due to the fact that during the process of etching the spacer material layer 120, in order to ensure that the spacer material on the top surface of the gate structure 110 and the surface of the semiconductor substrate 100 is Complete removal of the layer 120 requires a certain amount of over-etching. Therefore, the surface of the semiconductor substrate 100 will be damaged during the etching process, that is, a depression will be formed. Therefore, the repair process can be used to repair damage on the surface of the semiconductor substrate 100 .

Further, the repair treatment includes at least one of a thermal oxidation process, an in-situ steam production process, and a nitrogen oxidation process. Specifically, the thermal oxidation process can be carried out in an oxidation furnace or a rapid thermal annealing chamber on the semiconductor substrate 100 under oxygen gas at a temperature of 600°C to 1100°C; the in-situ vapor generation (ISSG) process is In the rapid thermal annealing chamber, hydrogen and oxygen are introduced, water vapor is synthesized in situ on the surface of the semiconductor substrate 100, and then combined with silicon and other materials on the surface of the semiconductor substrate 100 to form an oxide; the rapid thermal nitric oxidation process is The process gas nitrous oxide is used, and the process temperature is 800°C to 1300°C. For example, the temperature is 1000° C., and the annealing time is 20 to 160 seconds, such as 70 seconds, to repair the surface of the semiconductor substrate 100 . Among them, the repair process in this embodiment preferably adopts a thermal oxidation process.

Next, as shown in FIG. 6 , step S4 is performed to form metal silicide 170 on the exposed surface of the semiconductor substrate 100 and the top surface of the gate structure 110 . Specifically, the method of forming the metal silicide 170 includes: forming a metal layer 160 on the exposed top surface of the gate structure 110, the semiconductor substrate 100 and the spacer structure 130; The substrate 100 is annealed so that the metal in the metal layer 160 reacts with the gate structure 110 and the silicon in the semiconductor substrate 100 to form a metal silicide 170; and, to the semiconductor substrate 100 performs a cleaning process to remove the unreacted metal layer 160 on the top surface of the gate structure 110 , the semiconductor substrate 100 and the spacer structure 130 . Since, in step S3 , the spacer material layer 120 on the top surface of the gate structure 110 and the surface of the semiconductor substrate 100 is completely removed, therefore, the spacer material layer 120 on the top surface of the gate structure 110 and the semiconductor substrate 100 can be The metal layer 160 with a relatively flat surface is formed on the surface of the bottom 100, so that a metal silicide with a relatively flat surface can be formed in subsequent processes.

Specifically, the metal layer 160 can be formed through a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. The metal layer 160 is made of titanium, zirconium, or tantalum. , at least one of tungsten, manganese, nickel and yttrium. The metal layer 160 in this embodiment is preferably an alloy of two or more metals. Finally, preferably, before forming the metal layer 160, an adhesion layer may be formed first, and the adhesion layer covers the exposed surface of the semiconductor substrate 100. After the metal layer 160 is formed, The metal layer 160 covers the adhesion layer. The adhesion layer can enhance the adhesion between the subsequently deposited metal layer 160 and the surface of the semiconductor substrate 100 (here, the source region 140 and the drain region 150), increase the flatness of the surface of the metal layer 160, and can be used to limit subsequent The metal in the metal layer 160 diffuses outside the source region 140 and the drain region 150 . The adhesion layer includes at least one of a titanium layer, a titanium nitride layer, a tantalum layer, and a tantalum nitride layer. That is, the adhesion layer may be any single-layer structure or a multi-layer stacked composite structure among a titanium layer, a titanium nitride layer, a tantalum layer, and a tantalum nitride layer.

Next, a low-temperature rapid annealing process may be used to anneal the semiconductor substrate 100, so that the metal in the metal layer 160 interacts with the gate structure 110 and the silicon in the semiconductor substrate 100 (ie, the silicon in the semiconductor substrate 100). The silicon in the silicon region reacts and forms metal suicide 170 . In this embodiment, preferably, gas containing hydrogen or nitrogen is used to perform the annealing process. In order to eliminate trace amounts of oxygen in the annealing environment and prevent the metal in the metal layer 160 from being oxidized, it is possible to further avoid or reduce defects on the surface of the metal silicide 170 and increase the flatness of the surface morphology of the metal silicide 170. Thus, it is possible to further Improve surface uniformity of metal suicide 170 .

It should be noted that in other embodiments of the present invention, since the gate of the gate structure 110 is not a silicon gate made of polycrystalline silicon, monocrystalline silicon, amorphous silicon, etc., but is, for example, a metal gate, in the subsequent step S4 The formed metal silicide 170 will not be formed on the surface of the gate structure 110 .

Next, a cleaning process is performed on the semiconductor substrate 100 to remove the unreacted metal layer 160 on the top surface of the gate structure 110 , the semiconductor substrate 100 and the spacer structure 130 . Here, the unreacted metal layer 160 on the surface of the spacer structure 130 is mainly removed. Wherein, a wet cleaning solution may be used to perform a cleaning process on the semiconductor substrate 100. The wet cleaning solution may be, for example, one or more mixed solutions of sulfuric acid, hydrogen peroxide, phosphoric acid, strong acid and hydroxide. , you can also heat the cleaning solution to a high temperature of 100° C., and then use the heated cleaning solution to perform a cleaning process on the semiconductor substrate 100 to increase the cleaning rate and quickly remove the unreacted metal layer 160 . Here, the cleaning time can be longer than 20 seconds to completely remove the unreacted metal layer 160 and avoid its residue.

In summary, it can be seen that in the manufacturing method of a semiconductor device provided by the present invention, by dry etching the sidewall material layer, the sidewall material layer can be prevented from remaining on the semiconductor substrate and subsequently forming metal silicide. When , the surface morphology of the metal silicide can be made smooth. As a result, uneven defects on the surface of the metal silicide can be avoided, thereby improving the uniformity of the surface of the metal silicide. Furthermore, since the dry etching process is used to etch the sidewall material layer, compared with the existing technology, the morphology of the sidewall will not be damaged.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes or modifications made by those of ordinary skill in the field of the present invention based on the above disclosure shall fall within the scope of the claims.

Claims (7)

1. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate;

forming a side wall material layer on the surface of the semiconductor substrate and the top and side surfaces of the gate structure, wherein the side wall material layer comprises a first silicon dioxide layer, a silicon nitride layer and a second silicon dioxide layer which are sequentially stacked, and the first silicon dioxide layer covers the surface of the semiconductor substrate and the top and side surfaces of the gate structure;

etching the side wall material layer by adopting a dry etching process until the top surface of the grid electrode structure and the surface of the semiconductor substrate are exposed to form a side wall structure on the side surface of the grid electrode structure, wherein the first silicon dioxide layer is etched by adopting a first etching gas until the surface of the silicon nitride layer is exposed; etching the silicon nitride layer and the second silicon dioxide layer by adopting second etching gas until the top surface of the grid structure and the surface of the semiconductor substrate are exposed, wherein the second etching gas is different from the first etching gas;

performing an ion implantation process on the exposed semiconductor to form a source region and a drain region, wherein the source region and the drain region are respectively positioned at two sides of the gate structure;

repairing the surface of the semiconductor substrate after the ion implantation process is carried out so as to repair dry etching damage of the surface of the semiconductor substrate;

and forming metal silicide on the exposed surface of the semiconductor substrate and the top surface of the gate structure.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the flow rates of the first etching gas and the second etching gas are each 5sccm to 600sccm; wherein the first etching gas is nitrogen, fluorine and carbon oxide gas; the second etching gas is hydrogen, oxygen and carbon fluoride.

3. The method of manufacturing a semiconductor device according to claim 1, wherein the repair process includes at least one of a thermal oxidation process, an in-situ steam production process, and a oxynitride process.

4. The method of manufacturing a semiconductor device according to claim 1, wherein the method of forming the metal silicide comprises:

forming a metal layer on the exposed top surface of the grid electrode structure, the semiconductor substrate and the surface of the side wall structure;

annealing the semiconductor substrate to enable metal in the metal layer to react with silicon in the gate structure and the semiconductor substrate and form metal silicide;

and performing a cleaning process on the semiconductor substrate to remove the unreacted metal layers on the top surface of the gate structure, the semiconductor substrate and the surface of the side wall structure.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the metal layer is made of at least one of titanium, zirconium, tantalum, tungsten, manganese, nickel, and yttrium.

6. The method of manufacturing a semiconductor device according to claim 4, wherein before forming the metal layer, the method further comprises forming an adhesion layer covering the exposed surface of the semiconductor substrate, the metal layer covering the adhesion layer after forming the metal layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the adhesion layer includes at least one of a titanium layer, a titanium nitride layer, a tantalum layer, and a tantalum nitride layer.