CN114334797A - Method for forming semiconductor device - Google Patents
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- CN114334797A CN114334797A CN202011056435.XA CN202011056435A CN114334797A CN 114334797 A CN114334797 A CN 114334797A CN 202011056435 A CN202011056435 A CN 202011056435A CN 114334797 A CN114334797 A CN 114334797A
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Abstract
The invention provides a method for forming a semiconductor device, which comprises the steps of providing a substrate, wherein a dielectric layer is arranged on the substrate, a through hole is formed in the dielectric layer, and the bottom of the through hole is exposed out of the top surface of a conductive layer in the substrate; etching the exposed top surface of the conductive layer by adopting a sputtering etching process, and forming a concave groove in the conductive layer; forming a sacrificial layer on the side wall and the bottom of the concave groove and the side wall of the through hole; after the sacrificial layer is formed, removing the sacrificial layer; on one hand, the concave groove is etched by utilizing a sputtering etching process, so that the etching shape of the concave groove is ensured; on the other hand, a sacrificial layer is formed and serves as a buffer layer, and in the process of removing the sacrificial layer, part of the conducting layer at the bottom of the sacrificial layer can be oxidized while part of the conducting layer can be taken away, so that the loss and the oxidation can be well controlled, the consistent contact resistance at the bottom of the through hole is ensured, and the performance of the finally formed semiconductor device is improved conveniently.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor device.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. The device is widely used as the most basic semiconductor device at present, and the traditional planar device has weak control capability on channel current, short channel effect is generated to cause leakage current, and finally the electrical performance of the semiconductor device is influenced.
In the manufacturing process of a semiconductor device, it is necessary to form a contact hole in a source region, a drain region, a gate structure, or the like of a transistor, fill a conductive material in the contact hole to form a conductive layer, and form a metal layer as a connection layer with the metal layer 1(M1) on the conductive layer after forming the conductive layer, so as to electrically connect the transistor to the outside. However, in the process of forming the metal layer on the conductive layer, the conductive layer is damaged, so that the conductive layer is lost, the difference of the interface connection between the conductive layer and the metal layer is large, the difference of the contact resistance is large, the performance of the formed semiconductor device is greatly different electrically, the yield of the formed semiconductor device is affected, and the use of the semiconductor device is limited.
Therefore, how to ensure the quality of the formed conductive layer, ensure that the interface connection difference between the conductive layer and the metal layer is small, and ensure the consistency of the electrical properties of the formed semiconductor device, thereby improving the properties of the formed final semiconductor device is a problem which needs to be solved urgently at present.
Disclosure of Invention
The invention provides a method for forming a semiconductor device, which ensures that the formed semiconductor device has higher quality.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including providing a substrate, the substrate having a dielectric layer thereon, the dielectric layer having a through hole therein, the bottom of the through hole exposing the top surface of a conductive layer in the substrate; etching the exposed top surface of the conductive layer by adopting a sputtering etching process, and forming a concave groove in the conductive layer; forming a sacrificial layer on the side wall and the bottom of the concave groove and the side wall of the through hole; and after the sacrificial layer is formed, removing the sacrificial layer.
Optionally, the parameters of the sputter etching process include argon gas, wherein the flow rate of the argon gas is 0-50 sccm, the source radio frequency power is 200W-1000W, and the bias power is 200W-1000W.
Optionally, after removing the sacrificial layer, the method further includes: and forming metal layers in the through holes and the concave grooves.
Optionally, after removing the sacrificial layer and before forming the metal layer, the method further includes: and carrying out reduction treatment on the surface of the conductive layer at the bottom of the concave groove.
Optionally, the parameters of the reduction processing include: the mixed gas of argon and hydrogen, wherein the flow rate of the mixed gas is 0-1000 sccm, the source radio frequency power is 200-1000W, and the bias power is 200-1000W.
Optionally, the sacrificial layer is made of titanium nitride or tantalum nitride or amorphous silicon.
Optionally, the step of forming the metal layer includes: forming an initial metal layer in the through hole, the concave groove and the dielectric layer; and flattening the initial metal layer until the surface of the dielectric layer is exposed to form the metal layer.
Optionally, the process of forming the initial metal layer is a chemical vapor deposition process, a selective growth process, or a physical vapor deposition process.
Optionally, the thickness of the sacrificial layer is less than or equal to
Optionally, the concave groove is a U-shaped groove structure.
Compared with the prior art, the technical scheme of the invention has the following advantages:
exposing the conducting layer in the substrate, and etching the top surface of the exposed conducting layer by a sputtering etching process to form a concave groove; forming sacrificial layers on the side walls and the bottoms of the concave grooves and the side walls of the through holes; then removing the sacrificial layer, and forming a metal layer in the through hole and the concave groove; on one hand, the concave groove is etched by utilizing a sputtering etching process, so that the etching shape of the concave groove is ensured; on the other hand, a sacrificial layer is formed and serves as a buffer layer, and during the process of removing the sacrificial layer, can take away part of the conductive layer and oxidize part of the conductive layer at the bottom of the sacrificial layer, and the deletion and the oxidation can be well controlled, since the conductive layer is partially removed during the process of removing the sacrificial layer, the size of the concave groove in the transverse direction is enlarged, so that in the process of forming the metal layer, the damage to the bottom conductive layer caused by the corrosive liquid in the process of planarizing the metal layer is reduced, this is because the size of the concave groove in the transverse direction becomes larger, the flow path of the etching liquid is increased, and at the same time, the capillary effect is reduced, therefore, the damage of the corrosive liquid to the conducting layer at the bottom of the metal layer is reduced, the difference of connection between the metal layer and the conducting layer is reduced, consistent contact resistance is ensured, and the performance of the finally formed semiconductor device is improved.
Drawings
Fig. 1to 3 are schematic structural views of a semiconductor device formation process in one embodiment;
fig. 4 to 9 are schematic structural diagrams illustrating a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
In the formation of a semiconductor device, after a conductive layer is formed, a via hole needs to be formed in the conductive layer, and a metal layer is formed in the via hole as a connection with the upper metal layer 1(M1), so that the connection between a transistor and an external circuit can be realized when the semiconductor device is used. For a transistor, a plurality of conductive layers need to be formed, and then, a corresponding through hole inner metal layer is formed, but in the process of forming the metal layer at present, not only the difference of the interface connection between the conductive layer in the through hole and the metal layer is large, but also the difference of the connection between the conductive layer in different through holes and the metal layer is large, so that the contact resistance at the bottom of the through hole is also inconsistent, and thus, the performance of the formed semiconductor device is poor, and the use of the semiconductor device is influenced.
For convenience of illustration, only one conductive layer is shown in the drawings.
Referring first to fig. 1, a substrate 100 is provided, the substrate 100 has a dielectric layer 101 thereon, the dielectric layer 101 has a through hole 102 therein, and the bottom of the through hole 102 exposes the top surface of a conductive layer 103 in the substrate 100.
Referring to fig. 2, the top surface of the conductive layer 103 at the bottom of the through hole 102 is wet etched to form a concave groove 104.
Referring to fig. 3, a metal layer 105 is formed in the concave groove 104 and the via hole 102.
The step of forming the metal layer 105 includes: forming an initial metal layer (not shown) in the concave groove 104, the through hole 102 and the surface of the dielectric layer 101, and planarizing the initial metal layer until the surface of the dielectric layer 101 is exposed to form the metal layer 105.
The inventors found that when the top surface of the conductive layer 103 at the bottom of the via 102 is wet etched to form the concave groove 104, the shape of the concave groove 104 is uncontrollable, which results in large difference of contact interface between the metal layer 105 and the conductive layer 103 and large difference of contact resistance in the via 102; meanwhile, in the process of forming the metal layer 105, in the process of planarization, corrosive liquid can permeate the surface of the conductive layer 103 along the gap between the metal layer 105 and the dielectric layer 101 to damage the conductive layer 103, so that the conductive layer 103 is lost, the performance of a formed semiconductor device is reduced, and the use of the semiconductor device is limited.
The inventor researches and discovers that after the conducting layer in the substrate is exposed, the top surface of the exposed conducting layer is etched by a sputtering etching process to form a concave groove; forming sacrificial layers on the side walls and the bottoms of the concave grooves and the side walls of the through holes; then removing the sacrificial layer, and forming a metal layer in the through hole and the concave groove; on one hand, the concave groove is etched by utilizing a sputtering etching process, so that the etching shape of the concave groove is ensured; on the other hand, a sacrificial layer is formed and serves as a buffer layer, and during the process of removing the sacrificial layer, can take away part of the conductive layer and oxidize part of the conductive layer at the bottom of the sacrificial layer, and the deletion and the oxidation can be well controlled, since the conductive layer is partially removed during the process of removing the sacrificial layer, the size of the concave groove in the transverse direction is enlarged, so that in the process of forming the metal layer, the damage to the bottom conductive layer caused by the corrosive liquid in the process of planarizing the metal layer is reduced, this is because the size of the concave groove in the transverse direction becomes larger, the flow path of the etching liquid is increased, and at the same time, the capillary effect is reduced, therefore, the damage of the corrosive liquid to the conducting layer at the bottom of the metal layer is reduced, the difference of connection between the metal layer and the conducting layer is reduced, consistent contact resistance is ensured, and the performance of the finally formed semiconductor device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 9 are schematic structural diagrams illustrating a semiconductor device forming process according to an embodiment of the present invention.
Referring first to fig. 4, a substrate 200 is provided, the substrate 200 has a dielectric layer 201 thereon, the dielectric layer 201 has a through hole 202 therein, and the bottom of the through hole 202 exposes the top surface of a conductive layer 203 in the substrate 200.
In this embodiment, the bottom of the via 202 exposes a portion of the top surface of the conductive layer 203.
In this embodiment, the base 200 further includes a substrate, and the conductive layer 203 is located on the substrate and includes a memory device, a logic device, and the like on the substrate.
In this embodiment, the conductive layer 203 is a metal layer, and is formed above the source-drain doped layer for electrically connecting the source-drain doped layer with the outside.
In this embodiment, the material of the conductive layer 203 is cobalt (Co); in other embodiments, the material of the conductive layer 203 may also be a metal material such as copper, aluminum, or the like.
In this embodiment, only one of the conductive layers 203 within the substrate 200 is illustrated.
In this embodiment, the dielectric layer 201 is made of silicon oxide.
In other embodiments, the material of the dielectric layer 201 may also be silicon nitride, silicon nitride boride, silicon oxycarbide, silicon oxynitride, or the like.
In this embodiment, the dielectric layer 201 is formed by chemical vapor deposition, and the process parameters of the chemical vapor deposition process include that the adopted gas includes oxygen and ammonia (NH)3) And N (SiH)3)3The flow rate of oxygen is 20 sccm-10000 sccm, and ammonia (NH)3) The flow rate of the gas is 20sccm to 10000sccm, N (SiH)3)3The flow rate of the gas is 20 sccm-10000 sccm, the pressure of the chamber is 0.01-10 torr, and the temperature is 30-90 ℃.
In this embodiment, the process of forming the through hole 202 is a dry etching process; in other embodiments, the via 202 may be formed by a wet etching process.
In this embodiment, the parameters of the dry etching process include: the gas used comprises CF4And CH3F，CF4The flow rate of (1) is 20sccm to 200sccm, CH3The flow rate of F is 20 sccm-50 sccm, the source radio frequency power is 200W-500W, and the chamber pressure is 1 Torr-10 Torr.
In this embodiment, the reason for using the dry etching process is that the etching rate of the dry etching in the longitudinal direction is greater than that of the etching in the lateral direction, so that the influence on the lateral cross section of the through hole 202 can be reduced in the process of forming the through hole 202.
In this embodiment, the through hole 202 is formed to provide a space for forming a metal layer on the surface of the conductive layer 203.
Referring to fig. 5, a sputter etching process is used to etch the exposed top surface of the conductive layer 203, and a concave groove 204 is formed in the conductive layer 203.
In this embodiment, the concave groove 204 is a "U" groove structure.
In this embodiment, the advantage of providing the concave groove 204 as a "U" groove structure is that: subsequently, in the process of removing the sacrificial layer, the concave groove 204 is easily expanded in the transverse direction (X direction), so that the length of the concave groove 204 in the transverse direction is increased, thereby increasing the flow path of the etching liquid in the process of forming the metal layer, reducing the etching liquid reaching the surface of the conductive layer 203, reducing the damage and the loss of the conductive layer 203 caused by the etching liquid, and contributing to improving the quality of the conductive layer 203.
In this embodiment, the parameters of the sputter etching process include argon gas, wherein the flow rate of argon gas (Ar) is 0-50 sccm, the source rf power is 200W-1000W, and the bias power is 200W-1000W.
In this embodiment, the concave groove 204 is formed by using a sputter etching process, so that the sputter etching process can well control the shape of the formed concave groove 204, and simultaneously, the surface quality of the concave groove 204 can be controlled, and the concave groove 204 can be ensured to have uniform flatness everywhere, so that on one hand, the difference of the connection interface between a metal layer and the concave groove 204 can be reduced when the metal layer is formed subsequently; on the other hand, when the metal layers are formed in the concave grooves 204 at the bottoms of different through holes, the difference of the interfaces between the metal layers in different through holes and the conductive layer 203 is ensured to be small due to the small difference of the shapes of the different concave grooves 204, so that the difference of the contact resistance in different through holes is ensured to be small, and the uniformity of the electrical properties of the formed semiconductor device is improved.
Referring to fig. 6, a sacrificial layer 205 is formed on the sidewalls and bottom of the concave groove 204 and the sidewalls of the via hole 202.
In this embodiment, the material of the sacrificial layer 205 is titanium nitride (TiN);
in other embodiments, the material of the sacrificial layer 205 may also be tantalum nitride (TaN) or amorphous silicon (α -Si).
In this embodiment, the sacrificial layer 205 acts as a buffer, so that the conductive layer 203 at the bottom of the concave groove 204 is not lost too much in the subsequent process, and the loss of the conductive layer 203 can be well controlled.
In this embodiment, the reason why the sacrificial layer 205 can play a role of buffering is that: instead of the conventional method of expanding the concave groove 204 in the transverse direction (X-axis direction) by direct wet etching, the conductive layer 203 at the bottom of the sacrificial layer 205 is partially taken away during the process of removing the sacrificial layer 205, so that the concave groove 204 is expanded in the transverse direction. The length of the concave groove 204 in the transverse direction is increased, and on the other hand, the missing amount of the conductive layer 203 is controlled, so that the buffer effect is achieved.
In this embodiment, the process of forming the sacrificial layer 205 is an atomic layer deposition process; in other embodiments, the process of forming the sacrificial layer 205 may also be a chemical vapor deposition process, a physical vapor deposition process, or the like.
In the present embodiment, the reason why the sacrificial layer 205 is formed by the atomic layer deposition process is that: the sacrificial layer 205 can be formed with good uniformity and coverage gradient.
In this embodiment, the thickness of the sacrificial layer 205 is less than or equal to
When the thickness of the sacrificial layer 205 is larger than
When the temperature is high. The thickness of the sacrificial layer 205 is too thick, so that the time for removing the sacrificial layer 205 is longer; and is not easy to be removed completely because of being too thick; meanwhile, because the time for removing the sacrificial layer 205 is longer, the amount of the conductive layer 203 oxidized at the bottom is more, and then the time for subsequent reduction is longer, and the phenomenon that the reduction is not complete easily occurs, thereby affecting the performance of the finally formed semiconductor device.
Referring to fig. 7, after the sacrificial layer 205 is formed, the sacrificial layer 205 is removed.
In this embodiment, during the process of removing the sacrificial layer 205, a portion of the conductive layer 203 is removed at the same time, and the surface of the conductive layer 203, which is in contact with the sacrificial layer 205, is oxidized due to the action of the etching solution to form an oxide 207, so that the size of the concave groove 204 in the transverse direction (X axis) is increased, and thus when the metal layer is subsequently planarized, the etching solution used in the planarization process does not reach the surface of the conductive layer 203, the planarization process is already finished, the metal layer is already formed, and the damage to the conductive layer 203 is reduced.
In this embodiment, the process of removing the sacrificial layer 205 is to use a mixed solution of hydrogen peroxide with a concentration of 1% to 10% and ammonia water with a concentration of 1% to 10%, and the temperature is 50 ℃ to 70 ℃.
Referring to fig. 8, the surface of the conductive layer 203 at the bottom of the concave groove 204 is subjected to a reduction treatment.
In this embodiment, in the process of removing the sacrificial layer 205, the conductive layer 203 contacted to the bottom of the sacrificial layer 205 is oxidized to form an oxide, and at this time, if the oxide is not reduced to a metal, the contact resistance at the bottom of the through hole 202 is increased, so that a phenomenon of heat generation easily occurs in the process of forming a semiconductor device, and the use of the semiconductor device is limited.
In this embodiment, the parameters of the reduction process include: the mixed gas of argon and hydrogen, wherein the flow rate of the mixed gas is 0-1000 sccm, the source radio frequency power is 200-1000W, the bias power is 200-1000W, and the temperature is room temperature.
Referring to fig. 9, a metal layer 206 is formed in the via 202 and the groove 204.
The step of forming the metal layer 206 includes: forming an initial metal layer (not shown) in the via 202, the groove 204 and the dielectric layer 201; and flattening the initial metal layer until the surface of the dielectric layer 201 is exposed, and forming the metal layer 206.
In this embodiment, since a portion of the conductive layer 203 is removed in the process of removing the sacrificial layer 205, so that the size of the concave groove 204 in the transverse direction is increased, in the process of planarizing the initial metal layer, a flow path through which the etching solution can reach the surface of the conductive layer 203 is increased, and at the same time, a capillary effect is reduced, so that damage of the etching solution to the conductive layer at the bottom of the metal layer in the planarization process is reduced, a difference in connection between the metal layer and the conductive layer is reduced, a uniform contact resistance is ensured, and performance of a finally formed semiconductor device is improved.
In this embodiment, the process of forming the initial metal layer is a selective growth process.
In other embodiments, the process of forming the initial metal layer may also be a chemical vapor deposition process, or a physical vapor deposition process.
In this embodiment, the material of the initial metal layer is tungsten.
In other embodiments, the material of the initial metal layer may also be Ru or cobalt (Co) or titanium (Ti).
In this embodiment, the reason for forming the initial metal layer by using the selective growth process is that the initial metal layer which is selectively grown grows from the bottom to the top, so that the formed initial metal layer is compact inside and has no defects of holes inside, thereby ensuring the performance of the formed semiconductor device.
In this embodiment, the process parameters for forming the initial metal layer include: the reaction gas comprises WF6Gas and H2Wherein the WF6The gas flow rate of the gas is 50-1000 sccm, and the gas flow rate is H2The gas flow rate of (2) is 500-20000 sccm; the reaction temperature is 100-400 ℃; the pressure of the chamber is 2-100 torr.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein a dielectric layer is arranged on the substrate, a through hole is formed in the dielectric layer, and the bottom of the through hole is exposed out of the top surface of a conductive layer in the substrate;
etching the exposed top surface of the conductive layer by adopting a sputtering etching process, and forming a concave groove in the conductive layer;
forming a sacrificial layer on the side wall and the bottom of the concave groove and the side wall of the through hole;
and after the sacrificial layer is formed, removing the sacrificial layer.
2. The method of claim 1, wherein the parameters of the sputter etch process include argon gas, wherein the flow rate of the argon gas is 0-50 sccm, the source rf power is 200W-1000W, and the bias power is 200W-1000W.
3. The method of forming of claim 1, wherein after removing the sacrificial layer, further comprising:
and forming metal layers in the through holes and the concave grooves.
4. The method of forming of claim 3, wherein after removing the sacrificial layer, prior to forming the metal layer, further comprising: and carrying out reduction treatment on the surface of the conductive layer at the bottom of the concave groove.
5. The method of forming as claimed in claim 4, wherein the parameters of the reduction process include: the mixed gas of argon and hydrogen, wherein the flow rate of the mixed gas is 0-1000 sccm, the source radio frequency power is 200-1000W, and the bias power is 200-1000W.
6. The method of claim 1, wherein the sacrificial layer is made of titanium nitride or tantalum nitride or amorphous silicon.
7. The method of forming of claim 3, wherein forming the metal layer comprises:
forming an initial metal layer in the through hole, the concave groove and the dielectric layer;
and flattening the initial metal layer until the surface of the dielectric layer is exposed to form the metal layer.
8. The method of forming of claim 7, wherein the process of forming the initial metal layer is a chemical vapor deposition process, a selective growth process, or a physical vapor deposition process.
9. The forming method of claim 1, wherein a thickness of the sacrificial layer is equal to or less than
10. The method of forming as claimed in claim 1 wherein said concave trough is a "U" trough configuration.
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| CN202011056435.XA CN114334797A (en) | 2020-09-30 | 2020-09-30 | Method for forming semiconductor device |
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| CN202011056435.XA CN114334797A (en) | 2020-09-30 | 2020-09-30 | Method for forming semiconductor device |
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