WO2024098567A1 - Memory, semiconductor structure and manufacturing method for semiconductor structure - Google Patents

Abstract

The embodiments of the present disclosure relate to a memory, a semiconductor structure and a manufacturing method for the semiconductor structure. The manufacturing method for the semiconductor structure comprises: providing a substrate, and forming on the substrate a conductive material layer; patterning the conductive material layer to form a plurality of conductive structures and grooves located between adjacent conductive structures; by using a first process, forming a first isolation layer conformally covering the conductive structures and the grooves; and by using a second process, forming a second isolation layer covering the first isolation layer, the density of the first isolation layer being greater than the density of the second isolation layer. The manufacturing method for the semiconductor structure forms the first isolation layer conformally covering the conductive structures and the grooves and the second isolation layer covering the first isolation layer, the first isolation layer and the second isolation layer collectively providing insulation and protection for the conductive structures, thereby avoiding or reducing the occurrence of short circuits among the conductive structures.

Description

Memory, semiconductor structure and method for manufacturing the same

Related Applications

The present disclosed embodiments claim priority to Chinese patent application number 202211412099.7, filed on November 11, 2022, and entitled “Memory, Semiconductor Structure and Method for Making the Same,” the entire text of which is hereby incorporated by reference.

Technical Field

The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a memory, a semiconductor structure and a preparation method thereof.

Background technique

Generally, a memory device includes a core and a peripheral region (also referred to as a core area or core region) for forming circuits for operating and controlling memory cells. In the core region, a sub-word line driver (SWD) connected to a word line is formed.

However, the existing sub-word line driver defines many metal lines in a small space, which easily causes the problem of short circuit between metal lines. Therefore, how to avoid metal line short circuit is a problem that needs to be solved urgently.

Summary of the invention

Based on this, the present disclosure provides a memory, a semiconductor structure and a method for manufacturing the same, which can effectively avoid or reduce the short circuit problem between conductive structures, thereby improving the production yield of the semiconductor structure.

On the one hand, the present disclosure provides a method for preparing a semiconductor structure, which comprises the following steps: providing a substrate and forming a conductive material layer on the substrate; patterning the conductive material layer to form a plurality of conductive structures and grooves between adjacent conductive structures; using a first process to form a first isolation layer that conformally covers the conductive structures and the grooves; using a second process to form a second isolation layer covering the first isolation layer; wherein the density of the first isolation layer is greater than the density of the second isolation layer.

In some embodiments, the thickness of the second isolation layer is greater than the thickness of the first isolation layer.

In some embodiments, the first process includes an atomic layer deposition process; and the second process includes a low pressure chemical vapor deposition process.

In some embodiments, a process temperature of the first process is lower than a process temperature of the second process.

In some embodiments, the process temperature of the first process ranges from 480°C to 580°C; the process temperature of the second process ranges from 600°C to 780°C.

In some embodiments, the thickness of the first isolation layer ranges from 3 nm to 5 nm; The thickness ranges from 30nm to 50nm.

In some embodiments, the material of the first isolation layer and the material of the second isolation layer both include nitride.

In some embodiments, the conductive structure includes a diffusion barrier layer and a metal layer on the diffusion barrier layer.

In some embodiments, a contact hole is formed in the substrate; the diffusion barrier layer conformally covers the contact hole and covers a portion of the top surface of the substrate; and the metal layer covers the diffusion barrier layer and fills the contact hole.

In some embodiments, before the first process is used to form the first isolation layer covering the conductive structure and the substrate, the preparation method further includes: performing plasma nitriding treatment on the exposed surface of the metal layer.

In some embodiments, the radio frequency power of the plasma nitriding treatment ranges from 500W to 1000W.

In some embodiments, after the exposed surface of the metal layer is subjected to plasma nitriding treatment and before the first process is used to form a first isolation layer covering the conductive structure and the substrate, the preparation method further includes: cleaning the metal layer to remove residual impurities on the surface of the metal layer.

In some embodiments, the metal layer is cleaned with deionized water; wherein the temperature of the deionized water ranges from 60° C. to 80° C.; and the cleaning time of the deionized water ranges from 20s to 60s.

On the other hand, the present disclosure provides a semiconductor structure, including a substrate, a plurality of conductive structures, a first isolation layer and a second isolation layer; there are grooves between adjacent conductive structures; the first isolation layer conformally covers the conductive structures and the grooves; the second isolation layer covers the first isolation layer; wherein the density of the first isolation layer is greater than the density of the second isolation layer.

In some embodiments, the thickness of the second isolation layer is greater than the thickness of the first isolation layer.

In some embodiments, the thickness of the first isolation layer ranges from 3 nm to 5 nm; the thickness of the second isolation layer ranges from 30 nm to 50 nm.

In some embodiments, the conductive structure includes a diffusion barrier layer and a metal layer on the diffusion barrier layer.

In some embodiments, a contact hole is provided in the substrate; the diffusion barrier layer conformally covers the contact hole and covers a portion of the top surface of the substrate; and the metal layer covers the diffusion barrier layer and fills the contact hole.

In some embodiments, a metal nitride layer is disposed on the exposed surface of the metal layer; the metal element in the metal nitride layer is the same as the metal element in the metal layer.

On the other hand, the present disclosure provides a memory, comprising the semiconductor structure provided by any of the above embodiments.

The memory, semiconductor structure and preparation method thereof provided by the present disclosure have at least the following beneficial effects:

In the memory, semiconductor structure and preparation method thereof provided by the present disclosure, the first isolation layer and the second isolation layer can together form an isolation structure to provide more effective insulation and protection for the conductive structure, thereby effectively avoiding or reducing the problem of short circuits between the conductive structures. In addition, the first isolation layer that conformally covers the conductive structure and the groove is first formed by a first process, and then the second isolation layer that covers the first isolation layer is formed by a second process, so that the density of the first isolation layer is The density is greater than that of the second isolation layer, that is, the first isolation layer close to the conductive structure has a greater density, thereby effectively avoiding or reducing the short circuit problem caused by metal precipitation on the surface of the conductive structure or metal residue on the surface of the conductive structure.

Furthermore, the memory, semiconductor structure and preparation method thereof provided by the present disclosure are suitable for forming a sub-word line driver for connecting to a word line in the core and peripheral regions of a memory device, and in this case, the conductive structure can be used as a metal line in the sub-word line driver. Usually, a sub-word line driver defines multiple conductive structures in a very small space. In the semiconductor structure and preparation method thereof provided by the present disclosure, the conductive structure is insulated and protected by the first isolation layer and the second isolation layer, which can avoid or reduce the short circuit problem between multiple conductive structures in the sub-word line driver, thereby facilitating the improvement of the production yield and the reliability of the semiconductor structure.

The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are merely embodiments of the embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without creative work.

FIG1 is a flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

FIG2 is a schematic cross-sectional view of a structure obtained in step S100 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

FIG3 is a schematic cross-sectional view of a structure obtained in step S200 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

FIG4 is a schematic cross-sectional view of a structure obtained in step S300 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

FIG5 is a schematic cross-sectional view of a structure obtained in step S400 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a cross-sectional structure of a structure obtained by forming a metal nitride layer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure.

Detailed ways

The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present disclosure. It is obvious that the described embodiments are only a part of the embodiments of the present disclosure, not all of them. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the embodiments of the present disclosure.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used in the specification of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

It should be understood that when an element or layer is referred to as being "on...", "adjacent...", it may be directly on other elements or layers, between other adjacent elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types and/or portions, these elements, components, regions, layers, doping types and/or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, a first isolation layer may be referred to as a second isolation layer, and similarly, a second isolation layer may be referred to as a first isolation layer.

Spatially relative terms such as "on..." may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as on... will be oriented "below" the other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

When used herein, the singular form "said/the" may also include the plural form, unless the context clearly indicates otherwise. It should also be understood that when the terms "compose" and/or "comprise" are used in this specification, the presence of the features, integers, steps, operations, elements and/or components may be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups is not excluded.

Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and/or tolerances are anticipated. Accordingly, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

In the related art, a memory device such as a dynamic random access memory (DRAM) generally includes a memory cell (cell, also known as a unit) array region and a core and peripheral region (also known as a core region or core region). The core and peripheral regions are regions in which circuits for operating and controlling memory cells are formed. In the core region, a bit line sense amplifier (BLSA) connected to a bit line and a sub-word line driver (SWD) connected to a word line are provided.

However, the existing sub-word line driver defines many metal lines in a small space, which easily causes the problem of short circuit between metal lines. Therefore, how to avoid metal line short circuit is a problem that needs to be solved urgently.

In view of the above-mentioned deficiencies in the prior art, the present disclosure provides a semiconductor structure and a preparation method thereof, which can effectively avoid or reduce the short circuit problem between conductive structures, thereby improving the production yield of the semiconductor structure, and the details will be described in subsequent embodiments.

According to some embodiments of the present disclosure, a method for preparing a semiconductor structure is provided, which can be used for but is not limited to preparing semiconductor structures located in core and peripheral regions.

Referring to FIG. 1 , the method for preparing the semiconductor structure may include the following steps:

S100: providing a substrate, and forming a conductive material layer on the substrate.

S200: patterning the conductive material layer to form a plurality of conductive structures and grooves between adjacent conductive structures.

S300: forming a first isolation layer conformally covering the conductive structure and the groove by using a first process.

S400: forming a second isolation layer covering the first isolation layer by using a second process.

The density of the first isolation layer is greater than the density of the second isolation layer.

In the method for preparing the semiconductor structure provided in the above embodiment, a first isolation layer and a second isolation layer are formed, and the first isolation layer and the second isolation layer can together constitute an isolation structure. Compared with the single-layer isolation structure in the traditional semiconductor structure, such an isolation structure can provide more effective insulation and protection for the conductive structure, thereby effectively avoiding or reducing the short circuit problem between the conductive structures. In addition, in the method for preparing the semiconductor structure provided in the above embodiment, a first process is first used to form a first isolation layer that conformally covers the conductive structure and the groove, and then a second process is used to form a second isolation layer that covers the first isolation layer, so that the density of the first isolation layer is greater than the density of the second isolation layer, that is, the first isolation layer close to the conductive structure has a greater density, thereby effectively avoiding or reducing the short circuit problem caused by the precipitation of metal on the surface of the conductive structure or the presence of metal residue on the surface of the conductive structure.

Furthermore, the semiconductor structure provided in the above embodiment and its preparation method are suitable for forming a sub-word line driver for connecting to a word line in the core and peripheral regions of a memory device. In this case, the conductive structure can be used as a metal line (also called a metal interconnect line, a conductive line) in the sub-word line driver. Usually, a sub-word line driver defines multiple conductive structures in a very small space. In the preparation method of the semiconductor structure provided in the above embodiment, the conductive structure is insulated and protected by the first isolation layer and the second isolation layer, which can avoid or reduce the short circuit between multiple conductive structures in the sub-word line driver. This can help improve the production yield and reliability of semiconductor structures.

It should be noted that the density described in the present disclosure refers to: the average value of the gap size between the atoms or molecules of the material; the smaller the average gap, the smaller the porosity, and the higher the density; the larger the average gap, the larger the porosity, and the lower the density.

In one embodiment, the thickness of the second isolation layer is greater than the thickness of the first isolation layer.

In one embodiment, the first process may include an atomic layer deposition process; and the second process may include a low pressure chemical vapor deposition process.

In one embodiment, a process temperature of the first process is lower than a process temperature of the second process.

In one embodiment, the process temperature of the first process may be in the range of 480° C. to 580° C.; the process temperature of the second process may be in the range of 600° C. to 780° C.

In one embodiment, the thickness of the first isolation layer may range from 3 nm to 5 nm; the thickness of the second isolation layer may range from 30 nm to 50 nm.

In one embodiment, the material of the first isolation layer and the material of the second isolation layer both include nitride.

In one embodiment, the conductive structure may include a diffusion barrier layer and a metal layer covering the diffusion barrier layer.

In one embodiment, before the first isolation layer covering the conductive structure and the substrate is formed by the first process, the method for preparing the semiconductor structure may further include the following steps:

The exposed surface of the metal layer is subjected to plasma nitriding treatment.

In one embodiment, the radio frequency power of the plasma nitriding treatment ranges from 500W to 1000W.

In one embodiment, after the exposed surface of the metal layer is subjected to plasma nitriding treatment and before the first isolation layer covering the conductive structure and the substrate is formed by the first process, the method for preparing the semiconductor structure may further include the following steps:

The metal layer is cleaned to remove residual impurities on the surface of the metal layer.

In one of the embodiments, the metal layer can be cleaned with deionized water; wherein the temperature of the deionized water ranges from 60° C. to 80° C.; and the cleaning time of the deionized water ranges from 20s to 60s.

In order to more clearly illustrate the preparation method provided by the present disclosure, please refer to Figures 2 to 5 below to understand some embodiments of the present disclosure.

In step S100 , referring to FIG. 2 , a substrate 100 is provided, and a conductive material layer 200 is formed on the substrate 100 .

The preparation method provided in the present disclosure does not specifically limit the material of the substrate 100. As an example, the substrate 100 may include but is not limited to a silicon substrate, a sapphire substrate, a glass substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, etc. or a combination thereof.

It can be understood that in the preparation method provided in the present disclosure, the substrate 100 is not a blank substrate, that is, the substrate 100 has a Other electrical structures may be formed on the substrate 100 . For example, a transistor array, a buried bit line, a buried word line, or a contact structure may be formed in or on the substrate 100 .

In some embodiments, please continue to refer to FIG. 2 , the substrate 100 includes a base, and a shallow trench isolation structure 120 is provided in the base, and the shallow trench isolation structure 120 defines an active area 130 in the base, and the active area 130 may include a channel area and a source area 141 and a drain area 142 formed on two opposite sides of the channel area. The present disclosure does not specifically limit the form of the shallow trench isolation structure 120. As an example, the shallow trench isolation structure 120 may include but is not limited to a nitride-oxide-nitride (N-O-N) shallow trench isolation structure.

As an example, as shown in FIG. 2 , the substrate 100 may further include a gate structure 110 formed on the upper surface of the substrate and covering the channel region, and a source region 141 and a drain region 142 are located on opposite sides of the gate structure 110 .

As an example, as shown in FIG2 , the gate structure 110 includes a gate dielectric layer 111 and a gate stack structure 112 , wherein the gate dielectric layer 111 is located on the channel region, and the gate stack structure 112 is located on the upper surface of the gate dielectric layer 111 .

As an example, as shown in FIG2 , the substrate 100 may further include a first capping layer 161, a second capping layer 162 and a third capping layer 163. The first capping layer 161 is formed on the sidewall of the gate structure 110 and the upper surface of the substrate; the second capping layer 162 covers the first capping layer 161; and the third capping layer 163 covers the second capping layer 162.

In step S200 , referring to FIGS. 2 to 3 , the conductive material layer 200 is patterned to form a plurality of conductive structures 210 and grooves 220 located between adjacent conductive structures 210 .

As an example, patterning the conductive material layer 200 to form a plurality of conductive structures 210 and grooves 220 between adjacent conductive structures 210 includes but is not limited to the following steps:

As shown in FIG2 , a first mask material layer 201, a second mask material layer 202, and a third mask layer 203 are sequentially formed from bottom to top on the surface of the conductive material layer 200 away from the substrate 100. The third mask layer 203 is used as a graphic target pattern to define the position and shape of the conductive structure 210. Then, the graphic target pattern is sequentially transferred to the second mask material layer 202 and the first mask material layer 201 to form a second mask layer and a first mask layer.

As shown in FIG3 , the substrate 100 (for example, the third cap layer 163 in the substrate 100) is used as an etching stop layer, and the conductive material layer 200 is etched using the second mask layer and the first mask layer as masks to form a plurality of conductive structures 210 and grooves 220 located between adjacent conductive structures 210. After the conductive structures 210 and the grooves 220 are formed by etching, the second mask layer and the first mask layer are removed.

The present disclosure does not specifically limit the method for forming the third mask layer 203. As an example, the third mask material layer can be formed on the surface of the second mask material layer 202 away from the first mask material layer 201. Then, the third mask material layer is subjected to a photolithography process to form a graphical target pattern in the third mask material layer, and the third mask material layer is converted into the third mask layer 203.

It can be understood that in this process, a plurality of graphical target patterns arranged at intervals are formed in the third mask material layer. The intervals between the patterned target patterns define the position and shape of the groove 220. In some embodiments, by enlarging the intervals between adjacent patterned target patterns, the groove 220 between adjacent conductive structures 210 in step S200 is enlarged, which can further avoid or reduce the short circuit problem between the conductive structures.

The preparation method provided in the present disclosure does not specifically limit the structure of the conductive structure 210. In some embodiments, the conductive structure 210 may include a diffusion barrier layer and a metal layer covering the diffusion barrier layer.

The preparation method provided in the above embodiment can prevent the metal material in the metal layer from diffusing into the substrate and causing contamination by forming a diffusion barrier layer, thereby preventing the performance of the electrical structure formed in or on the substrate 100 from being degraded or even failing.

In some embodiments, please continue to refer to FIG. 2 , forming a conductive material layer 200 on the substrate 100 may include the following steps:

A diffusion barrier material layer 211 ′ is formed on the substrate 100 . Then, a metal material layer 212 ′ is formed to cover the diffusion barrier material layer 211 ′. The diffusion barrier material layer 211 ′ and the metal material layer 212 ′ together constitute the conductive material layer 200 .

In some embodiments, referring to FIGS. 2 to 3 , patterning the conductive material layer 200 to form a plurality of conductive structures 210 and grooves 220 between adjacent conductive structures 210 may include the following steps:

The conductive material layer 200 composed of the diffusion barrier material layer 211' and the metal material layer 212' is patterned; wherein the diffusion barrier material layer 211' forms a diffusion barrier layer 211 after patterning; the metal material layer 212' forms a metal layer 212 after patterning, and the diffusion barrier layer 211 and the metal layer 212 together form a conductive structure 210.

The preparation method provided in the present disclosure does not specifically limit the material of the diffusion barrier layer 211. It is understandable that the material of the diffusion barrier layer 211 only needs to consider its ability to block the diffusion of the metal layer 212 material, without considering its conductive properties. Therefore, the diffusion barrier layer 211 can be selected from a conductive diffusion barrier layer material, or an insulating diffusion barrier layer material with better diffusion ability of the barrier metal layer 212; wherein the conductive diffusion barrier layer material may include but is not limited to titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), etc. or a combination thereof; the insulating diffusion barrier layer material may include but is not limited to silicon nitride (SiN), silicon oxynitride (SiON), etc. or a combination thereof.

The preparation method provided in the present disclosure does not specifically limit the material of the metal layer 212. As an example, the material of the metal layer 212 may include, but is not limited to, copper (Cu), gold (Au), silver (Ag), tin (Sn), lead (Pb), tungsten (W), etc. or a combination thereof.

3 , in some embodiments, a contact hole (not shown in FIG. 3 ) may be formed in the substrate 100, such as two contact holes formed on opposite sides of the gate structure 110, for respectively exposing the source region 141 or the drain region 142. The conductive structure 210 may be formed in the contact hole to connect to the source region 141 or the drain region 142.

For example, in the conductive structure 210 , the diffusion barrier layer 211 may conformally cover the contact hole and cover a portion of the top surface of the substrate 100 ; the metal layer 212 may cover the diffusion barrier layer 211 and fill the contact hole.

In some embodiments, please continue to refer to FIG. 3 , the substrate 100 may further include an isolation spacer 150 located on two opposite sides of the gate structure 110 and between the gate structure 110 and the conductive structure 210 .

In step S300 , referring to FIG. 4 , a first isolation layer 300 conformally covering the conductive structure 210 and the groove 220 is formed by a first process.

In step S400 , referring to FIG. 5 , a second isolation layer 400 covering the first isolation layer 300 is formed by a second process.

The density of the first isolation layer 300 is greater than the density of the second isolation layer 400 .

The preparation method provided in the present disclosure does not specifically limit the thickness of the first isolation layer 300 and the second isolation layer 400. In some embodiments, the thickness of the second isolation layer 400 is greater than the thickness of the first isolation layer 300.

As an example, the thickness of the first isolation layer 300 may range from 3 nm to 5 nm; for example, the thickness of the first isolation layer 300 may be 3 nm, 3.5 nm, 4 nm, 4.5 nm or 5 nm, etc. As an example, the thickness of the second isolation layer 400 may range from 30 nm to 50 nm; for example, the thickness of the second isolation layer 400 may be 30 nm, 35 nm, 40 nm, 45 nm or 50 nm, etc.

In some embodiments, the first process used to form the first isolation layer 300 in step S300 includes but is not limited to atomic layer deposition (ALD).

In the method for preparing the semiconductor structure provided in the above embodiment, since the first isolation layer 300 that conformally covers the conductive structure 210 and the groove 220 is formed by the atomic layer deposition process, the obtained first isolation layer 300 has a high density and good balance. In addition, the atomic layer deposition process is a technology that forms a thin film by alternately saturating chemical adsorption of multiple different gases, thereby growing layer by layer at the atomic level. Therefore, in the method for preparing the semiconductor structure provided in the above embodiment, since the first isolation layer 300 that conformally covers the conductive structure 210 and the groove 220 is formed by the atomic layer deposition process, the thickness of the obtained first isolation layer 300 can be effectively controlled by adjusting the number of depositions.

In some embodiments, the first process used to form the first isolation layer 300 in step S300 may be a plasma enhanced atomic layer deposition process (PEALD). The plasma enhanced atomic layer deposition process is an extension of the atomic layer deposition process. Through plasma gas bombardment, a large number of active free radicals are generated, which enhances the reactivity of the precursor material, thereby expanding the selection range and application requirements of the atomic layer deposition process for the precursor source, shortening the reaction cycle time, and also reducing the requirements for the process temperature, so that low-temperature or even room-temperature deposition can be achieved.

In some embodiments, the second process used to form the second isolation layer 400 in step S400 includes but is not limited to a low pressure chemical vapor deposition process (Low Pressure Chemical Vapor Deposition, abbreviated as LP-CVD).

The present disclosure does not specify the process temperature of the first process in step S300 or the process temperature of the second process in step S400. In some embodiments, the process temperature of the first process is lower than the process temperature of the second process.

As an example, the process temperature of the first process may range from 480°C to 580°C; for example, the process temperature of the first process may be 480°C, 500°C, 520°C, 540°C, 560°C, or 580°C, etc. As an example, the process temperature of the second process may range from 600°C to 780°C; for example, the process temperature of the second process may be 600°C, 640°C, 680°C, 720°C, or 780°C, etc.

The present disclosure does not specifically limit the pressure in the reaction chamber during the second process in step S400. As an example, the pressure in the reaction chamber during the second process may be in the range of 0.15 torr to 0.25 torr. For example, the pressure in the reaction chamber during the second process may be in the range of 0.15 torr, 0.175 torr, 0.2 torr, 0.225 torr or 0.25 torr, etc. The pressure in the reaction chamber during the second process is in the range of 0.15 torr to 0.25 torr, which is beneficial to improve the process rate of the second process.

The preparation method provided in the present disclosure does not specifically limit the materials of the first isolation layer 300 and the second isolation layer 400. In some embodiments, the material of the first isolation layer 300 and the material of the second isolation layer 400 both include nitride.

Some embodiments of the present disclosure are described in detail below by taking the example that the material of the second isolation layer 400 all includes nitride.

In some embodiments, in step S400, a low pressure chemical vapor deposition process is used to form a second isolation layer 400 covering the first isolation layer 300, and the material of the second isolation layer 400 includes nitride. The present disclosure does not specifically limit the method of forming the second isolation layer 400 by the low pressure chemical vapor deposition process. As an example, the second isolation layer 400 can be formed by, but is not limited to, a chemical reaction of dichlorosilane (SiH ₂ Cl ₂ , also known as DCS).

In some embodiments, the chemical reaction formula of the low pressure chemical vapor deposition process using dichlorosilane is as follows:
3SiH ₂ Cl ₂ +4NH ₃ →Si ₃ N ₄ +6HCl+6H ₂ ;
HCl + NH ₃ → NH ₄ Cl;
2SiH ₂ Cl ₂ +10NH ₃ →Si ₃ N ₄ +6NH ₄ Cl+6H ₂ .

In the method for preparing the semiconductor structure provided in the above embodiment, in step S400, silicon chloride (Si ₃ N ₄ ) can be formed as the second isolation layer 400 by using dichlorosilane using a low pressure chemical vapor deposition process, and ammonium chloride (NH ₄ CL) and hydrogen (H ₂ ) are by-products in the above chemical reaction. The internal stress of the second isolation layer 400 formed under this condition ranges from 0.8×10 ¹⁰ dyne/cm ² to 1.2×10 ¹⁰ dyne/cm ² ; for example, the internal stress of the second isolation layer 400 formed under this condition is 0.8×10 ¹⁰ dyne/cm ² , 0.9dyne/cm ² , 1dyne/cm ² , 1.1dyne/cm ² or 1.2×10 ¹⁰ dyne/cm ² , etc.

The present disclosure does not specifically limit the gas flow rate of dichlorosilane in the method for preparing the above-mentioned semiconductor structure; as an example, the gas flow rate of dichlorosilane can range from 30 sccm to 60 sccm; for example, the gas flow rate of dichlorosilane can be 30 sccm, 40 sccm, 50 sccm or 60 sccm, etc.

The present disclosure does not make any specific reference to the gas flow rate of ammonia (NH ₃ ) in the method for preparing the semiconductor structure. Limitation; as an example, the gas flow rate of ammonia can range from 150 sccm to 600 sccm; for example, the gas flow rate of dichlorosilane can be 150 sccm, 250 sccm, 350 sccm, 500 sccm or 600 sccm, etc.

In some embodiments, the gas flow ratio of dichlorosilane to ammonia may range from 0.1 to 0.2; for example, the gas flow ratio of dichlorosilane to ammonia may be 0.1, 0.125, 0.15, 0.175 or 0.2, etc.

In some embodiments, before forming the first isolation layer 300 covering the conductive structure 210 and the substrate 100 by using the first process in step S300, the method for preparing the semiconductor structure may further include the following steps:

The exposed surface of the metal layer 212 is subjected to a plasma nitriding treatment.

As an example, microwaves may be used to perform remote plasma nitriding (RPN) on the exposed surface of the metal layer 212.

In the method for preparing the semiconductor structure provided in the above embodiment, the exposed surface of the metal layer 212 can be protected by performing plasma nitriding treatment on the exposed surface of the metal layer 212 .

The present disclosure does not specifically limit the RF power when performing plasma nitriding treatment on the exposed surface of the metal layer 212. As an example, the RF power may range from 500W to 1000W; for example, the RF power may be 500W, 600W, 700, 800, 900 or 1000W, etc.

In the method for preparing the semiconductor structure provided in the above embodiment, the radio frequency power for plasma nitriding treatment of the exposed surface of the metal layer 212 is in the range of 500W to 1000W, so that the surface of the metal layer 212 can be effectively passivated.

It can be understood that in the present disclosure, the RF power for plasma nitriding treatment of the exposed surface of the metal layer 212 can be adaptively selected according to actual needs, and the ability to passivate the exposed surface of the metal layer 212 can be enhanced by increasing the wattage of the RF power for plasma nitriding treatment of the exposed surface of the metal layer 212.

6 , as an example, a metal nitride layer 213 may be formed on the exposed surface of the metal layer 212 by plasma nitriding. It is understood that the metal element in the metal nitride layer 213 is the same as the metal element in the metal layer 212.

In some embodiments, after the exposed surface of the metal layer 212 is subjected to plasma nitriding treatment and before the first isolation layer 300 covering the conductive structure 210 and the substrate 100 is formed by the first process in step S300, the method for preparing the semiconductor structure may further include the following steps:

The metal layer 212 is cleaned to remove residual impurities on the surface of the metal layer 212 .

In the method for preparing the semiconductor structure provided in the above embodiment, by cleaning the metal layer 212 , it is possible to avoid metal impurities remaining on the surface of the metal layer 212 , thereby effectively avoiding or reducing the short circuit problem caused by metal residues on the surface of the metal layer 212 .

The present disclosure does not specifically limit the method for cleaning the metal layer 212 to remove the residual impurities on the surface of the metal layer 212. In some embodiments, the metal layer 212 may be cleaned with deionized water (DIW). Cleaning.

The present disclosure does not specifically limit the temperature of the deionized water in the step of using deionized water to clean the metal layer 212. As an example, the temperature of the deionized water may range from 60°C to 80°C; for example, the temperature of the deionized water may be 60°C, 65°C, 70°C, 75°C or 80°C, etc. That is, hot deionized water (HDIW for short) may be used to clean the metal layer 212.

The present disclosure does not specifically limit the cleaning time of deionized water in the step of using deionized water to clean the metal layer 212. As an example, the cleaning time of deionized water can range from 20s to 60s; for example, the cleaning time of deionized water can be 20s, 30s, 40s, 50s or 60s, etc.

It should be noted that in the preparation method provided in the present disclosure, the core and peripheral regions may include sub-word line drivers, sense amplifiers (SA) and connectors, etc. In the core and peripheral regions, multiple sub-word line drivers may be arranged along the word line direction in the storage cell array region.

It should be understood that, although the various steps in the flowchart of FIG. 1 are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in FIG. 1 may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

According to some embodiments, the present disclosure also provides a semiconductor structure. The semiconductor structure can be prepared by using the semiconductor structure preparation method provided in some embodiments above. The semiconductor structure can be arranged in, but not limited to, the core and peripheral regions.

5 , the semiconductor structure may include a substrate 100 , a plurality of conductive structures 210 , a first isolation layer 300 , and a second isolation layer 400 .

There is a groove 220 between adjacent conductive structures 210 ; the first isolation layer 300 conformally covers the conductive structure 210 and the groove 220 ; the second isolation layer 400 covers the first isolation layer 300 , and the density of the first isolation layer 300 is greater than that of the second isolation layer 400 .

In the semiconductor structure provided in the above embodiment, the first isolation layer 300 and the second isolation layer 400 covering the first isolation layer 300 are conformally covered on the conductive structure 210. The first isolation layer 300 and the second isolation layer 400 together provide insulation and protection for the conductive structure 210, which can effectively avoid or reduce the problem of short circuit between the conductive structures 210. In addition, the density of the first isolation layer 300 is greater than the density of the second isolation layer 400, that is, the first isolation layer 300 close to the conductive structure 210 has a greater density, so that the short circuit problem caused by the precipitation of metal on the surface of the conductive structure 210 or the metal residue on the surface of the conductive structure 210 can be effectively avoided or reduced.

Furthermore, the semiconductor structure provided in the above embodiment is suitable for forming a sub-word line driver for connecting to a word line in the core and peripheral regions of a memory device. In this case, the conductive structure 210 can be used as a metal line in the sub-word line driver. Usually, a sub-word line driver defines a plurality of conductive structures 210 in a very small space. In the semiconductor structure provided in the above embodiment, by providing a first isolation layer 300 and a second isolation layer 400 to insulate and protect the conductive structure 210, the short circuit problem between the plurality of conductive structures 210 in the sub-word line driver can be avoided or reduced, thereby facilitating the improvement of the production yield and the reliability of the semiconductor structure.

The semiconductor structure provided in the present disclosure does not specifically limit the material of the substrate 100. As an example, the substrate 100 may include but is not limited to a silicon substrate, a sapphire substrate, a glass substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, etc. or a combination thereof.

It can be understood that in the semiconductor structure provided by the present disclosure, the substrate 100 is not a blank substrate, that is, other electrical structures may be formed in or on the substrate 100, for example, a transistor array, a buried bit line, a buried word line or a contact structure may be formed in or on the substrate 100. For example, the specific structure of the substrate 100 can be found in the above content, which will not be repeated here.

The semiconductor structure provided in the present disclosure does not specifically limit the structure of the conductive structure 210. Please continue to refer to FIG5. In some embodiments, the conductive structure 210 may include a diffusion barrier layer 211 and a metal layer 212 covering the diffusion barrier layer 211.

The semiconductor structure provided in the above embodiment can prevent the metal material in the metal layer 212 from diffusing into the substrate 100 and causing contamination by providing the diffusion barrier layer 211, thereby preventing the performance of the electrical structure formed in or on the substrate 100 from being degraded or even failing.

The semiconductor structure provided by the present disclosure does not specifically limit the material of the diffusion barrier layer 211. It is understandable that the material of the diffusion barrier layer 211 only needs to consider its ability to block the diffusion of the metal layer 212 material, without considering its conductive properties. Therefore, the diffusion barrier layer 211 can be made of a conductive diffusion barrier material, or an insulating diffusion barrier material with better diffusion ability to block the metal layer 212; wherein the conductive diffusion barrier material may include but is not limited to titanium nitride, tungsten nitride, tantalum, tantalum nitride, ruthenium, etc. or a combination thereof; the insulating diffusion barrier material may include but is not limited to silicon nitride, silicon oxynitride, etc. or a combination thereof.

The semiconductor structure provided in the present disclosure does not specifically limit the material of the metal layer 212. As an example, the material of the metal layer 212 may include but is not limited to copper, gold, silver, tin, lead, tungsten, etc. or a combination thereof.

In some embodiments, please continue to refer to FIG. 5 , a contact hole (not shown in FIG. 5 ) may be provided in the substrate 100, for example, two contact holes located on opposite sides of the gate structure 110, for respectively exposing the source region 141 or the drain region 142. The conductive structure 210 may be provided in the contact hole to be connected to the source region 141 or the drain region 142.

For example, in the conductive structure 210, the diffusion barrier layer 211 may conformally cover the contact hole and cover the substrate 10. 0; the metal layer 212 may cover the diffusion barrier layer 211 and fill the contact hole.

In some embodiments, please continue to refer to FIG. 5 , the substrate 100 may further include an isolation spacer 150 located on two opposite sides of the gate structure 110 and between the gate structure 110 and the conductive structure 210 .

The semiconductor structure provided by the present disclosure does not specifically limit the thickness of the first isolation layer 300 and the second isolation layer 400. In some embodiments, the thickness of the second isolation layer 400 is greater than the thickness of the first isolation layer 300.

As an example, the thickness of the first isolation layer 300 may range from 3 nm to 5 nm; for example, the thickness of the first isolation layer 300 may be 3 nm, 3.5 nm, 4 nm, 4.5 nm or 5 nm, etc. As an example, the thickness of the second isolation layer 400 may range from 30 nm to 50 nm; for example, the thickness of the second isolation layer 400 may be 30 nm, 35 nm, 40 nm, 45 nm or 50 nm, etc.

The semiconductor structure provided in the present disclosure does not specifically limit the materials of the first isolation layer 300 and the second isolation layer 400. In some embodiments, the material of the first isolation layer 300 and the material of the second isolation layer 400 both include nitride.

As an example, the second isolation layer 400 may include silicon chloride.

Please continue to refer to FIG. 6 . In some embodiments, the semiconductor structure may further include a metal nitride layer 213 disposed on the exposed surface of the metal layer 212 .

In the semiconductor structure provided by the above embodiment, since the exposed surface of the metal layer 212 has the metal nitride layer 213 , the exposed surface of the metal layer 212 can be protected.

It should be noted that, in the semiconductor structure provided by the present disclosure, the metal nitride layer 213 can be obtained by performing plasma nitriding treatment on the exposed surface of the metal layer 212 .

The semiconductor structure provided in the present disclosure does not specifically limit the material of the metal nitride layer 213. In some embodiments, the metal element in the metal nitride layer 213 is the same as the metal element in the metal layer 212. For example, when the material of the metal line 212 includes tungsten, the material of the metal nitride layer 213 may include tungsten nitride.

It should be noted that in the semiconductor structure provided by the present disclosure, the core and peripheral regions may include sub-wordline drivers, sense amplifiers, connectors, etc. In the core and peripheral regions, multiple sub-wordline drivers may be arranged along the wordline direction in the memory cell array region.

It should be noted that the preparation methods of the semiconductor structures in the present disclosure can all be used to prepare corresponding semiconductor structures. Therefore, the technical features between the method embodiments and the structural embodiments can be replaced and supplemented with each other without causing conflicts, so that those skilled in the art can understand the technical content of the present disclosure.

According to some embodiments, the present disclosure also provides a memory, which may include the semiconductor structure in any of the above embodiments. For example, the memory may be, but is not limited to, a dynamic random access memory (DRAM), a static random access memory (SRAM), etc.

The technical features of the above-mentioned embodiments can be combined arbitrarily. All possible combinations of the various technical features are described; however, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

The above-described embodiments only express several implementation methods of the embodiments of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the embodiments of the present disclosure, and these all belong to the protection scope of the embodiments of the present disclosure. Therefore, the protection scope of the patent of the embodiments of the present disclosure shall be subject to the attached claims.

Claims (20)

1. A method for preparing a semiconductor structure, comprising:

   Providing a substrate, and forming a conductive material layer on the substrate;

   Patterning the conductive material layer to form a plurality of conductive structures and grooves between adjacent conductive structures;

   Using a first process to form a first isolation layer that conformally covers the conductive structure and the groove;

   forming a second isolation layer covering the first isolation layer by a second process;

   Wherein, the density of the first isolation layer is greater than the density of the second isolation layer.
2. The method for preparing a semiconductor structure according to claim 1, wherein a thickness of the second isolation layer is greater than a thickness of the first isolation layer.
3. The method for preparing a semiconductor structure according to claim 1 or 2, wherein:

   The first process includes an atomic layer deposition process;

   The second process includes a low pressure chemical vapor deposition process.
4. The method for preparing a semiconductor structure according to claim 3, wherein a process temperature of the first process is lower than a process temperature of the second process.
5. The method for preparing a semiconductor structure according to claim 4, wherein:

   The process temperature of the first process ranges from 480°C to 580°C;

   The process temperature of the second process ranges from 600°C to 780°C.
6. The method for preparing a semiconductor structure according to any one of claims 1 to 5, wherein:

   The thickness of the first isolation layer ranges from 3 nm to 5 nm;

   The thickness of the second isolation layer ranges from 30 nm to 50 nm.
7. The method for preparing a semiconductor structure according to claim 6, wherein the material of the first isolation layer and the material of the second isolation layer both include nitride.
8. The method for preparing a semiconductor structure according to any one of claims 1 to 7, wherein the conductive structure comprises a diffusion barrier layer and a metal layer located on the diffusion barrier layer.
9. The method for preparing a semiconductor structure according to claim 8, wherein a contact hole is formed in the substrate;

   The diffusion barrier layer conformally covers the contact hole and covers a portion of the top surface of the substrate;

   The metal layer covers the diffusion barrier layer and fills the contact hole.
10. The method for preparing a semiconductor structure according to claim 8, wherein before forming a first isolation layer covering the conductive structure and the substrate by using a first process, the method further comprises:

    The exposed surface of the metal layer is subjected to plasma nitriding treatment.
11. The method for preparing a semiconductor structure according to claim 10, wherein the radio frequency power of the plasma nitriding treatment ranges from 500W to 1000W.
12. The method for preparing a semiconductor structure according to claim 10, wherein after the exposed surface of the metal layer is subjected to plasma nitriding treatment and before the first isolation layer covering the conductive structure and the substrate is formed by the first process, the method further comprises:

    The metal layer is cleaned to remove residual impurities on the surface of the metal layer.
13. The method for preparing a semiconductor structure according to claim 12, wherein the metal layer is cleaned with deionized water;

    The temperature of the deionized water ranges from 60° C. to 80° C., and the cleaning time of the deionized water ranges from 20s to 60s.
14. A semiconductor structure comprising:

    substrate;

    A plurality of conductive structures; grooves are provided between adjacent conductive structures;

    A first isolation layer, conformally covering the conductive structure and the groove;

    a second isolation layer, covering the first isolation layer;

    Wherein, the density of the first isolation layer is greater than the density of the second isolation layer.
15. The semiconductor structure according to claim 14, wherein the thickness of the second isolation layer is greater than the thickness of the first isolation layer.
16. The semiconductor structure according to claim 14 or 15, wherein:

    The thickness of the first isolation layer ranges from 3 nm to 5 nm;

    The thickness of the second isolation layer ranges from 30 nm to 50 nm.
17. The semiconductor structure according to any one of claims 14 to 16, wherein the conductive structure comprises a diffusion barrier layer and a metal layer located on the diffusion barrier layer.
18. The semiconductor structure according to claim 17, wherein a contact hole is provided in the substrate;

    The diffusion barrier layer conformally covers the contact hole and covers a portion of the top surface of the substrate;

    The metal layer covers the diffusion barrier layer and fills the contact hole.
19. The semiconductor structure according to claim 18, wherein a metal nitride layer is provided on the exposed surface of the metal layer; and the metal element in the metal nitride layer is the same as the metal element in the metal layer.
20. A memory comprising the semiconductor structure according to any one of claims 14 to 19.