CN110752213A - Method for manufacturing semiconductor structure - Google Patents
Method for manufacturing semiconductor structure Download PDFInfo
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- CN110752213A CN110752213A CN201911025745.2A CN201911025745A CN110752213A CN 110752213 A CN110752213 A CN 110752213A CN 201911025745 A CN201911025745 A CN 201911025745A CN 110752213 A CN110752213 A CN 110752213A
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- silicon oxide
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
Abstract
The invention provides a manufacturing method of a semiconductor structure, which comprises the following steps: providing a semiconductor substrate, and forming more than two spaced gate structures on the semiconductor substrate; forming a first silicon oxide layer covering the side wall and the bottom of the groove between the adjacent gate structures; performing a metal silicidation process on the control gate; performing a thinning process on the first silicon oxide layer; and forming a second silicon oxide layer which seals the groove and forms an air gap. Compared with the prior art, the first silicon oxide layer formed in the groove is thinned before the groove is sealed by the second silicon oxide layer to form the air gap, so that the finally formed air gap can be increased in width and height, and the standard can be met.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor structure.
Background
As the physical size of NAND flash memory cells shrinks, the crosstalk between two adjacent flash memory cells becomes more severe. In order to solve the problem, preparing air gaps (air gaps) between the memory cells is an effective method for reducing crosstalk, and the air gaps are adopted in the current mainstream NAND flash memory chips.
After the final etching of the control gate polysilicon layer of the flash memory cell is completed, a layer of silicon oxide needs to be grown on the side wall of the gate to protect the floating gate at the bottom, so that the floating gate is prevented from being consumed by silicidation in the subsequent metal silicification process. Generally, a Self-aligned Double imaging process (SADP) is used for a control gate process, a formed control gate polysilicon layer inevitably has an odd-even effect, and the width of a trench between control gates has an odd-even difference, which results in that the distance between two side walls is smaller after depositing silicon oxide, and even the side walls are connected together at the bottom of the trench to fill the bottom of the trench, so that an air gap formed subsequently cannot meet the standard in width and height.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor structure, which aims to solve the problem that an air gap of a grid structure cannot meet the standard in width and height.
To solve the above technical problem, the present invention provides a method for fabricating a semiconductor structure, comprising:
providing a semiconductor substrate, and forming more than two spaced grid structures on the semiconductor substrate, wherein each grid structure comprises a floating grid, a dielectric layer and a control grid which are sequentially stacked from bottom to top;
forming a first silicon oxide layer covering the side wall and the bottom of the groove between the adjacent gate structures;
performing a metal silicidation process on the control gate;
performing a thinning process on the first silicon oxide layer;
and forming a second silicon oxide layer which seals the groove and forms an air gap.
Optionally, the method for manufacturing the semiconductor structure is characterized in that the thinning process is a SiCoNi etching process.
Optionally, in theThe method for manufacturing the semiconductor structure is characterized in that the thickness of the first silicon oxide layer thinned by the thinning process is
Optionally, the method for manufacturing the semiconductor structure is characterized in that the pressure of the SiCoNi etching process is 3 Torr-10 Torr, the etching temperature is 25 ℃ to 50 ℃, the plasma power is 20W-40W, and NF3The flow rate is 4 sccm-10 sccm, NH3The flow rate is 60 sccm-120 sccm, the He flow rate is 200 sccm-300 sccm, and the sublimation temperature is more than 100 ℃.
Optionally, before performing a metal silicidation process on the control gate, the method for manufacturing the semiconductor structure further includes:
and removing the first silicon oxide layer at the top of the trench to expose partial side walls of the control gate.
Optionally, before removing the first silicon oxide layer on the top of the trench, the method for manufacturing a semiconductor structure further includes:
forming a silicon nitride layer, wherein the silicon nitride layer covers the first silicon oxide layer and fills the groove;
forming a peripheral device in a peripheral area of the gate structure; and removing the silicon nitride layer.
Optionally, in the method for manufacturing a semiconductor structure, the first silicon oxide has a thickness of
Optionally, in the manufacturing method of the semiconductor structure, the first silicon oxide layer is formed by using an atomic deposition process.
Optionally, in the manufacturing method of the semiconductor structure, a metal silicidation process is performed on the control gate by using Ni.
Optionally, in the manufacturing method of the semiconductor structure, the floating gate and the control gate are made of polysilicon, and the dielectric layer is an ONO layer.
The manufacturing method of the semiconductor structure provided by the invention comprises the following steps: providing a semiconductor substrate, and forming more than two spaced gate structures on the semiconductor substrate; forming a first silicon oxide layer covering the side wall and the bottom of the groove between the adjacent gate structures; performing a metal silicidation process on the control gate; performing a thinning process on the first silicon oxide layer; and forming a second silicon oxide layer which seals the groove and forms an air gap. Compared with the prior art, the first silicon oxide layer formed in the groove is thinned before the groove is sealed by the second silicon oxide layer to form the air gap, so that the finally formed air gap can be increased in width and height, and the standard can be met.
Drawings
Fig. 1 is a flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention;
fig. 2 to 8 are schematic device structures corresponding to steps of a method for manufacturing a semiconductor structure according to an embodiment of the present invention;
wherein the reference numerals are as follows:
11-a semiconductor substrate; 12-a gate structure; 121-floating gate; 122-a dielectric layer; 123-control gate; 13-a first silicon oxide layer; 101-a trench; 14-a silicon nitride layer; 15-second silicon dioxide layer.
Detailed Description
The method for fabricating the semiconductor structure according to the present invention is further described in detail with reference to the drawings and the embodiments. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
Referring to fig. 1, an embodiment of the invention provides a method for fabricating a semiconductor structure, including the following steps:
s11, providing a semiconductor substrate, and forming more than two spaced gate structures on the semiconductor substrate;
s12, forming a first silicon oxide layer, wherein the first silicon oxide layer covers the side wall and the bottom of the groove between the adjacent gate structures;
s13, performing a metal silicification process on the control gate;
s14, thinning the first silicon oxide layer;
and S15, forming a second silicon oxide layer which seals the groove and forms an air gap.
Compared with the prior art, the first silicon oxide layer formed in the groove is thinned before the groove is sealed by the second silicon oxide layer to form the air gap, so that the finally formed air gap can be increased in width and height, and the standard can be met.
The method for fabricating the semiconductor structure according to the embodiment of the invention is further described with reference to fig. 2 to 7.
First, referring to fig. 2, step S11 is performed to provide a semiconductor substrate 11, and two or more spaced gate structures 12 are formed on the semiconductor substrate 11.
Shallow trench isolation (not shown) may be disposed in the semiconductor substrate 11, the material of the semiconductor substrate 11 may be single crystal silicon, polysilicon, amorphous silicon, silicon germanium compound, silicon-on-insulator (SOI), or the like, or other materials known to those skilled in the art, and doped regions and the like may also be formed in the semiconductor substrate 11.
The gate structure 12 includes a floating gate 121, a dielectric layer 122 and a control gate 123 stacked in sequence from bottom to top, wherein the floating gate 121 and the control gate 123 are preferably made of polysilicon, and the dielectric layer is preferably an ONO (silicon oxide-silicon nitride-silicon oxide) layer. Generally, the gate structure 12 may be formed by sequentially forming a floating gate layer, a dielectric material layer and a control gate layer on the semiconductor substrate 11, and then etching the floating gate layer, the dielectric material layer and the control gate layer, which is well known to those skilled in the art and therefore will not be described herein again.
Next, referring to fig. 3, step S12 is executed to form a first silicon oxide layer 13, where the first silicon oxide layer 13 covers sidewalls and a bottom of the trench 101 between the adjacent gate structures 12, the first silicon oxide layer 13 is used to protect the floating gate 121 at the bottom from being consumed by silicidation in the subsequent metal silicidation process, and only when the first silicon oxide layer 13 reaches a certain thickness, the first silicon oxide layer 13 can play a role in preventing the floating gate 121 from being consumed by silicidation in the subsequent metal silicidation process, and meanwhile, considering that the thickness of the first silicon oxide layer 13 also affects the morphology of the air gap, therefore, in this embodiment, the thickness of the first silicon oxide layer 13 is preferably equal to
For example, can beAnd the like, using an atomic deposition process.
In this embodiment, only the first silicon oxide layer 13 is illustrated to cover the sidewalls and the bottom of the trench 101 for convenience, but it is understood that the first silicon oxide layer 13 may also extend to the top surface of the control gate 123.
Preferably, referring to fig. 5, after step S12 is completed, the method for manufacturing a semiconductor structure of the present embodiment further includes: the first silicon oxide layer 13 on the top of the trench 101 is removed to expose a portion of the sidewalls of the control gate 123. Specifically, the first silicon oxide layer 13 on the top of the trench 101 may be removed by dry etching, where the gas of the dry etching is HCl. This step provides for the subsequent metal processing to be performed, increasing the contact area during the processing.
Next, referring to fig. 6, step S13 is executed to perform a metal silicidation process on the control gate 123. For example, a metal silicidation process may be performed on the control gate 123 using Ni.
In addition, for the NAND flash memory device, when the gate structure 12 is formed on the semiconductor substrate 11, a peripheral device (not shown) is further formed in a peripheral area of the gate structure 12, wherein the peripheral device may include a logic gate and the like, and the logic gate may be formed by forming a logic gate dielectric layer and then etching the logic gate dielectric layer. Therefore, referring to fig. 4, before removing the first silicon oxide layer 13 on the top of the trench 101, the method for manufacturing the semiconductor structure of the present embodiment preferably further includes: forming a silicon nitride layer 14, wherein the silicon nitride layer 14 covers the first silicon oxide layer 13 and fills the trench; forming a peripheral device in a peripheral region of the gate structure 12; and removing the silicon nitride layer 14. The silicon nitride layer 14 is formed to protect the gate structure 12 during peripheral device processing and also to provide an air gap region after subsequent removal.
After performing the metal silicidation process on the control gate 123, referring to fig. 7, a step S14 is performed to thin the first silicon oxide layer 13. In this embodiment, preferably, the thinning process is a SiCoNi etching process, and the SiCoNi etching process includes the following steps:
remote plasma (Remote plasma) gas generation, NF3+NH3→NH4F+NH4F·HF；
Etching, NH4F or NH4F·HF+SiO2→(NH4)2SiF6+H2O；
Sublimation, (NH)4)2SiF6→SiF4+NH3+HF；
More preferably, the pressure of the SiCoNi etching process is 3 Torr-10 Torr, the etching temperature is 25 ℃ -50 ℃, the plasma power is 20W-40W, and NF3The flow rate is 4 sccm-10 sccm, NH3The flow rate is 60 sccm-120 sccm, the He flow rate is 200 sccm-300 sccm, the sublimation temperature is more than 100 ℃, and the process condition is adopted, so that the thinned first silicon oxide layer 13 can be obtainedHas a thickness of
The control gate can also be protected from being consumed during the etching process. .
The biggest characteristic of the SiCoNi etching process is that SiO2The etching selectivity of/Si is very high (>20: 1) therefore, the silicon oxide on the bottom and the side wall of the trench 101 is thinned, the size of an air gap is increased in width and height, and plasma damage and polycrystalline silicon consumption to a device can be avoided.
Finally, referring to fig. 8, step S15 is performed to form a second silicon oxide layer 15, where the second silicon oxide layer 15 seals the trench 101 and forms an air gap. In this step, the process of sealing the trench 101 and forming an air gap by using the second silicon oxide layer 15 is well known to those skilled in the art, and therefore, will not be described herein again.
In summary, the manufacturing method of the semiconductor structure provided by the invention solves the problem that the air gap of the gate structure cannot meet the standard in terms of width and height.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method for fabricating a semiconductor structure, comprising:
providing a semiconductor substrate, and forming more than two spaced grid structures on the semiconductor substrate, wherein each grid structure comprises a floating grid, a dielectric layer and a control grid which are sequentially stacked from bottom to top;
forming a first silicon oxide layer covering the side wall and the bottom of the groove between the adjacent gate structures;
performing a metal silicidation process on the control gate;
performing a thinning process on the first silicon oxide layer;
and forming a second silicon oxide layer which seals the groove and forms an air gap.
2. The method of claim 1, wherein the thinning process is a SiCoNi etching process.
3. The method of manufacturing a semiconductor structure according to claim 1 or 2, wherein the thickness of the first silicon oxide layer thinned by the thinning process is set to be
4. The method of claim 2, wherein the SiCoNi etching process is performed at a pressure of 3Torr to 10Torr, an etching temperature of 25 ℃ to 50 ℃, a plasma power of 20W to 40W, and NF3The flow rate is 4 sccm-10 sccm, NH3The flow rate is 60 sccm-120 sccm, the He flow rate is 200 sccm-300 sccm, and the sublimation temperature is more than 100 ℃.
5. The method of fabricating a semiconductor structure according to claim 1, wherein before performing a metal silicidation process on the control gate, the method further comprises:
and removing the first silicon oxide layer at the top of the trench to expose partial side walls of the control gate.
6. The method of fabricating a semiconductor structure according to claim 5, wherein before removing the first silicon oxide layer at the top of the trench, the method further comprises:
forming a silicon nitride layer, wherein the silicon nitride layer covers the first silicon oxide layer and fills the groove;
forming a peripheral device in a peripheral area of the gate structure; and
and removing the silicon nitride layer.
7. The method of claim 1, wherein the first silicon oxide has a thickness of
8. The method of claim 1, wherein the first silicon oxide layer is formed using an atomic deposition process.
9. The method of claim 1, wherein a metal silicidation process is performed on the control gate using Ni.
10. The method of claim 1, wherein the floating gate and the control gate are made of polysilicon and the dielectric layer is an ONO layer.
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| CN201911025745.2A CN110752213A (en) | 2019-10-25 | 2019-10-25 | Method for manufacturing semiconductor structure |
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| CN201911025745.2A CN110752213A (en) | 2019-10-25 | 2019-10-25 | Method for manufacturing semiconductor structure |
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| CN111653571A (en) * | 2020-07-23 | 2020-09-11 | 上海华力微电子有限公司 | Method for forming semiconductor structure |
| CN115881621A (en) * | 2023-01-10 | 2023-03-31 | 广州粤芯半导体技术有限公司 | Shallow trench isolation structure and preparation method thereof, semiconductor structure and chip |
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