CN115881621A - Shallow trench isolation structure and preparation method thereof, semiconductor structure and chip - Google Patents
Shallow trench isolation structure and preparation method thereof, semiconductor structure and chip Download PDFInfo
- Publication number
- CN115881621A CN115881621A CN202310032176.4A CN202310032176A CN115881621A CN 115881621 A CN115881621 A CN 115881621A CN 202310032176 A CN202310032176 A CN 202310032176A CN 115881621 A CN115881621 A CN 115881621A
- Authority
- CN
- China
- Prior art keywords
- oxide layer
- protective layer
- silicon wafer
- shallow trench
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 56
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 239000010410 layer Substances 0.000 claims abstract description 161
- 239000011241 protective layer Substances 0.000 claims abstract description 75
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 73
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 73
- 239000010703 silicon Substances 0.000 claims abstract description 73
- 238000000034 method Methods 0.000 claims abstract description 61
- 230000008569 process Effects 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 24
- LXPCOISGJFXEJE-UHFFFAOYSA-N oxifentorex Chemical compound C=1C=CC=CC=1C[N+](C)([O-])C(C)CC1=CC=CC=C1 LXPCOISGJFXEJE-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 8
- 238000006243 chemical reaction Methods 0.000 claims description 57
- 238000007254 oxidation reaction Methods 0.000 claims description 42
- 230000003647 oxidation Effects 0.000 claims description 29
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 21
- 239000001301 oxygen Substances 0.000 claims description 21
- 229910052760 oxygen Inorganic materials 0.000 claims description 21
- 238000010438 heat treatment Methods 0.000 claims description 19
- 239000007789 gas Substances 0.000 claims description 10
- 230000005284 excitation Effects 0.000 claims description 4
- 230000000630 rising effect Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 238000011049 filling Methods 0.000 description 14
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- 238000000151 deposition Methods 0.000 description 7
- 229910017855 NH 4 F Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000859 sublimation Methods 0.000 description 4
- 230000008022 sublimation Effects 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 239000006227 byproduct Substances 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- VUZPPFZMUPKLLV-UHFFFAOYSA-N methane;hydrate Chemical compound C.O VUZPPFZMUPKLLV-UHFFFAOYSA-N 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000001172 regenerating effect Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
Landscapes
- Element Separation (AREA)
Abstract
The application relates to the technical field of semiconductors, in particular to a shallow trench isolation structure and a preparation method thereof, a semiconductor structure and a chip, and aims to solve the problems that in the related technology, a natural oxide layer cannot be completely removed, so that the growth of a subsequent linear oxide layer is not facilitated, and the isolation of an active region by the shallow trench isolation structure is not facilitated. A method for preparing a shallow trench isolation structure comprises the following steps: forming a shallow trench structure on a silicon chip, wherein a natural oxide layer is formed on the surface of the shallow trench structure; removing the natural oxide layer by adopting a SiCoNi etching process, and forming a protective layer on the surface of the silicon wafer with the natural oxide layer removed, wherein the protective layer comprises the following materials: ammonium hexafluorosilicate; and removing the protective layer, and forming a linear oxide layer on the surface of the silicon wafer with the protective layer removed.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a shallow trench isolation structure, a preparation method thereof, a semiconductor structure and a chip.
Background
Shallow Trench Isolation (STI) is a process for forming Isolation regions between active regions of transistors on a substrate, which can effectively ensure that n-type and p-type doped regions are completely separated. Specifically, the shallow trench isolation technique is to etch away Si in n-type and p-type doped regions to form a shallow trench, and then fill the shallow trench with an insulating material to achieve the purpose of isolation. Compared with the traditional intrinsic oxidation isolation technology, the shallow trench isolation technology can reduce the leakage current between electrodes and bear larger breakdown voltage.
In the isolation process of STI, the isolation process is realized by a silicon oxide dielectric layer filled between active regions. Therefore, the filling of the silicon oxide dielectric layer is a key process for the STI isolation. Before filling the shallow trench by depositing silicon oxide using HDPCVD (High Density Plasma Chemical Vapor Deposition) or HARP (High aspect ratio process), a thin oxide film (e.g., linear oxide layer) is grown on the surface of the etched shallow trench by thermal oxidation. The main function is to increase the adhesion of HDPCVD or HARP deposited silicon oxide to the shallow trench interface. Because the shallow trench has extremely small width and deep depth, the conventional dielectric film growth method is difficult to fill, namely, a filling cavity is easy to form. The excellent filling capacity of HDPCVD or HARP just meets the requirements of STI on shallow trench filling.
In addition, the thin oxide film grown on the surface of the etched shallow trench by utilizing thermal oxidation can be used for repairing the damage of the side wall formed in the etching process and improving the insulation effect of the subsequent shallow trench deposition film, meanwhile, the sharp corner is repaired before HDPCVD or HARP deposition, the STI contact surface can be reduced, the HDPCVD or HARP filling silicon oxide is excited by using plasma, and the linear oxide layer can also be used as a buffer layer in the deposition process, so that the growth process and the film forming quality of the linear oxide layer directly influence the insulation performance of the linear oxide layer and the filling effect of the subsequent HDPCVD or HARP deposition silicon oxide.
Currently, in the related art, before the linear oxide layer grows, the wafer is cleaned to remove the natural oxide layer generated during the atmospheric contact process of the wafer or the oxide layer remained in the front end process, because the poor film quality of the natural oxide layer affects the insulation and isolation effect of the STI and the quality of the subsequent linear oxide layer. At present, the natural oxide layer is mainly removed by a wet etching process, namely the natural oxide layer on the surface of the shallow trench is removed by using buffered hydrofluoric acid formed by mixing hydrofluoric acid and ammonium fluoride, but the natural oxide layer etched by the wet etching process has at least the following defects: firstly, in the waiting time from the end of wet etching to the growth of the linear oxide layer by using the furnace tube, the natural oxide layer still grows, and the complete removal of the natural oxide layer cannot be ensured. The second wet etching is isotropic etching, which aggravates the damage of the side wall of the shallow trench during the etching process and causes the problem of uneven growth of the linear oxide layer, and meanwhile, the subsequent HDPCVD or HARP process has the unevenness of selectively growing the linear oxide layer, which also affects the filling effect of the HDPCVD or HARP, and is not beneficial to the isolation of the shallow trench isolation structure to the active region.
Disclosure of Invention
Therefore, the application provides a shallow trench isolation structure and a preparation method thereof, a semiconductor structure and a chip, which are used for solving the problems that in the related technology, a natural oxide layer cannot be completely removed, so that the subsequent growth of a linear oxide layer is not facilitated, and the isolation of an active region by the shallow trench isolation structure is not facilitated.
In a first aspect, a method for manufacturing a shallow trench isolation structure is provided, including:
forming a shallow trench structure on a silicon chip, wherein a natural oxide layer is formed on the surface of the shallow trench structure;
removing the natural oxide layer by adopting a SiCoNi etching process, and forming a protective layer on the surface of the silicon wafer with the natural oxide layer removed, wherein the protective layer is made of the following materials: ammonium hexafluorosilicate;
and removing the protective layer, and forming a linear oxide layer on the surface of the silicon wafer from which the protective layer is removed.
Optionally, a SiCoNi etching process is used to remove the natural oxide layer, and a protective layer is formed on the surface of the silicon wafer from which the natural oxide layer is removed, including:
placing the silicon wafer with the natural oxide layer in a first reaction cavity;
NH is introduced into the first reaction chamber 3 、NF 3 And a plasma gas source;
by reaction of NH 3 And NF 3 Under the excitation of plasma, the plasma reacts with the natural oxide layer to convert the natural oxide layer into a protective layer.
Optionally, NH 3 The flow rate of the flow is 70 to 100sccm 3 The flow rate of the gas is 14 to 30sccm.
Optionally, the removing of the protective layer and the forming of the linear oxide layer on the surface of the silicon wafer from which the protective layer is removed occur in the same reaction chamber.
Optionally, removing the protective layer includes:
placing the silicon wafer with the protective layer in a second reaction cavity;
vacuumizing the second reaction cavity until the vacuum degree in the second reaction cavity is 6.8to 7.2Torr;
and heating the second reaction cavity to sublimate and remove the surface of the protective layer silicon wafer.
Optionally, the heating temperature is 180 to 190 ℃, and the heating time is 15 to 30s.
Optionally, forming a linear oxide layer on the surface of the silicon wafer with the protective layer removed includes:
and after the protective layer is removed, directly forming a linear oxide layer on the surface of the silicon wafer with the protective layer removed in a second reaction cavity by a thermal oxidation method.
Optionally, the temperature of the thermal oxidation method is 900 to 1100 ℃, and the flow of the introduced oxygen gas source is 20 to 30SLM.
Optionally, directly forming a linear oxide layer on the surface of the silicon wafer with the protective layer removed by a thermal oxidation method in the second reaction chamber, where the linear oxide layer includes:
raising the temperature of the second reaction chamber from the heating temperature to the temperature of the thermal oxidation reaction;
and introducing oxygen into the second reaction cavity, so that the oxygen and the surface of the silicon wafer with the protective layer removed undergo a thermal oxidation reaction to generate a linear oxide layer.
Optionally, the temperature rising speed is 75 to 125 ℃/s, and the time is 10 to 12s.
In a second aspect, a shallow trench isolation structure is provided, which is obtained by the method according to the first aspect.
In a third aspect, a semiconductor structure is provided, comprising:
the shallow trench isolation structure of the second aspect.
In a fourth aspect, a chip is provided, which includes:
the semiconductor structure of the third aspect.
Compared with the prior art, this application has following beneficial effect:
by adopting a SiCoNi etching process, a natural oxide layer on the surface of the shallow trench structure can be removed, and a protective layer is generated, wherein the protective layer is made of the following materials: the ammonium hexafluorosilicate can directly form the linear oxide layer on the surface of the shallow trench structure by only removing the protective layer under the condition of isolating air or oxygen before forming the linear oxide layer on the surface of the silicon wafer, thereby reducing the residue of the natural oxide layer as much as possible. Therefore, on one hand, the silicon on the surface of the shallow trench structure can directly generate the linear oxide layer, so that the side wall damage caused by STI etching can be conveniently repaired, and the film quality of the linear oxide layer is ensured. On the other hand, the linear oxide layer has higher compactness and film forming quality, and can ensure good insulating property and subsequent filling effect of HDPCVD or HARP deposited silicon oxide, thereby improving the isolation effect of the shallow trench isolation structure on the active region.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a shallow trench isolation structure according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram illustrating a process for removing native oxide and forming a passivation layer on a silicon wafer according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of the temperature change in the second reaction chamber with time according to the embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to specific examples. This application may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Based on the above technical problem, some embodiments of the present application provide a method for manufacturing a shallow trench isolation structure, as shown in fig. 1, including:
s1), forming a shallow trench structure 2 on a silicon wafer 1, wherein a natural oxide layer 20 is formed on the surface of the shallow trench structure 2;
s2), removing the natural oxide layer 20 by adopting a SiCoNi etching process, and forming a protective layer 30 on the surface of the silicon wafer 1 with the natural oxide layer 20 removed, wherein the protective layer 30 comprises the following materials: ammonium hexafluorosilicate;
s3), removing the protective layer 30, and forming a linear oxide layer 3 on the surface of the silicon wafer with the protective layer 30 removed.
The silicon wafer 1 may be a wafer.
The shallow trench structure 2 may be formed by STI etching, and after the STI etching is completed, the natural oxide layer 20 may be formed on the surface of the shallow trench structure 2 by the wafer contacting with the atmosphere.
The thickness of the natural oxide layer 20 may be 30 to 60 angstroms.
The SiCoNi etch is a highly selective preclean that acts to remove the native oxide layer 20 from the surface of the silicon wafer 1. Specifically, NF is formed after the silicon chip 1 enters the reaction chamber 3 And NH 3 The mixed gas generates active particles under the excitation action of plasma, and the active particles enter a reaction cavity to react with a natural oxide layer (silicon oxide) on the surface of the silicon wafer 1 to generate a sublimable compound hexafluorosilicic acidAmmonia ((NH) 4 ） 2 SiF 6 ) Thereby removing the silicon oxide on the surface of the silicon wafer 1.
The linear oxide layer 3 may be formed by reaction in a thermal oxidation furnace tube.
In the method for manufacturing the shallow trench isolation structure provided in the embodiment of the present application, the SiCoNi etching process is used to remove the natural oxide layer 20 on the surface of the shallow trench isolation structure 2, and generate the protection layer 30, where the protection layer 30 is made of a material including: ammonium hexafluorosilicate is used, and before the linear oxide layer 3 is formed on the surface of the silicon wafer 1, the protective layer 30 is only required to be removed under the condition of isolating air or oxygen, so that the linear oxide layer 3 can be directly formed on the surface of the shallow trench structure 2, and the residue of the natural oxide layer 20 is reduced as much as possible. Therefore, on the one hand, silicon on the surface of the shallow trench structure 2 can directly generate the linear oxide layer 3, so that the side wall damage caused by STI etching is convenient to repair, and the film quality of the linear oxide layer 3 is ensured. On the other hand, the linear oxide layer 3 has higher compactness and film forming quality, and can ensure good insulating property and subsequent filling effect of HDPCVD or HARP deposited silicon oxide, thereby improving the isolation effect of the shallow trench isolation structure on the active region.
In some embodiments, S2), removing the native oxide layer 20 by using a SiCoNi etching process, and forming a protective layer 30 on the surface of the silicon wafer 1 from which the native oxide layer 20 is removed, as shown in fig. 2, including:
s21), placing the silicon wafer 1 with the natural oxide layer 20 in the first reaction cavity 100;
s22), introducing NH into the first reaction chamber 100 3 、NF 3 And a plasma gas source;
s23) reacting NH 3 And NF 3 Under the excitation of the plasma, the plasma reacts with the native oxide layer 20 to convert the native oxide layer 20 into the protective layer 30.
In these examples, NH 3 、NF 3 And the native oxide layer 20, as follows: NF 3 +NH 3 →NH 4 F/NH 4 HF and NH 4 F/NH 4 F.HF+SiO 2 →(NH 4 ) 2 SiF 6 (s)+H 2 O, thereby converting the native oxide layer 20 into the protective layer 30.
In some embodiments, the NH as described above 3 The flow rate of the flow is 70 to 100sccm 3 The flow rate of the flow rate is 14 to 30sccm.
In these examples, by reacting NH 3 、NF 3 The removal of the native oxide layer 20 can be completed as much as possible by controlling the amount within the above range.
In some embodiments, the plasma gas source may be argon.
In some embodiments, the removal of the protective layer 30 and the formation of the linear oxide layer 3 on the surface of the silicon wafer 1 from which the protective layer 30 is removed occur in the same reaction chamber.
In these embodiments, the surface of the silicon wafer 1 from which the protective layer 30 is removed is prevented from being exposed to the atmosphere to regenerate the native oxide layer 20.
In some embodiments, removing the protective layer 30 includes:
placing the silicon wafer 1 with the protective layer 30 in a second reaction chamber;
vacuumizing the second reaction cavity until the vacuum degree in the second reaction cavity is 6.8to 7.2Torr
And heating the second reaction chamber to remove the protective layer 30 from the surface of the silicon wafer 1 by sublimation.
In these embodiments, the protective layer 30 is removed from the surface of the silicon wafer 1 by sublimation in a vacuum chamber, thereby preventing the surface of the silicon wafer 1 from which the protective layer 30 has been removed from contacting with oxygen in the air and regenerating the native oxide layer 20. The reaction equation for sublimation of the protective layer 30 is as follows: (NH) 4 ) 2 SiF 6 (s)→SiF 4 (g)+NH 3 (g)+HF(g)。
In some embodiments, the heating temperature is 180 to 190 ℃ and the time is 15 to 30s.
In these embodiments, by controlling the heating temperature and time within the above-described ranges, the protective layer 30 can be completely removed by sublimation.
In some embodiments, forming a linear oxide layer 3 on the surface of the silicon wafer 1 from which the protective layer 30 is removed includes:
after the protective layer 30 is removed, a linear oxide layer 3 is formed on the surface of the silicon wafer 1 from which the protective layer 30 is removed by a thermal oxidation method directly in the second reaction chamber.
In the embodiments, the linear oxide layer 3 is formed on the surface of the silicon wafer 1 with the protective layer 30 removed by the thermal oxidation method directly in the second reaction chamber, and the silicon wafer 1 with the protective layer 30 removed does not need to be taken out of the second reaction chamber, so that the surface of the silicon wafer 1 with the protective layer 30 removed can be further prevented from contacting with oxygen in the air to regenerate the natural oxide layer 20.
The second reaction cavity can be a reaction cavity of a thermal oxidation furnace tube. Before the linear oxide layer 3 is formed on the surface of the silicon wafer 1 from which the protective layer 30 needs to be removed, the silicon wafer 1 on which the protective layer 30 is formed can be directly transferred into a reaction chamber of a thermal oxidation furnace tube, then the silicon wafer is vacuumized, the protective layer 30 is removed from the surface of the silicon wafer 1 by heating, and then oxygen is directly introduced into the reaction chamber of the thermal oxidation furnace tube to perform a thermal oxidation reaction, so as to generate the linear oxide layer 3. Therefore, when the silicon wafer 1 is transferred into the thermal oxidation furnace tube, under the protection of the protective layer 30, the natural oxide layer 20 can be prevented from being regenerated on the surface of the silicon wafer 1, the protective layer 30 is directly removed in the thermal oxidation furnace tube, and then only oxygen needs to be introduced into the thermal oxidation furnace tube and the temperature is raised, so that the surface of the silicon wafer 1 and the oxygen are subjected to thermal oxidation reaction to generate the compact linear oxide layer 3. The loose natural oxide layer 20 generated on the surface of the silicon chip 1 in contact with the atmosphere can be effectively avoided in the whole process, so that the residue of the natural oxide layer 20 is reduced as much as possible.
In some embodiments, the temperature of the thermal oxidation method is 900 to 1100 ℃, and the flow rate of the introduced oxygen gas source is 20 to 30SLM.
In the embodiments, the linear oxide layer 3 with higher density can be generated, which is beneficial to repairing the STI sidewall damage and improving the filling effect of HDPCVD or HARP, thereby being beneficial to the isolation of the shallow trench isolation structure from the active region.
In some embodiments, the source of elemental oxygen may be selected from one or more of oxygen, ozone, carbon dioxide, and water.
In some embodiments, the method further comprises: in the thermal oxidation method, hydrogen is introduced into the second reaction chamber.
In these embodiments, the introduction of hydrogen gas can cause the hydrogen and oxygen elemental gas sources to produce water, which, due to the presence of water, facilitates the formation of a more dense linear oxide layer 3.
In some embodiments, the hydrogen flow rate may be 0.8 to 1.0SLM.
In some embodiments, the linear oxide layer 3 is formed on the surface of the silicon wafer 1 from which the protective layer 30 is removed by a thermal oxidation method directly in the second reaction chamber, as shown in fig. 3, and includes:
raising the temperature of the second reaction chamber from the heating temperature to the temperature of the thermal oxidation reaction;
and introducing oxygen into the second reaction chamber, so that the oxygen and the surface of the silicon wafer 1 with the protective layer 30 removed undergo a thermal oxidation reaction to generate a linear oxide layer 3.
In these embodiments, the second reaction chamber is directly heated from the heating temperature to the thermal oxidation temperature, and then oxygen is introduced into the second reaction chamber 200, so that the oxygen and the surface of the silicon wafer with the protective layer 30 removed can undergo a thermal oxidation reaction at the thermal oxidation temperature, and thus the linear oxide layer 3 with higher density can be generated, and the heat loss caused by temperature decrease and temperature increase can be reduced.
In some embodiments, the temperature is increased at a rate of 75-125 deg.C/s for 10-12s.
In these embodiments, the native oxide layer 20 may be eliminated to the greatest extent by controlling the rate and time of the temperature increase.
In some embodiments, ramping up the second reaction chamber from the heated temperature to the temperature of the thermal oxidation reaction comprises:
the second reaction cavity is heated from the heating temperature to the first temperature, the oxygen element gas source and the surface of the silicon wafer with the protective layer removed react to generate a thermal oxide lining layer at the first temperature, then the second reaction cavity is heated from the first temperature to the temperature of the thermal oxidation reaction, and the thermal oxide layer continues to grow on the thermal oxide lining layer until the linear oxide layer 3 is formed on the surface of the silicon wafer 1 with the protective layer 30 removed.
In these embodiments, the linear oxide layer 3 may include a thermal oxide liner layer and a subsequently grown thermal oxide layer. The formation of the thermal oxide liner layer can reduce the generation of a natural oxide layer, eliminate the generation of the natural oxide layer as much as possible, and can prepare for the growth of a subsequent thermal oxide layer, thereby improving the film formation quality of the entire linear oxide layer 3.
In some embodiments, the first temperature may be 600 to 750 ℃.
In some embodiments, as shown in fig. 1, the method further comprises: s4) depositing silicon oxide by adopting HDPCVD or HARP to form a dielectric layer 4 in the shallow trench structure of the linear oxide layer 3.
In these embodiments, the dielectric layer 4 is filled in the shallow trench structure 2to isolate the active region.
Some embodiments of the present application provide a shallow trench isolation structure prepared by the method as described above.
In the shallow trench isolation structure, the natural oxide layer 20 hardly exists between the linear oxide layer 3 and the silicon wafer 1, so that the side wall damage caused by STI etching can be better repaired, and the film quality of the linear oxide layer 3 is ensured. Meanwhile, with the improvement of compactness, film forming quality and the like of the linear oxide layer 3, the linear oxide layer 3 can be ensured to have good insulating property, and the subsequent filling effect of HDPCVD or HARP deposited silicon oxide can be ensured, so that the isolation effect of the shallow trench isolation structure on the active region can be effectively improved.
In some embodiments, the shallow trench isolation structure further comprises a dielectric layer 4 filled in the shallow trench isolation structure, and the material of the dielectric layer 4 comprises silicon dioxide.
In the embodiments, the dielectric layer 4 can be formed by HDPCVD or HARP deposition, and since the linear oxide layer 3 has good film forming quality, when the dielectric layer 4 is formed by HDPCVD or HARP deposition, the adhesion property of the dielectric layer 4 on the linear oxide layer 3 can be increased, so that the filling effect of the dielectric layer 4 in the shallow trench structure 2 is improved, and further, the shallow trench isolation effect can be improved.
Some embodiments of the present application provide a semiconductor structure comprising: the shallow trench isolation structure as described above.
Some embodiments of the present application provide a chip comprising: a semiconductor structure as described above.
The present invention is described above with reference to specific embodiments, and in order to objectively explain technical effects produced by the present invention, the following embodiments are described in detail as examples.
In the following examples, all the raw materials were commercially available and, in order to maintain the reliability of the experiment, the raw materials used in the following examples all had the same physical and chemical parameters or were subjected to the same treatment.
Example 1
The preparation method of the shallow trench isolation structure provided in embodiment 1 includes the following steps:
step 1), providing a wafer which is subjected to STI etching, wherein a natural oxide layer (native oxide) exists on the STI side wall and the silicon surface of the wafer;
step 2), removing natural oxide layers (native oxide) on the surface of the wafer and the surface of the STI by adopting a SiCoNi etching technology, and specifically operating as follows: placing a wafer with a natural oxide layer on the surface in a SiCoNi reaction cavity of PVD equipment, and introducing NF into the reaction cavity 3 （14sccm）、NH 3 (70 sccm) and turn on Power:30W, the power on time is about 9s, the temperature is normal temperature, and the reaction equation is as follows: (NF) 3 +NH 3 →NH 4 F/NH 4 HF and NF 4 F/NH 4 F.HF+SiO 2 →(NH 4 ) 2 SiF 6 (s)+H 2 O), the SiCoNi etching technology has higher etching selectivity, almost does not react with silicon nitride and silicon when etching a natural oxide layer, and protects the original appearance of the surface of a wafer;
step 3), forming on the surface of the wafer and the surface of the shallow trench structure after the etching is finishedSolid by-product ammonium hexafluorosilicate ((NH) 4 ) 2 SiF 6 ) As a protective layer, preventing the formation of a native oxide layer;
step 4), placing the wafer with the surface covered with the ammonium hexafluorosilicate by-product in a reaction chamber of a thermal oxidation furnace with the vacuum degree of 6.8Torr at normal temperature, then gradually heating to 180 ℃ and keeping for 15s to ensure that the ammonium hexafluorosilicate by-product is sublimated from a solid state to a gaseous state to be decomposed and volatilized, wherein the reaction equation is as follows: (NH) 4 ) 2 SiF 6 (s)→SiF 4 (g)+NH 3 (g)+HF(g)）；
And 5) after the steps are finished, heating the reaction cavity of the thermal oxidation furnace to 600 ℃, keeping the temperature for 8s, then heating to the growth temperature of the normal linear oxide layer of about 900 ℃, and keeping the temperature for 10s, thereby finishing the growth process of the linear oxide layer.
Example 2
The preparation method of the shallow trench isolation structure in the embodiment 2 is basically the same as that of the shallow trench isolation structure in the embodiment 1, and the difference is that: in the step 2) of the embodiment 2), the flow rate of NF3 is 30sccm, the flow rate of NH3 is 100sccm, the radio frequency is 30W, and the temperature is normal temperature; in the step 4), the vacuum degree is 7.2Torr, the temperature is raised to 190 ℃, and the temperature is kept for 30s; in the step 5), the temperature is firstly increased to 750 ℃ and kept for 8s, and then the temperature is increased to 1100 ℃ and kept for 12s.
Example 3
The preparation method of the shallow trench isolation structure in the embodiment 3 is basically the same as that of the shallow trench isolation structure in the embodiment 1, except that: in the step 2) of example 3, the flow rate of NF3 was 20sccm, the flow rate of NH3 was 85sccm, the radio frequency was 30W, and the temperature was room temperature; in the step 4), the vacuum degree is 7.0Torr, the temperature is raised to 185 ℃, and the temperature is kept for 25s; in the step 5), the temperature is firstly increased to 680 ℃ and kept for 8s, and then the temperature is increased to 1000 ℃ and kept for 11s.
Test example
The natural oxide layer in the shallow trench isolation structures provided in embodiments 1 to 3 is subjected to a spectrum test (ellipsometer) to obtain a natural oxide layer of less than about 4 angstroms, which indicates that the natural oxide is completely removed.
In summary, by using the SiCoNi etching process to etch the natural oxide layer 20 on the surface of the shallow trench structure 2, the natural oxide layer 20 on the surface of the shallow trench structure 2 can be removed, and the protection layer 30 is generated, where the protection layer 30 is made of a material including: ammonium hexafluorosilicate. Thus, before the linear oxide layer 3 is formed on the surface of the silicon wafer 1, the silicon wafer is transferred into a thermal oxidation furnace tube under the protection of the protection layer 30, so that the surface of the shallow trench structure can be protected from the atmosphere, after the silicon wafer is transferred into the thermal oxidation furnace tube, the protection layer 30 is removed in the thermal oxidation furnace tube through vacuum heating, then the temperature of the thermal oxidation furnace tube is directly raised to the temperature of thermal oxidation reaction, so that the surface of the shallow trench structure and oxygen are subjected to the thermal oxidation reaction to generate the linear oxide layer, the natural oxide layer can be possibly removed completely, the phenomenon that the natural oxide layer is reintroduced in the middle process is reduced, the finally formed linear oxide layer 3 has good compactness and film forming quality, and therefore the silicon wafer can be ensured to have good insulating performance, the subsequent HDPCVD or HARP has good filling effect, and further the isolation effect of the shallow trench isolation structure on an active region can be improved. The problem of among the shallow trench isolation structure among the relevant art because the existence of natural oxide layer is unfavorable for the growth of follow-up linear oxide layer, and then be unfavorable for shallow trench isolation structure to keep apart the active area is solved.
All possible combinations of the technical features of the above embodiments may not be described for the sake of brevity, but should be considered as within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.
Claims (13)
1. A method for preparing a shallow trench isolation structure is characterized by comprising the following steps:
forming a shallow trench structure on a silicon chip, wherein a natural oxide layer is formed on the surface of the shallow trench structure;
removing the natural oxide layer by adopting a SiCoNi etching process, and forming a protective layer on the surface of the silicon wafer with the natural oxide layer removed, wherein the protective layer is made of the following materials: ammonium hexafluorosilicate;
and removing the protective layer, and forming a linear oxide layer on the surface of the silicon wafer with the protective layer removed.
2. The method of claim 1,
removing the natural oxide layer by adopting a SiCoNi etching process, and forming a protective layer on the surface of the silicon wafer from which the natural oxide layer is removed, wherein the method comprises the following steps:
placing the silicon wafer with the natural oxide layer in a first reaction cavity;
NH is introduced into the first reaction chamber 3 、NF 3 And a plasma gas source;
make the NH to 3 And NF 3 Under the excitation of plasma, the protective layer reacts with the natural oxide layer to convert the natural oxide layer into the protective layer.
3. The method of claim 2,
the NH 3 The flow rate of the (1) is 70 to 100sccm, and the NF is 3 The flow rate of the flow rate is 14 to 30sccm.
4. The method of claim 2,
and removing the protective layer and forming a linear oxide layer on the surface of the silicon wafer from which the protective layer is removed in the same reaction cavity.
5. The method of claim 1 or 2, wherein said removing the protective layer comprises:
placing the silicon wafer with the protective layer in a second reaction cavity;
vacuumizing the second reaction cavity until the vacuum degree in the second reaction cavity is 6.8to 7.2Torr;
and heating the second reaction cavity to sublimate and remove the protective layer from the surface of the silicon wafer.
6. The method of claim 5,
the heating temperature is 180 to 190 ℃, and the heating time is 15 to 30s.
7. The method of claim 5, wherein the forming a linear oxide layer on the surface of the silicon wafer from which the protective layer is removed comprises:
and after the protective layer is removed, directly forming the linear oxide layer on the surface of the silicon wafer with the protective layer removed in the second reaction cavity by a thermal oxidation method.
8. The method of claim 7,
the temperature of the thermal oxidation method is 900 to 1100 ℃, and the flow of the introduced oxygen element air source is 20 to 30SLM.
9. The method of claim 7,
forming the linear oxide layer on the surface of the silicon wafer with the protective layer removed by a thermal oxidation method directly in the second reaction chamber, wherein the linear oxide layer comprises:
raising the temperature of the second reaction chamber from the heating temperature to the temperature of the thermal oxidation reaction;
and introducing an oxygen source gas into the second reaction cavity, so that the oxygen source gas and the surface of the silicon wafer with the protective layer removed are subjected to thermal oxidation reaction to generate the linear oxide layer.
10. The method of claim 9,
the temperature rising speed is 75 to 125 ℃/s, and the time is 10 to 12s.
11. A shallow trench isolation structure prepared by the method of any one of claims 1 to 10.
12. A semiconductor structure, comprising:
the shallow trench isolation structure of claim 11.
13. A chip, comprising:
the semiconductor structure of claim 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310032176.4A CN115881621A (en) | 2023-01-10 | 2023-01-10 | Shallow trench isolation structure and preparation method thereof, semiconductor structure and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310032176.4A CN115881621A (en) | 2023-01-10 | 2023-01-10 | Shallow trench isolation structure and preparation method thereof, semiconductor structure and chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115881621A true CN115881621A (en) | 2023-03-31 |
Family
ID=85758361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310032176.4A Pending CN115881621A (en) | 2023-01-10 | 2023-01-10 | Shallow trench isolation structure and preparation method thereof, semiconductor structure and chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115881621A (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030143852A1 (en) * | 2002-01-25 | 2003-07-31 | Nanya Technology Corporation | Method of forming a high aspect ratio shallow trench isolation |
| US20030199151A1 (en) * | 2002-04-18 | 2003-10-23 | Nanya Technology Corporation | Method of fabricating a shallow trench isolation structure |
| US20040142562A1 (en) * | 2003-01-16 | 2004-07-22 | Zhen-Long Chen | Method of fabricating a shallow trench isolation structure |
| US7416989B1 (en) * | 2006-06-30 | 2008-08-26 | Novellus Systems, Inc. | Adsorption based material removal process |
| US20090298294A1 (en) * | 2008-05-30 | 2009-12-03 | United Microelectronics Corp. | Method for clearing native oxide |
| CN102687249A (en) * | 2009-12-23 | 2012-09-19 | 应用材料公司 | Smooth siconi etch for silicon-containing films |
| CN103972161A (en) * | 2014-05-08 | 2014-08-06 | 上海华力微电子有限公司 | SiCoNi etching method for through-silicon-via morphology correction |
| CN104269371A (en) * | 2014-09-01 | 2015-01-07 | 上海华力微电子有限公司 | Etching device and method |
| CN104992903A (en) * | 2015-07-30 | 2015-10-21 | 上海华力微电子有限公司 | High-quality gate oxide forming method |
| CN105742157A (en) * | 2014-12-30 | 2016-07-06 | Asm Ip控股有限公司 | Germanium Oxide Pre-Clean Module And Process |
| CN110752213A (en) * | 2019-10-25 | 2020-02-04 | 上海华力微电子有限公司 | Method for manufacturing semiconductor structure |
-
2023
- 2023-01-10 CN CN202310032176.4A patent/CN115881621A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030143852A1 (en) * | 2002-01-25 | 2003-07-31 | Nanya Technology Corporation | Method of forming a high aspect ratio shallow trench isolation |
| US20030199151A1 (en) * | 2002-04-18 | 2003-10-23 | Nanya Technology Corporation | Method of fabricating a shallow trench isolation structure |
| US20040142562A1 (en) * | 2003-01-16 | 2004-07-22 | Zhen-Long Chen | Method of fabricating a shallow trench isolation structure |
| US7416989B1 (en) * | 2006-06-30 | 2008-08-26 | Novellus Systems, Inc. | Adsorption based material removal process |
| US20090298294A1 (en) * | 2008-05-30 | 2009-12-03 | United Microelectronics Corp. | Method for clearing native oxide |
| CN102687249A (en) * | 2009-12-23 | 2012-09-19 | 应用材料公司 | Smooth siconi etch for silicon-containing films |
| CN103972161A (en) * | 2014-05-08 | 2014-08-06 | 上海华力微电子有限公司 | SiCoNi etching method for through-silicon-via morphology correction |
| CN104269371A (en) * | 2014-09-01 | 2015-01-07 | 上海华力微电子有限公司 | Etching device and method |
| CN105742157A (en) * | 2014-12-30 | 2016-07-06 | Asm Ip控股有限公司 | Germanium Oxide Pre-Clean Module And Process |
| CN104992903A (en) * | 2015-07-30 | 2015-10-21 | 上海华力微电子有限公司 | High-quality gate oxide forming method |
| CN110752213A (en) * | 2019-10-25 | 2020-02-04 | 上海华力微电子有限公司 | Method for manufacturing semiconductor structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2776726B2 (en) | Method for manufacturing semiconductor device | |
| JP4340830B2 (en) | Method for forming gate insulating film of semiconductor device | |
| US7442620B2 (en) | Methods for forming a trench isolation structure with rounded corners in a silicon substrate | |
| CN100459072C (en) | Method of forming thin SGOI wafers with high relaxation and low stacking fault defect density | |
| KR100637689B1 (en) | Method for forming contact of semiconductor device using solid phase epitaxy | |
| JP2009177161A (en) | Method for forming insulation film | |
| KR20110104482A (en) | Gapfill improvement with low etch rate dielectric liners | |
| JPH05347249A (en) | Low-temperature silicon epitaxial growth method | |
| US10741390B2 (en) | Forming method of epitaxial layer, forming method of 3D NAND memory and annealing apparatus | |
| CN103928387A (en) | Method for padding shallow trench isolation structure and preparation method for semiconductor device | |
| KR100390919B1 (en) | Method for fabricating semiconductor device | |
| KR20200074898A (en) | Method for fabricating a monocrystalline structure | |
| CN111933572A (en) | Semiconductor structure and manufacturing method thereof | |
| JP2006520540A (en) | Process for forming shallow trench isolation for strained silicon processes. | |
| CN115881621A (en) | Shallow trench isolation structure and preparation method thereof, semiconductor structure and chip | |
| KR20010009810A (en) | Trench-type isolation method using Si-Ge epitaxial layer | |
| WO2001047006B1 (en) | Tunnel nitride for improved polysilicon emitter | |
| CN101183659B (en) | Groove isolation technology employed on the surface of silicon chip | |
| TW202038379A (en) | Methods of forming semiconductor devices | |
| KR20120140112A (en) | Manufacturing method of semiconductor device | |
| KR20020037337A (en) | Method for forming crystalline silicon nitride | |
| CN104795351A (en) | Method for forming isolation structure | |
| JP4946017B2 (en) | Manufacturing method of semiconductor device | |
| CN104979204B (en) | The forming method of fin formula field effect transistor | |
| JP2701793B2 (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20230331 |