TW202038379A - Methods of forming semiconductor devices - Google Patents

Abstract

A method includes etching a semiconductor substrate to form a trench, and depositing a dielectric layer using an Atomic Layer Deposition (ALD) cycle. The dielectric layer extends into the trench. The ALD cycle includes pulsing Hexachlorodisilane (HCD) to the semiconductor substrate, purging the HCD, pulsing triethylamine to the semiconductor substrate, and purging the triethylamine. An anneal process is then performed on the dielectric layer.

Description

Manufacturing method of semiconductor device

The embodiments of the present invention are related to semiconductor manufacturing technology, and particularly to semiconductor devices and manufacturing methods thereof.

As the size of the integrated circuit becomes smaller and the requirements for the speed of the integrated circuit become higher and higher, the transistor requires a higher drive current and is accompanied by a smaller and smaller size. Therefore, Fin Field-Effect Transistors (FinFET) were developed. Fin-type field effect transistors include vertical semiconductor fins on the substrate. The semiconductor fins are used to form source and drain regions, and to form a channel region between the source and drain regions. A Shallow Trench Isolation (STI) region is formed to define the semiconductor fins. The fin field effect transistor also includes a gate stack formed on the sidewall and top surface of the semiconductor fin.

In the formation of shallow trench isolation regions and the formation of fin-type field effect transistors, the shallow trench isolation regions are formed first, such as using a flowable oxide, followed by ultraviolet light (Ultra-Violet, UV) curing or oxygen-containing Thermal oxidation in the environment is post-processed. Then, the corresponding wafers are annealed.

According to some of the embodiments of the present invention, a method of manufacturing a semiconductor device is provided. The method includes: etching the semiconductor substrate to form a trench; depositing a dielectric layer using an atomic layer deposition cycle, wherein the dielectric layer extends into the trench, and wherein the atomic layer deposition cycle includes pulsing hexachlorodisilane to the semiconductor substrate; Blow off hexachlorodisilane; pulse triethylamine onto the semiconductor substrate; and blow off triethylamine; and perform an annealing process on the dielectric layer.

According to some other embodiments of the embodiments of the present invention, methods for manufacturing semiconductor devices are provided. The method includes depositing a dielectric layer on the semiconductor strip, wherein the deposition of the dielectric layer includes a cycle, and the cycle includes: attaching silicon and chlorine atoms to oxygen atoms on the semiconductor strip; replacing with nitrogen atoms and alkyl groups And replacing the nitrogen atom and the first part of the alkyl group with an oxygen atom; removing the nitrogen atom and the second part of the alkyl group with an OH bond; and annealing the dielectric layer to form a Si-O-Si bond.

According to still other embodiments of the embodiments of the present invention, methods for manufacturing semiconductor devices are provided. The method includes forming a first semiconductor strip; depositing a dielectric layer containing silicon oxide, carbon doped in the silicon oxide, wherein the dielectric layer includes: a horizontal portion; and one end of the vertical portion connected to the horizontal portion, wherein the vertical portion Contacting the sidewall of the lower portion of the first semiconductor strip, wherein the top of the first semiconductor strip protrudes higher than the top surface of the vertical portion to form a semiconductor fin; and forming a gate stack to extend on the sidewall and top surface of the semiconductor fin.

The following content provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are only examples and are not used to limit the embodiments of the present invention. For example, if it is mentioned in the description that the first part is formed on or above the second part, it may include an embodiment where the first part and the second part are in direct contact, or may include additional parts formed on the first part and the second part. Between the two parts, the first part and the second part are not in direct contact. In addition, the embodiment of the present invention may reuse reference numbers and/or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not represent a specific relationship between the different embodiments and/or configurations discussed.

In addition, this article may use spatial relative terms, such as "below...", "below...", "below", "above...", "above" and similar terms, which are relative to each other. The terminology is used to facilitate the description of the relationship between one element(s) or component(s) and another element(s) or component(s) as shown in the figure. These spatial relative terms include the different orientations of the devices in use or operation, as well as the orientations described in the diagrams. When the device is turned in different directions (rotated by 90 degrees or other directions), the spatially relative adjectives used here will also be interpreted according to the turned position.

Provide shallow trench isolation regions, fin-type field effect transistors and their forming methods. According to some embodiments, the intermediate stage of the formation process of the shallow trench isolation region and the fin field effect transistor is illustrated. Discuss some variations of some embodiments. Throughout the various schematic diagrams and illustrative embodiments, similar reference numerals are used to indicate similar elements. According to some of the embodiments of the present invention, the shallow trench isolation region is formed by forming a SiNOCH film, and then performing an annealing process to convert Si-NC bonds in the SiNOCH film into Si-OH bonds, and then into Si- O-Si bond. Through these processes, the shallow trench isolation region obtained has no or substantially no voids and seams.

The embodiment will be described for a specific background, that is, a shallow trench isolation formation process by forming a conformal shallow trench isolation layer. The concepts of the discussed embodiments can also be applied to the structure and processing of other structures, including but not limited to any other gap filling process to be filled with silicon oxide. The embodiments discussed here will provide examples to enable or use the subject matter of the embodiments of the present invention, and those with ordinary knowledge in the technical field to which the invention pertains will easily understand the modifications that can be made while maintaining the various embodiments.​​​​ Within the expected range. Similar reference numbers and symbols in the following figures indicate similar components. Although method embodiments performed in a specific order can be discussed, other method embodiments can be performed in any logical order.

FIGS. 1, 2A, 2B, and 3-9 illustrate schematic cross-sectional views of an intermediate stage of forming a part of a shallow trench isolation region and a fin-type field effect transistor according to some embodiments of the present invention. The corresponding manufacturing process is also schematically shown in the manufacturing process 200 shown in FIG. 22.

In Figure 1, a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor substrate, a Semiconductor-On-Insulator (SOI) substrate, or a similar substrate, which may be doped (for example, with p-type or n-type dopants). ) Or without adulteration. The semiconductor substrate (also referred to as the substrate) 20 may be a part of the wafer 10, such as a silicon wafer. In general, the semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer or a similar film layer. The insulating layer is provided on a substrate that is usually a silicon or glass substrate. Other substrates can also be used, such as multilayer or graded substrates. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; alloy semiconductors, Contains SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; or a combination of the foregoing.

Further referring to FIG. 1, a well region 22 is formed in the base 20. The corresponding process is shown as process 202 in the process flow 200 shown in FIG. 22. According to some of the embodiments of the present invention, the well region 22 is a p-type well region, which is formed by implanting p-type impurities into the substrate 20, and the p-type impurities may be boron, indium or similar impurities. According to other embodiments in the embodiment of the present invention, the well region 22 is an n-type well region, which is formed by implanting n-type impurities into the substrate 20. The n-type impurities may be phosphorus, arsenic, antimony or similar impurities. . The formed well region 22 may extend to the top surface of the substrate 20. The n-type or p-type impurity concentration may be equal to or less than 10 ¹⁸ cm ^-3 , for example, in the range of about 10 ¹⁷ cm ^-3 to about 10 ¹⁸ cm ^-3 .

Referring to FIG. 2A, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20. The pad oxide layer 28 may be a thin film formed of silicon oxide. According to some of the embodiments of the present invention, the pad oxide layer 28 is formed in a thermal oxidation process, wherein the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 can also serve as an etch stop layer for etching the hard mask layer 30. According to some of the embodiments of the present invention, the hard mask layer 30 is formed of silicon nitride, for example, using Low-Pressure Chemical Vapor Deposition (LPCVD). According to other embodiments in the embodiments of the present invention, the hard mask layer 30 is formed by thermal nitridation of silicon or plasma-assisted chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD). A patterned photoresist (not shown) is formed on the hard mask layer 30. Then, using the patterned photoresist as an etching mask, the hard mask layer 30 and the pad oxide layer 28 are patterned to form a patterned hard mask as shown in Figure 2A (also called a hard mask). Cover) 30.

Then, the patterned hard mask layer 30 serves as an etching mask to etch the pad oxide layer 28 and the substrate 20, thereby forming a trench 32 in the substrate 20, as shown in FIG. 2A. The corresponding process is shown as process 204 in the process flow 200 shown in FIG. 22. According to some of the embodiments of the present invention, the grooves 32 are formed as groove strips whose length directions are parallel to each other. The portion of the semiconductor substrate 20 between the trenches 32 is referred to as a semiconductor strip 26 hereinafter.

Figure 2B is a schematic cross-sectional view of the reference section 2B-2B in Figure 2A. To simplify the discussion, two semiconductor strips 26 are shown, and the trenches between them are called narrow trenches 32A. There may be a group of closely arranged semiconductor strips 26 separated from each other by narrow trenches 32A. According to some embodiments, the narrow trench 32A has a small width W1, which may be less than about 250 Å, or in the range of about 100 Å to about 250 Å. For example, there may also be wide trenches on the opposite outer side of the group of closely arranged semiconductor strips 26. The width W2 of the wide trench 32B is greater than the width W1, for example, the ratio W2/W1 is greater than about 2.0. The width W2 can also be greater than about 150 Å. The grooves (also called narrow grooves) 32A and (also called wide grooves) 32B are collectively called grooves 32. According to some of the embodiments of the present invention, the depth D1 of the narrow trench 32A is smaller than the depth D2 of the wide trench 32B.

Figures 3 and 4 illustrate the intermediate stages of the growth/deposition of the dielectric layer 34. The corresponding process is shown as process 206 in the process flow 200 shown in FIG. 22. At the beginning of the deposition process, the wafer 10 is placed in an Atomic Layer Deposition (ALD) chamber (not shown), where an Atomic Layer Deposition cycle is performed to grow the dielectric layer 34 compliantly. FIG. 3 shows the initial growth of the dielectric layer 34, which is compliant, and the thickness T1 of the horizontal portion of the dielectric layer 34 is equal to the thickness T2 of the vertical portion of the dielectric layer 34.

FIG. 10 schematically shows the intermediate chemical structure during the growth of the dielectric layer 34. The reference numerals 112, 114, 116, and 118 are used to denote the intermediate structure shown in FIG. 10 to distinguish the structures generated by different stages. The wafer 10 includes a base layer 110, which can represent the components exposed in Figure 3, including a substrate 20, a semiconductor strip 26, a pad layer (also called a pad oxide layer) 28, and a hard mask. The cover 30, as long as these components are exposed at the beginning of the deposition process. The initial structure in Figure 10 is called structure 112. In the illustrated example, the substrate layer 110 is shown as containing silicon. The silicon may be in the form of crystalline silicon, amorphous silicon, polycrystalline silicon, or silicon in a compound. According to some of the embodiments of the present invention, due to the formation of native oxide and exposure to moisture, Si—OH bonds are formed on the surface of the silicon-containing layer (also referred to as the substrate layer) 110. The substrate layer 110 may include other types of silicon-containing materials, such as silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, or similar materials. As shown in FIG. 3, the dielectric layer 34 can also be deposited on other non-silicon-containing layers, such as the liner layer 28 and the hard mask 30.

Referring again to FIG. 10, in the process 130, hexachlorodisilane (HCD) is introduced/pulsed into the atomic layer deposition chamber in which the wafer 10 (FIG. 3) is placed. The corresponding process is shown as process 208 in the process flow 200 shown in FIG. 22. HCD has the chemical formula (SiCl ₃ ) ₂ . Figure 11A illustrates the chemical formula of HCD molecules according to some embodiments. The chemical formula shows that the HCD molecule contains a chlorine atom bonded to two silicon atoms. When the HCD is pulsed into the atomic layer deposition chamber, the wafer 10 is heated to a temperature of, for example, about 550°C to about 670°C. The OH bond shown in structure 112 is broken, and the silicon atom and the chlorine atom bonded to them are bonded to the oxygen atom to form an O-Si-Cl bond. The resulting structure is called structure 114. According to some of the embodiments of the present invention, when HCD is introduced, the plasma is not turned on. The HCD gas can be maintained in the atomic layer deposition chamber for a period of about 20 seconds to about 25 seconds. According to some embodiments, the pressure of the atomic layer deposition chamber may range from about 100 Pascals (Pa) to about 150 Pa.

Next, the HCD is purged from the atomic layer deposition chamber. The corresponding process is also shown as process 208 in the process flow 200 shown in FIG. 22. In the process 132, a process gas containing nitrogen atoms bonded to an alkyl group may be pulsed into the atomic layer deposition chamber. For example, triethylamine can be pulsed. The corresponding process is shown as process 210 in the process flow 200 shown in FIG. 22. Triethylamine may have the chemical formula N(CH ₂ CH ₃ ) ₃ , which contains a nitrogen atom bonded to three ethyl groups (CH ₂ CH ₃ ). Figure 11B illustrates the chemical formula of triethylamine according to some embodiments. The chemical formula shows that triethylamine contains one nitrogen atom bonded to three ethyl groups, and each ">" symbol connected to the N atom represents an ethyl group (CH ₂ CH ₃ or CH ₂ molecule bonded to a CH ₃ molecule). With the introduction/pulsing of triethylamine, the temperature of the wafer 10 also keeps increasing, for example, in the range of about 550°C to about 670°C. The temperature can also be kept the same as the temperature of the process introduced into the HCD. According to some of the embodiments of the present invention, when triethylamine is introduced, the plasma is not turned on. During the pulse of triethylamine, the pressure of the atomic layer deposition chamber may range from about 800 Pa to about 1,000 Pa.

Structure 114 reacts with triethylamine. The resulting structure is called structure 116. The Si-Cl bond in structure 114 is broken so that nitrogen atoms (such as in triethylamine) can bond to silicon atoms. Silicon atoms can be bonded to three nitrogen atoms, and each nitrogen atom is also bonded to two ethyl groups. In the process 132, the triethylamine may be kept in the atomic layer deposition chamber for about 5 seconds to about 15 seconds, and then the triethylamine may be blown out of the atomic layer deposition chamber.

Next, as shown in the process 134 in FIG. 10, oxygen (O ₂ ) is pulsed into the atomic layer deposition chamber. The corresponding process is shown as process 212 in the process flow 200 shown in FIG. 22. In the process 212, the structure 116 reacts with oxygen to produce the structure 118. Alkyl groups (such as the ethyl group in structure 116) help convert Si-N into Si-O bonds. For example, the Si-N bond in structure 116 is broken by process 134 and the silicon atom is bonded to Oxygen atom. Some nitrogen atoms and their bonded ethyl groups can also remain bonded to silicon atoms. Some oxygen atoms can be bonded to two silicon atoms to create cross-links between some silicon atoms. According to some of the embodiments of the present invention, when oxygen is introduced, the plasma is not turned on. During the pulse of oxygen, the pressure of the atomic layer deposition chamber may range from about 800 Pa to about 1,000 Pa. The oxygen can be kept in the atomic layer deposition chamber for a period of about 5 seconds to about 15 seconds, and then blown out of the atomic layer deposition chamber.

In the process discussed above, the combination of processes 130 and 132 may be referred to as an atomic layer deposition cycle 136. The atomic layer deposition cycle 136 allows the growth of an atomic layer containing silicon atoms and bonding nitrogen atoms and ethyl groups accordingly. In addition, the combination of processes 130, 132, and 134 can also be referred to as an atomic layer deposition cycle 138. The atomic layer deposition cycle 138 allows the growth of an atomic layer containing silicon atoms and the corresponding bonded nitrogen atoms and ethyl groups, and bonding oxygen. atom. According to some embodiments, the atomic layer produced by the atomic layer deposition cycle 138 has a thickness of about 1 Å.

After the process 134 is completed, the atomic layer deposition cycle 138 including the processes 130, 132, and 134 is repeated to deposit a plurality of atomic layers to form the dielectric layer 34, as shown in FIG. In the subsequent atomic layer deposition cycle, the Si-O bond and Si-N bond formed in the previous atomic layer deposition cycle can be broken, and the Si-Cl bond can be formed due to the pulse of HCD. The Si-Cl bond can then be replaced with a Si-N bond and the corresponding ethyl group. Then you can use O _{2 to} form Si-O bonds, with Si-O bonds replacing some of the Si-N bonds. Figure 12 shows the additional atomic layer as an example. It should be understood that, depending on the desired thickness of the dielectric layer 34, there may be many atomic layers. The deposited dielectric layer 34 is a SiONCH layer.

The atomic layer deposition cycle 138 is repeated until the resulting dielectric layer 34 has the desired thickness. For example, as shown in FIG. 4, the portions of the dielectric layer 34 grown from adjacent semiconductor strips 26 grow toward each other, and eventually contact each other to produce an interface 36. It should be understood that the place where a seam may occur is also referred to as the interface 36. Some voids 38 may also be generated at the interface 36, and these voids 38 may be due to small grooves on the sidewall of the semiconductor strip 26. It should be understood that although the portions of the dielectric layer 34 grown from the adjacent semiconductor strips 26 are in contact with each other, these portions only contact each other without forming cross-links between them. For example, Figure 13 schematically shows a seam/interface 36 formed between the left part of the dielectric layer 34 and the right part of the dielectric layer 34, between the boundary atoms in the left part and the right part No crosslinks are formed.

According to some of the embodiments of the present invention, after the atomic layer deposition cycle 138, the resulting dielectric layer 34 has a carbon percentage ranging from about 1% to about 15%, and a nitrogen percentage ranging from about 5% to about 20%. % Range. The remaining elements in the dielectric layer 34 are mainly silicon and oxygen, and the atomic ratio of silicon to oxygen can be about 1.5:2 to about 1:2.5. The ratio can be, for example, about 1:2.

After the deposition (growth) of the dielectric layer 34, an annealing process is performed. The corresponding process is shown as process 214 in the process flow 200 shown in FIG. 22. According to some of the embodiments of the present invention, the annealing process includes a low temperature wet annealing process (process 216), a high temperature wet annealing process (process 218), and a dry annealing process (process 220). Steam (H ₂ O) can be used as a process gas for low temperature process and high temperature wet annealing process. The dry annealing process can use nitrogen (N ₂ ), argon or similar gas as a carrier gas. The annealing process is discussed below with reference to Figures 14 to 20.

According to some of the embodiments of the present invention, a low temperature wet annealing process is first performed. The corresponding process is shown as process 216 in the process flow 200 shown in FIG. 22. The low temperature wet annealing process is performed at a relatively low temperature of about 300°C to about 450°C. The low temperature wet annealing process can last from about 3 hours to about 5 hours. The pressure during the low temperature annealing may be about 1 atmosphere. The low temperature wet annealing process has two functions. The first function is to allow water/steam (H ₂ O) molecules to penetrate into the dielectric layer 34, as shown schematically in Figure 15, where the solid dots represent H ₂ O molecules. The second function is to partially convert Si-NC bonds, Si-CH ₃ bonds, and Si-N-Si bonds in the dielectric layer 34 into Si-OH bonds. Control the temperature to a temperature high enough to cause at least partial conversion.

Figure 21 shows some experimental results, where the X axis represents annealing conditions, including annealing temperature and annealing time. The letter "C" for each X-axis value represents the annealing temperature in degrees Celsius, the letter "M" represents the annealing time in minutes, and the letter "H" represents the annealing time in hours. For example, "W200C30M" represents the corresponding value obtained when the wafer is annealed at 200°C for 30 minutes. There are three Y-axes, representing nitrogen ([N]) atomic percentage, carbon ([C]) atomic percentage, and the expansion rate of the dielectric layer after annealing. The results in Figure 21 indicate that before the annealing process (corresponding to the X-axis value "NA"), the carbon percentage and nitrogen percentage are high. As the annealing process continues and/or higher temperatures are used, the carbon percentage and nitrogen percentage decrease to a certain degree, for example, less than 1%. This means that the original carbon and nitrogen atoms (as shown in Figure 12) begin to convert into OH, as shown in Figure 14. In addition, as shown in Figure 21, when the temperature is higher than 450°C, the expansion rate of the dielectric film may increase. Because the expansion of the surface portion of the dielectric layer 34 is earlier than the inside, the expansion of the surface portion of the dielectric layer 34 will disadvantageously prevent H ₂ O molecules from penetrating and reaching the inside of the dielectric layer 34. Therefore, in order to avoid premature expansion of the surface portion of the dielectric layer 34, a low-temperature wet annealing treatment is performed at a temperature (for example, lower than about 450° C.) at which the dielectric layer 34 does not expand. On the other hand, in order to improve the conversion efficiency and steam permeation efficiency, the low-temperature wet annealing process is performed at a temperature that is not too low, and the temperature can be in the range of about 300°C to about 450°C.

Figures 19 and 20 show the results measured from the sample, and show similar results in the low temperature wet annealing process at 300°C and 450°C. Figure 19 shows the etch rate (of the dielectric layer 34) as a function of the depth into the dielectric layer 34. The etching rate indicates the composition of the dielectric layer 34, such as how many C and N atoms are replaced by OH groups. The values 310 and 312 are the results of annealing at 300°C for 4 hours. The values 314 and 316 are the results of annealing at 450°C for 4 hours. The samples were also annealed under the same higher annealing temperature condition (600°C for 2 hours) and the same dry annealing temperature condition (600°C for 1 hour). Figure 19 shows that although the low temperature wet annealing process is carried out at different temperatures, their etching rates at different depths of the sample are similar, which means that the low temperature wet annealing temperature of 300°C and 450°C will not affect the H The penetration of ₂ O molecules makes the difference.

FIG. 20 shows the carbon concentration as a function of the depth into the dielectric layer 34. Line 318 is also the result of low temperature wet annealing at 300°C for 4 hours. Line 320 is the result of low temperature wet annealing at 450°C for 4 hours. The samples corresponding to lines 318 and 320 were also annealed under the same higher annealing temperature condition (600°C for 2 hours) and the same dry annealing temperature condition (600°C for 1 hour). Figure 20 shows that although the low temperature wet annealing process is carried out at different temperatures, the carbon percentage is similar. The carbon percentage is an indicator of the conversion rate (from CN to OH) of the sample at different depths. These results indicate that using 300°C or 450°C as the temperature of the low-temperature annealing process will not cause differences in the permeability of H ₂ O molecules.

After the low temperature wet annealing process, a high temperature wet annealing process is performed. The corresponding process is shown as process 218 in the process flow 200 shown in FIG. 22. The high temperature wet annealing process is performed at a relatively high temperature of about 450°C to about 650°C. The high temperature wet annealing process can last from about 1.5 hours to about 2.5 hours. The pressure of the high temperature annealing process can be about 1 atmosphere. As shown in Figure 16, the temperature is high enough to effectively convert the Si-C-N bonds in the dielectric layer 34 into Si-OH bonds. On the other hand, the temperature cannot be too high to cause excessive oxidation of the semiconductor material. For example, when the semiconductor strip 26 includes SiGe, the temperature of the high-temperature annealing process should be lower than about 650°C. Otherwise, SiGe may be oxidized. Silicon can also be oxidized at temperatures above about 650°C, albeit at a lower rate. Therefore, the temperature of the high temperature wet annealing process may be in the range of about 500°C to about 650°C or in the range of about 500°C to about 600°C.

The high temperature wet annealing process causes the Si-N bond and Si-O bond to break. The alkyl group attached to the N atom is also disconnected with the nitrogen atom. The OH group is attached to the broken bond. The obtained chemical structure can be schematically shown in Figure 14. Figure 16 shows the structure at the interface 36 (also refer to Figure 4). The Si—OH bonds formed in the portions of the dielectric layer 34 on both sides of the interface 36 are closely arranged, and the portions of the dielectric layer 34 on both sides of the interface 36 may be in contact with each other. But no crosslinks are formed. During the high temperature wet annealing process, the dielectric layer 34 expands, and the expansion rate in volume can be as high as about 10%. As a result of the expansion, the portions of the dielectric layer 34 on both sides of the interface 36 are in close contact with each other, and the seam 36 (Figs. 4 and 15) and the void 38 (Fig. 4) can be eliminated. This makes the subsequent cross-linking process possible.

After the high temperature wet annealing process, a dry annealing process is performed to crosslink. The corresponding process is shown as process 220 in the process flow 200 shown in FIG. 22. Oxygen-free process gases (such as nitrogen (N ₂ ), argon, or similar gases) can be used as process gases. The dry annealing temperature cannot be too high or too low. If the temperature is too low, the OH bond may not be broken, and crosslinking may not be achieved. If the temperature is too high, the semiconductor (such as SiGe) may mix with the surrounding materials. According to some of the embodiments of the present invention, the dry annealing process is performed at a temperature of about 550°C to about 650°C. The dry annealing process can last from about 0.5 hours to about 1.5 hours. The pressure can be about 1 atmosphere. The carrier gas can be used to take away the generated H ₂ O vapor. The carrier gas can be nitrogen, argon or similar gas.

In the dry annealing process, the OH bond and the Si-O bond (Figures 14 and 16) are broken, and the broken H and OH combine to form H ₂ O molecules, as shown in Figure 18. Due to the loss of H atoms, the metal bond will be suspended and may bond with Si to form silicon oxide (SiO ₂ ). After the dry annealing process is completed, a small amount of carbon and nitrogen atoms may remain in the silicon oxide (dielectric layer 34), wherein the atomic percentage of carbon and nitrogen is less than about 1%, and may be about 0.5% to about 1.0%. This is different from the shallow trench isolation region formed using traditional methods, in which carbon may not be present.

As shown in Figure 18, the silicon atoms on both sides of the previously existing interface/joint 36 are cross-linked by oxygen atoms. Therefore, crosslinks are formed between the portions of the dielectric layer 34 on both sides of the interface 36. The H ₂ O molecules represented by the solid dots are taken away. Figure 5 shows the resulting structure, in which the seams/interfaces formed during the deposition process have been eliminated, and there may no longer be distinguishable interfaces.

According to some embodiments, in the previous process, the narrow trench 32A is completely filled. Since the deposition of the dielectric layer 34 is performed using atomic layer deposition of a compliant deposition method, when the deposition process is completed, the wide trench 32B may not be completely filled. Therefore, as shown in FIG. 5, some parts of the wide trench 32B are left unfilled. The portion of the dielectric layer 34 in the wide trench 32B is compliant.

Referring to FIG. 6, the remaining wide trench 32B is filled with a dielectric layer 40. The corresponding process is shown as process 222 in the process flow 200 shown in FIG. 22. The dielectric layer 40 can also be a deposited silicon nitride layer, a carbon-containing dielectric or similar materials. The dielectric layer 40 is formed using, for example, atomic layer deposition, high-density plasma chemical vapor deposition (High-Density Plasma Chemical Vapor Deposition). Vapor Deposition, HDPCVD) or chemical vapor deposition (Chemical Vapor Deposition, CVD). The dielectric layer 40 may also be formed of SiOCN, using Flowable Chemical Vapor Deposition (FCVD), spin-on coating or similar processes. The dielectric layer 40 is deposited to a height higher than the top surface of the dielectric layer 34.

Referring to FIG. 7, a planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed to remove the excess portion of the dielectric material. The remaining part of the dielectric material is the shallow trench isolation region 42. The corresponding process is also shown as process 222 in the process flow 200 shown in FIG. 22. The hard mask 30 can be used as a chemical mechanical polishing stop layer for the planarization process. The shallow trench isolation region 42 between the closely arranged semiconductor strips 26 may be formed of a homogeneous material, which extends to the opposite semiconductor strip 26. The shallow trench isolation region formed in the wide trench may include a compliant dielectric layer 34 and a dielectric layer 40. Although a vertical portion is shown, the dielectric layer 34 has vertical portions on both sides of the dielectric region (also called shallow trench isolation region) 42 and contacts the two sidewalls of the dielectric region 42.

Then, the hard mask 30 and the pad oxide layer 28 are etched. As shown in FIG. 8, the dielectric layer 34 is etched so that the top of the semiconductor strip 26 protrudes higher than the top surface 34A of the remaining part of the shallow trench isolation region 42 to form a protruding fin 44. The corresponding process is shown as process 224 in the process flow 200 shown in FIG. 22. A dry etching process can be used for etching, for example, HF ₃ and NH _{3 are} used as the etching gas. According to an alternative embodiment of the embodiment of the present invention, the etchback of the dielectric layer 34 is performed using a wet etching process. The etching chemistry may include, for example, an HF solution.

During the etchback process, the dielectric layer 40 is not etched, so that the dummy (dielectric) fin 46 protrudes higher than the top surface 34A of the remaining part of the shallow trench isolation region 42. The dummy dielectric fin 46 is so named because the component (also called dummy fin) 46 protrudes higher than the adjacent dielectric layer 34, thus forming fins, and these fins are different from those used to form fin field effects. Typical semiconductor fins for transistors, these fins cannot be used to form fin-type field effect transistors. Due to the conformal deposition of the dielectric layer 34, when the narrow trench 32A is filled with the dielectric layer 34, the wide trench 32B (Figure 2B) is not completely filled. This makes the filling of the dielectric layer 40 possible and the formation of the dummy fin 46 possible. When the size of the fin field effect transistor is very small, the generation of dummy fins helps to improve the device performance of the fin field effect transistor.

In the subsequent forming process, a fin field effect transistor 54 is formed based on the protruding semiconductor fin 44 (FIG. 9). FIG. 9 shows a schematic cross-sectional view of the protruding fin 44 and the gate stack 52. The gate stack 52 extends on the sidewalls and top surfaces of the protruding semiconductor fin (also called fin) 44 and the dummy fin 46. A brief discussion of the paradigm formation process will be given in the following paragraphs.

According to some of the embodiments of the present invention, a dummy gate stack (not shown) is formed, and the dummy gate stack extends on the sidewalls and top surfaces of the protruding semiconductor fin 44 and the dummy fin 46. Then, gate spacers (not shown) are formed on the sidewalls of the dummy gate stack. Then, source/drain regions (not shown) are formed on both sides of the dummy gate stack and the gate spacer, for example, by etching the protruding semiconductor fin 44 that is not covered by the dummy gate stack, And epitaxy grows the source/drain regions. Then, a Contact Etch Stop Layer (CESL) 56 and an Inter-Layer Dielectric (ILD) 58 are formed to cover the source/drain regions and the dummy gate stack. Then, the dummy gate stack is etched to expose the protruding semiconductor fin 44 again. Then, a gate stack 52 including a gate dielectric 48 and a gate electrode 50 is formed in the groove left by the removed dummy gate stack.

The embodiments of the present invention have some advantageous features. The traditional shallow trench isolation formation uses flowable chemical vapor deposition. Flowable chemical vapor deposition cannot form a compliant dielectric layer and therefore cannot form dummy dielectric fins. According to some of the embodiments of the present invention, an atomic layer deposition process is used to form a carbon and nitrogen doped film, and then the film is annealed to form a silicon oxide film. Through a series of low temperature wet annealing process, high temperature wet annealing process and dry annealing process, the joints and voids produced during the atomic layer deposition process can be eliminated.

According to some of the embodiments of the present invention, a method includes etching a semiconductor substrate to form a trench; depositing a dielectric layer using an atomic layer deposition cycle, wherein the dielectric layer extends into the trench, and wherein the atomic layer deposition cycle includes Pulse hexachlorodisilane to the semiconductor substrate; blow off the hexachlorodisilane; pulse triethylamine to the semiconductor substrate; and blow off the triethylamine; and perform an annealing process on the dielectric layer. In one embodiment, the atomic layer deposition cycle further includes pulsing oxygen (O ₂ ) to the semiconductor substrate after purging triethylamine; and purging oxygen. In one embodiment, the method further includes repeating an atomic layer deposition cycle including pulsed oxygen. In one embodiment, the method further includes repeating the atomic layer deposition cycle. In one embodiment, the annealing process includes a low-temperature annealing process performed at a first temperature; a high-temperature annealing process performed at a second temperature higher than the first temperature; and performed at a third temperature higher than the first temperature The dry annealing process. In one embodiment, the low-temperature annealing process is performed at a first temperature, and the first temperature is in a range of about 300°C to about 450°C. In one embodiment, the high temperature annealing process is performed at the second temperature, and the second temperature is in the range of about 500°C to about 650°C. In one embodiment, the dry annealing process is performed at a third temperature, and the third temperature is in a range of about 500°C to about 650°C.

According to some of the embodiments of the present invention, a method includes: depositing a dielectric layer on a semiconductor strip, wherein the deposition of the dielectric layer includes a cycle, and the cycle includes: attaching silicon and chlorine atoms to the semiconductor strip Replace the chlorine atom with a nitrogen atom and an alkyl group; and replace the nitrogen atom and the first part of the alkyl group with an oxygen atom; remove the nitrogen atom and the second part of the alkyl group with an OH bond; and anneal the dielectric layer To form a Si-O-Si bond. In one embodiment, this cycle includes an atomic layer deposition (ALD) cycle, and the attachment of silicon and chlorine atoms includes pulsed hexachlorodisilane; and purging the hexachlorodisilane. In one embodiment, this cycle includes an atomic layer deposition cycle, and the substitution of chlorine atoms includes pulsed triethylamine; and purging triethylamine. In one embodiment, this cycle includes an atomic layer deposition cycle, and the replacement of the nitrogen atom and the first part of the alkyl group includes pulsed oxygen (O ₂ ); and oxygen purging. In one embodiment, the annealing of the dielectric layer includes driving H ₂ O molecules into the dielectric layer at a first temperature; and at a second temperature higher than the first temperature, replacing nitrogen atoms with oxygen atoms and OH molecules And an alkyl group; and forming a Si-O-Si bond through a dry annealing process, wherein the dry annealing process is performed at a third temperature higher than the first temperature. In one embodiment, the dielectric layer is formed in the trench, and the semiconductor strip is located on one side of the trench, and the method further includes: forming an additional dielectric region, wherein the semiconductor strip and the additional dielectric region contact the dielectric layer Etch back the part of the dielectric layer, wherein the semiconductor fin is formed on the top of the semiconductor strip, and the dummy dielectric fin is formed on the top of the additional dielectric region; and the gate is stacked on the semiconductor fin And an additional dielectric area.

According to some embodiments of the embodiments of the present invention, the integrated circuit structure includes a first semiconductor strip; a dielectric layer including silicon oxide, carbon is doped in the silicon oxide, wherein the dielectric layer includes: a horizontal portion; and a vertical portion Part is connected to one end of the horizontal part, wherein the vertical part contacts the sidewall of the lower part of the first semiconductor strip, wherein the top of the first semiconductor strip is higher than the top surface of the vertical part to form a semiconductor fin; and the gate is stacked on the semiconductor fin Extend on the side walls and the top surface. In one embodiment, the integrated circuit structure further includes a dielectric region overlapping the horizontal portion, wherein the top of the dielectric region protrudes higher than the top surface of the vertical portion to form a dummy dielectric fin, wherein the gate stack is further in the dummy The dielectric fin extends on the sidewall and top surface. In one embodiment, the dielectric region and the dielectric layer are formed of different dielectric materials. In one embodiment, the integrated circuit structure further includes an interlayer dielectric overlapping the dummy dielectric fin. In an embodiment, the vertical portion and the horizontal portion have the same thickness. In an embodiment, the integrated circuit structure further includes a second semiconductor strip; and an additional dielectric layer, wherein the additional dielectric layer is formed of the same homogeneous dielectric material as the dielectric material of the dielectric layer, and wherein the additional There are no seams in the dielectric layer.

According to some of the embodiments of the present invention, a method includes forming a first semiconductor strip; depositing a dielectric layer including silicon oxide, carbon doping in the silicon oxide, wherein the dielectric layer includes: a horizontal portion; and a vertical Part is connected to one end of the horizontal part, wherein the vertical part contacts the sidewall of the lower part of the first semiconductor strip, wherein the top of the first semiconductor strip protrudes higher than the top surface of the vertical part to form a semiconductor fin; and forming a gate stack on the semiconductor fin The sidewalls and top surface of the sheet extend. In one embodiment, the method further includes forming a dielectric region overlapping with the horizontal portion, wherein the top of the dielectric region protrudes higher than the top surface of the vertical portion to form a dummy dielectric fin, wherein the gate stack is further in the dummy dielectric The electric fins extend on the side walls and top surface. In one embodiment, the dielectric region and the dielectric layer are formed of different dielectric materials. In one embodiment, the method further includes depositing an interlayer dielectric that overlaps the dummy dielectric fin. In one embodiment, the deposition of the dielectric layer uses a compliant deposition process. In one embodiment, the method further includes: after the dielectric layer is deposited and before the gate stack is formed: performing a low temperature wet annealing process at a first temperature; after the low temperature wet annealing process, the temperature is higher than the first temperature. The high temperature wet annealing process is performed at the second temperature of the temperature; and after the high temperature wet annealing process, the dry annealing process is performed at a third temperature higher than the first temperature.

The components of several embodiments are summarized above, so that those with ordinary knowledge in the technical field to which the invention belongs can better understand the aspects of the embodiments of the invention. Those with ordinary knowledge in the technical field of the invention should understand that they can design or modify other manufacturing processes and structures based on the embodiments of the present invention to achieve the same purposes and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field of the invention should also understand that such equivalent structures do not depart from the spirit and scope of the embodiments of the present invention, and they can do so without departing from the spirit and scope of the embodiments of the present invention. Various changes, replacements and adjustments.

10: Wafer 20: Base 22: Well area 26: Semiconductor strip 28: pad oxide layer 30: Hard mask layer 32: groove 32A: Narrow groove 32B: Wide groove 34, 40: Dielectric layer 34A: Top surface 36: Interface 38: gap 42: Shallow trench isolation area 44: Fins 46: Dummy Fin 48: gate dielectric 50: gate electrode 52: gate stack 54: fin field effect transistor 56: Contact etch stop layer 58: Interlayer dielectric 110: substrate layer 112,114,116,118: structure 130,132,134,202,204,206,208,210,212,214,216,218,220,222,224: process 136,138: Atomic Layer Deposition Cycle 200: Process flow 310,312,314,316: Numerical value 318,320: line D1, D2: depth T1, T2: thickness W1, W2: width

The content of the embodiments of the present invention can be better understood through the following detailed description in conjunction with the accompanying drawings. It should be emphasized that according to industry standard practice, many features are not drawn to scale. In fact, in order to be able to discuss clearly, the size of various components may be arbitrarily increased or decreased. FIGS. 1, 2A, 2B, and 3 to 9 are schematic cross-sectional views of the intermediate stages of forming Shallow Trench Isolation (STI) regions and FinFETs according to some embodiments. FIG. 10 illustrates an Atomic Layer Deposition (ALD) cycle for forming a SiNOCH film according to some embodiments. 11A and 11B respectively illustrate the chemical structure and symbol of hexachlorodisilane and triethylamine according to some embodiments. Figure 12 shows a schematic chemical structure of a SiNOCH film according to some embodiments. Figure 13 schematically illustrates a seam separating two parts of a SiNOCH film according to some embodiments. FIG. 14 illustrates a schematic chemical structure of the SiNOCH film after the wet annealing process is performed according to some embodiments. Figures 15 and 16 schematically illustrate the keys at the seams after the low-temperature wet annealing process and the high-temperature wet annealing process, respectively, according to some embodiments. FIG. 17 illustrates a schematic chemical structure of silicon oxide after a dry annealing process according to some embodiments. Figure 18 schematically illustrates the cross-linking at the seam according to some embodiments. Figure 19 illustrates the effect of converting Si-C-N bonds into Si-OH bonds through a low-temperature wet annealing process according to some embodiments. FIG. 20 illustrates the variation of carbon concentration with depth when different low temperatures are used in the wet annealing process according to some embodiments. Figure 21 illustrates the effects of wet annealing conditions on the nitrogen concentration, carbon concentration and expansion rate of the deposited dielectric film according to some embodiments. FIG. 22 illustrates a process flow for forming shallow trench isolation regions and fin field effect transistors according to some embodiments.

200: Process flow

202,204,206,208,210,212,214,216,218,220,222,224: process

Claims (20)

A method for manufacturing a semiconductor device includes: Etching a semiconductor substrate to form a trench; A dielectric layer is deposited using an atomic layer deposition cycle, wherein the dielectric layer extends into the trench, and wherein the atomic layer deposition cycle includes: Pulse hexachlorodisilane to the semiconductor substrate; Blow off the hexachlorodisilane; Pulse triethylamine to the semiconductor substrate; and Blow off the triethylamine; and An annealing process is performed on the dielectric layer. According to claim 1, the method for manufacturing a semiconductor device, wherein the atomic layer deposition cycle further includes: After blowing off the triethylamine, pulse oxygen to the semiconductor substrate; and Blow out the oxygen. According to claim 2, the method for manufacturing a semiconductor device further includes repeating the atomic layer deposition cycle including pulsed oxygen. According to claim 1, the method for manufacturing a semiconductor device further includes repeating the atomic layer deposition cycle. According to claim 1, the method of manufacturing a semiconductor device, wherein the annealing process includes: A low temperature annealing process performed at a first temperature; A high temperature annealing process performed at a second temperature higher than the first temperature; and A dry annealing process performed at a third temperature higher than the first temperature. The method for manufacturing a semiconductor device according to claim 5, wherein the low-temperature annealing process is performed at the first temperature, and the first temperature is in a range of about 300°C to about 450°C. The method for manufacturing a semiconductor device according to claim 5, wherein the high temperature annealing process is performed at the second temperature, and the second temperature is in a range of about 500°C to about 650°C. The method for manufacturing a semiconductor device according to claim 5, wherein the dry annealing process is performed at the third temperature, and the third temperature is in the range of about 500°C to about 650°C. A method for manufacturing a semiconductor device includes: A dielectric layer is deposited on a semiconductor strip, wherein the deposition of the dielectric layer includes a cycle, and the cycle includes: Attach silicon and chlorine atoms to the oxygen atoms on the semiconductor strip; Replace the chlorine atom with a nitrogen atom and an alkyl group; and Substituting oxygen atoms for the first part of the nitrogen atom and the alkyl group; Use an OH bond to remove the nitrogen atom and the second part of the alkyl group; and The dielectric layer is annealed to form Si-O-Si bonds. The method for manufacturing a semiconductor device according to claim 9, wherein the cycle includes an atomic layer deposition cycle, and the attachment of silicon and chlorine atoms includes: Pulsed hexachlorodisilane; and Blow off the hexachlorodisilane. The method for manufacturing a semiconductor device according to claim 9, wherein the cycle includes an atomic layer deposition cycle, and the substitution of the chlorine atom includes: Pulsed triethylamine; and Blow off the triethylamine. The method of manufacturing a semiconductor device according to claim 9, wherein the cycle includes an atomic layer deposition cycle, and the substitution of the first part of the nitrogen atom and the alkyl group includes: Pulse oxygen; and Blow out the oxygen. The method of manufacturing a semiconductor device according to claim 9, wherein the annealing of the dielectric layer comprises: driving H ₂ O molecules into the dielectric layer at a first temperature; and at a second temperature higher than the first temperature At a temperature, replacing the nitrogen atom and alkyl group with oxygen atoms and OH molecules; and forming the Si-O-Si bond through a dry annealing process, wherein the dry annealing process is at a third temperature higher than the first temperature Under. According to claim 9, the method of manufacturing a semiconductor device, wherein the dielectric layer is formed in a trench, the semiconductor strip is located on one side of the trench, and the method further includes: Forming an additional dielectric region, wherein the semiconductor strip and the additional dielectric region contact two sidewalls of a part of the dielectric layer; Etching back the portion of the dielectric layer, wherein a semiconductor fin is formed on the top of the semiconductor strip, and a dummy dielectric fin is formed on the top of the additional dielectric region; and A gate stack is formed to extend over the semiconductor fin and the additional dielectric region. A method for manufacturing a semiconductor device includes: Forming a first semiconductor strip; A dielectric layer including silicon oxide is deposited, and carbon is doped in the silicon oxide, wherein the dielectric layer includes: A horizontal part; and A vertical portion is connected to one end of the horizontal portion, wherein the vertical portion contacts the sidewall of the lower portion of the first semiconductor strip, wherein the top of the first semiconductor strip protrudes higher than the top surface of the vertical portion to form a semiconductor fin; as well as A gate stack is formed to extend on the sidewall and top surface of the semiconductor fin. For example, the manufacturing method of the semiconductor device of claim 15, further including: Forming a dielectric region overlapping with the horizontal portion, wherein the top of the dielectric region protrudes higher than the top surface of the vertical portion to form a dummy dielectric fin, wherein the gate stack is further on the dummy dielectric fin The sidewalls and top surface of the sheet extend. The method of manufacturing a semiconductor device according to claim 16, wherein the dielectric region and the dielectric layer are formed of different dielectric materials. According to claim 16, the method for manufacturing a semiconductor device further includes depositing an interlayer dielectric that overlaps the dummy dielectric fin. The method for manufacturing a semiconductor device according to claim 15, wherein the deposition of the dielectric layer uses a compliant deposition process. According to claim 15, the method for manufacturing a semiconductor device further includes after depositing the dielectric layer and before forming the gate stack: Performing a low temperature wet annealing process at a first temperature; After the low temperature wet annealing process, performing a high temperature wet annealing process at a second temperature higher than the first temperature; and After the high temperature wet annealing process, a dry annealing process is performed at a third temperature higher than the first temperature.

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