CN106847751A - The forming method of fin formula field effect transistor - Google Patents
The forming method of fin formula field effect transistor Download PDFInfo
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- CN106847751A CN106847751A CN201510887996.7A CN201510887996A CN106847751A CN 106847751 A CN106847751 A CN 106847751A CN 201510887996 A CN201510887996 A CN 201510887996A CN 106847751 A CN106847751 A CN 106847751A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
A kind of forming method of fin formula field effect transistor, including：Offer includes the substrate of first area and second area, and the surface of substrate has fin；The top surface of the surface less than fin of sacrifice layer, the partial sidewall of sacrifice layer covering fin, and sacrifice layer is formed in substrate surface；The sidewall surfaces in fin form the first barrier layer afterwards；Afterwards, sacrifice layer is removed；Afterwards, the top surface of the fin in first area exposes sidewall surfaces, the first barrier layer surface and fin is formed has first kind ion in doped layer, doped layer；Technique is doped to the side wall that the fin of second area exposes afterwards, the ion of doping process doping is Second Type ion；Annealing process is carried out afterwards, drives first kind ion doping to enter the fin of first area, drive Second Type ion doping to enter the fin of second area；The first barrier layer and doped layer are removed afterwards.The performance improvement of the semiconductor structure for being formed.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of shape of fin formula field effect transistor
Into method.
Background technology
With developing rapidly for semiconductor fabrication, semiconductor devices towards component density higher, with
And the direction of integrated level higher is developed.Transistor is just extensive at present as most basic semiconductor devices
Using, thus the component density and integrated level with semiconductor devices raising, the grid of planar transistor
Size is also shorter and shorter, and traditional planar transistor dies down to the control ability of channel current, produces short ditch
Channel effect, produces leakage current, the electric property of final influence semiconductor devices.
In order to overcome the short-channel effect of transistor, suppress leakage current, prior art proposes fin effect
Transistor (Fin FET) is answered, fin formula field effect transistor is a kind of common multi-gate device.Fin effect
Answering the structure of transistor includes：Positioned at the fin and dielectric layer of semiconductor substrate surface, the dielectric layer covers
The side wall of fin described in cover, and dielectric layer surface is less than fin top；Positioned at dielectric layer surface, with
And top and the grid structure of sidewall surfaces of fin；Source in the fin of the grid structure both sides
Area and drain region.
However, as the size of semiconductor devices constantly reduces, the manufacturing process of fin formula field effect transistor
It is challenged, it is difficult to ensure the stable performance of fin formula field effect transistor.
The content of the invention
The problem that the present invention is solved is to provide a kind of forming method of fin formula field effect transistor, the half of formation
The performance improvement of conductor structure.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, including：
Substrate is provided, the substrate includes first area and second area, the first area of the substrate and second
Region surface has fin respectively；Sacrifice layer is formed in the substrate surface, the sacrifice layer covering is described
The partial sidewall of fin, and the sacrifice layer surface less than the fin top surface；Forming institute
State after sacrifice layer, the first barrier layer is formed in the sidewall surfaces of the fin；Forming first resistance
After barrier, the sacrifice layer is removed；After the sacrifice layer is removed, the fin in first area is sudden and violent
The top surface of the sidewall surfaces, the first barrier layer surface and fin exposed forms doped layer, described to mix
There is first kind ion in diamicton；After the sacrifice layer is removed, the fin exposure to second area
The side wall for going out is doped technique, and the ion of the doping process doping is Second Type ion；Formed
Doped layer is simultaneously doped after technique to second area fin, carries out annealing process, drives the first kind
Ion doping enters the fin of first area, drives Second Type ion doping to enter the fin of second area；
After the annealing process, first barrier layer and doped layer are removed.
Optionally, there is the first well region in the fin and substrate of the first area, in first well region
With first kind ion；There is the second well region, described second in the fin and substrate of the second area
There is Second Type ion in well region.
Optionally, the forming step of the doped layer includes：The substrate surface and fin side wall and
Top surface forms doping；The first mask layer is formed on the doping of the first area；With described
First mask layer is mask, the etching removal doping, until exposing the part side of substrate, fin
Untill wall surface and the first barrier layer surface, the doped layer is formed in first area.
Optionally, also include：The second barrier layer is formed in the doping layer surface.
Optionally, the material on second barrier layer is silicon nitride.
Optionally, the material on first barrier layer is silicon nitride.
Optionally, it is isotropic etc. that technique is doped to the side wall that the fin of second area exposes
Gas ions doping process.
Optionally, the parameter of isotropic plasma doping process includes：Process gas includes
Doped source gas and inert gas, the flow of the doped source gas is 1sccm~50sccm, inert gas
Flow be 1sccm~50sccm, process atmospheric pressures are less than or equal to 1mTorr, and plasma source power is
100W~500W, bias power is less than or equal to 1W.
Optionally, also include：Before the sacrifice layer is formed, formed in the substrate and fin portion surface
Boundary layer；The sacrifice layer is formed at the interface layer surfaces；After the sacrifice layer is removed, formed
Before doped layer, the boundary layer that removal exposes.
Optionally, the forming step of the sacrifice layer includes：Formed in the substrate and fin portion surface and sacrificed
Film, the top of the surface higher than fin of the expendable film；Planarize the expendable film；It is described in planarization
After expendable film, the expendable film is etched back to, forms surface less than the sacrifice layer at the top of fin.
Optionally, the material of the sacrifice layer is bottom antireflection material or organic dielectric material.
Optionally, the forming step on first barrier layer includes：In the sacrificial layer surface and fin
The side wall and top surface in portion form the first barrier film；First barrier film is etched back to until exposing sacrificial
Domestic animal layer and fin top surface, form first barrier layer.
Optionally, the annealing process is spike annealing or rapid thermal annealing；The temperature of the annealing process
It it is 1000 DEG C~1100 DEG C, the time is 3 seconds~8 seconds.
Optionally, the top surface of the fin has the second mask layer；Removing first barrier layer
After doped layer, second mask layer is removed.
Optionally, the forming step of the substrate and fin includes：Semiconductor base is provided；Described half
The part surface of conductor substrate forms the second mask layer；With second mask layer as mask, etching is described
Semiconductor base, forms the substrate and fin.
Optionally, also include：After first barrier layer and doped layer is removed, in the substrate table
Face forms dielectric layer, and the dielectric layer covers the partial sidewall surface of the fin, and the dielectric layer table
Top surface of the face less than the fin.
Optionally, also include：After the dielectric layer is formed, the grid knot of the fin is developed across
Structure, the grid structure covers the partial sidewall and top surface of the fin；In the grid structure two
Source region and drain region are formed in the fin of side.
Optionally, the first kind ion is N-type ion；The Second Type ion is p-type ion.
Compared with prior art, technical scheme has advantages below：
In forming method of the invention, after sacrifice layer is formed, the is formed in the fin side wall for exposing
One barrier layer, after the sacrifice layer is removed, the doped layer for being formed can cover and once be sacrificed layer and cover
The first area fin side wall of lid, subsequently by annealing process after, the first kind in the doped layer
Ion can spread in the fin side wall for being contacted, therefore, it is possible to remove doping after by annealing
Layer so that the groove depth-to-width ratio increase between adjacent fin, is conducive to the follow-up lining between adjacent fin
Basal surface forms the dielectric layer of dense uniform.Secondly as first barrier layer exposes second area
Once the fin side wall of layer covering was sacrificed, then second area can be exposed by doping process directly
Fin wall doping Second Type ion, without being additionally formed the doped layer comprising Second Type ion with right
Second area fin is doped, therefore allows adjacent fin spacing from further diminution, thus improves device
Part density.Being additionally, since need not be additionally formed the doped layer comprising Second Type ion for the secondth area
Domain fin is doped, additionally it is possible to reduces by a photoetching process such that it is able to Simplified flowsheet step, and saves
Save process costs.
Brief description of the drawings
Fig. 1 to Fig. 4 is a kind of cross-sectional view of the forming process of semiconductor structure；
Fig. 5 to Figure 13 is the cross-section structure of the forming process of the fin formula field effect transistor of the embodiment of the present invention
Schematic diagram.
Specific embodiment
As stated in the Background Art, as the size of semiconductor devices constantly reduces, fin formula field effect transistor
Manufacturing process it is challenged, it is difficult to ensure the stable performance of fin formula field effect transistor.
Found by research, constantly reduced with for forming the fin size of fin formula field effect transistor,
The source region and drain region bottom being formed in fin are susceptible to bottom break-through (punch through) phenomenon, i.e.,
There is break-through between the source region and the bottom in drain region, leakage current is produced in the bottom in the source region and drain region.
In order to overcome the bottom punch through, a kind of method is that anti-break-through injection is carried out in fin, described
Transoid ion is injected in region between source region and drain region bottom, to isolate source region and drain region bottom.However,
Due in larger distance at the top of source region and drain region bottom to fin, then the depth of the anti-break-through injection also compared with
Greatly so that the anti-break-through injection easily causes implant damage to fin portion surface and inside, can still reduce
The performance of fin formula field effect transistor.
For the implant damage problem for overcoming above-mentioned anti-break-through injection to cause, Fig. 1 to Fig. 4 is that one kind is partly led
The cross-sectional view of the forming process of body structure.
Refer to Fig. 1, there is provided substrate 100, the surface of the substrate 100 has fin 101, the substrate
100 and the surface of fin 101 there is doping 102, there are Doped ions in the doping 102.
Fig. 2 is refer to, deielectric-coating 103 is formed on the surface of the doping 102.
Fig. 3 is refer to, the deielectric-coating 103 (as shown in Figure 2) is etched back to form dielectric layer 103a,
Top surface of the dielectric layer 103a surfaces less than the fin 101.
Fig. 4 is refer to, removal is higher than the doping 102 (as shown in Figure 3) on dielectric layer 103a surfaces, shape
Into doped layer 102a；Annealing process is carried out, the Doped ions in doped layer 102a is diffused into fin 101
It is interior.
However, as the density of semiconductor devices is improved so that the groove dimensions between adjacent fin 101
It is corresponding to reduce, accordingly increase the groove depth-to-width ratio between adjacent fin 101.Due to the substrate 100
Deielectric-coating 103 is re-formed after forming doping with the surface of fin 101, then the meeting of doping 102 for being formed
Further increase the depth-to-width ratio of groove, cause subsequently to be difficult to fill the deielectric-coating of dense uniform in groove
103.Secondly as the groove depth-to-width ratio between the adjacent fin 101 of the fin is larger, easily make described
Doping 102 itself is the sidewall surfaces for being difficult to closely fit in the surface of substrate 100 and fin 101,
Especially the corner on the side wall of fin 101 and the surface of substrate 100 is difficult to be brought into close contact doping 102.
In order to solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, bag
Include：There is provided substrate, the substrate include first area and second area, the first area of the substrate and
Second area surface has fin respectively；Sacrifice layer, the sacrifice layer covering are formed in the substrate surface
The partial sidewall of the fin, and the sacrifice layer surface less than the fin top surface；In shape
Into after the sacrifice layer, the first barrier layer is formed in the sidewall surfaces of the fin；Forming described the
After one barrier layer, the sacrifice layer is removed；After the sacrifice layer is removed, in the fin of first area
The top surface of sidewall surfaces, the first barrier layer surface and fin that portion exposes forms doped layer, institute
Stating has first kind ion in doped layer；After the sacrifice layer is removed, to the fin of second area
The side wall for exposing is doped technique, and the ion of the doping process doping is Second Type ion；
Form doped layer and second area fin is doped after technique, carry out annealing process, drive first
Types of ion is doped into the fin of first area, drives Second Type ion doping to enter the fin of second area；
After the annealing process, first barrier layer and doped layer are removed.
Wherein, the first barrier layer is formed in the fin side wall for exposing after sacrifice layer is formed, in removal
After the sacrifice layer, the doped layer for being formed can cover the first area fin for being once sacrificed layer covering
Side wall, subsequently by annealing process after, first kind ion in the doped layer can be to being contacted
Fin side wall in diffusion, therefore, it is possible to by annealing after remove doped layer so that adjacent fin
Between the increase of groove depth-to-width ratio, be conducive to subsequently substrate surface between adjacent fin formed it is fine and close
Even dielectric layer.Secondly as first barrier layer exposes second area was once sacrificed layer covering
Fin side wall, then the fin wall doping second that directly can be exposed to second area by doping process
Types of ion, is carried out without being additionally formed the doped layer comprising Second Type ion with to second area fin
Doping, therefore allow adjacent fin spacing from further diminution, thus improve device density.And, by
It is used to be doped second area fin in the doped layer comprising Second Type ion need not be additionally formed,
Can also reduce by a photoetching process such that it is able to Simplified flowsheet step, and save process costs.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
Specific embodiment of the invention is described in detail.
Fig. 5 to Figure 13 is the cross-section structure of the forming process of the fin formula field effect transistor of the embodiment of the present invention
Schematic diagram.
Refer to Fig. 5, there is provided substrate 200, the substrate 200 includes first area 210 and second area
220, the first area 210 and the surface of second area 220 of the substrate have fin 201 respectively.
The surface of substrate 200 of the first area 210 has one or more fins 201 respectively；Described
The surface of substrate 200 in two regions 220 has one or more fins 201 respectively.In the present embodiment,
The distance between adjacent fin 201 is less than or equal to 50 nanometers in one region 210 or second area 220.
In the present embodiment, the first area 210 is used to form PMOS transistor；Secondth area
Domain 220 is used to form nmos pass transistor.In other embodiments, the first area 210 is used for shape
Into nmos pass transistor, the second area 220 is used to form PMOS transistor.
In the present embodiment, also have first in the fin 201 and substrate 200 of the first area 210
There is first kind ion in well region, first well region；The He of fin 201 of the second area 220
Also having in substrate 200 has Second Type ion in second well region, second well region.Wherein, institute
First kind ion is stated for N-type ion；The Second Type ion is p-type ion.
The follow-up anti-break-through ion being doped into the fin 201 of first area 210 is N-type ion, doping
It is p-type ion to enter the anti-break-through ion in the fin 201 of second area 220；The anti-break-through ion phase
For being subsequently formed in the Doped ions transoid in the source region and drain region in fin 201, source region is avoided with this
There is break-through and the bottom in drain region between.
In the present embodiment, the top surface of the fin 201 also has the second mask layer 203, described the
Two mask layers 203 form the mask of fin 201 as etching, and second mask layer 203 can also
Enough during subsequent technique, the top surface for protecting fin 201.In other embodiments, institute
The top surface for stating fin 201 can also not have the second mask layer 203.
In the present embodiment, the fin 201 and substrate 200 are formed by etching semiconductor substrate.Institute
The forming step for stating fin 201 includes：Semiconductor base is provided；In the part table of the semiconductor base
Face forms mask layer 202；With the mask layer 202 as mask, the semiconductor base is etched, form institute
State substrate 200 and the fin 201 positioned at the surface of substrate 200.The semiconductor base is silicon substrate, germanium
Substrate and silicon-Germanium substrate.In the present embodiment, the semiconductor base is monocrystalline substrate, i.e., described fin
The material of portion 201 and substrate 200 is monocrystalline silicon.
The forming step of the substrate 200 and fin 201 includes：Semiconductor base is provided；Described half
The part surface of conductor substrate forms the second mask layer 203；With second mask layer 203 as mask, carve
The semiconductor base is lost, the substrate 200 and fin 201 is formed.
In the present embodiment, first well region and the second well region shape before the semiconductor base is etched
Into.In another embodiment, first well region and the second well region are forming the substrate 200 and fin
After 201, formed using ion implantation technology.
The forming step of second mask layer 203 includes：Mask is formed in the semiconductor substrate surface
Material membrane；Patterned layer is formed on the mask material film surface；Described in patterned layer as mask etching
Mask material film forms second mask layer 203 untill semiconductor substrate surface is exposed.
In one embodiment, the patterned layer is patterned photoresist layer, and the patterned layer is used
Coating process and photoetching process are formed.In another embodiment, in order to reduce the feature of the fin 201
The distance between size and adjacent fin 201, the patterned layer use multiple graphical mask work
Skill is formed.The multiple graphical masking process includes：Self-alignment duplex pattern (Self-aligned
Double Patterned, SaDP) technique, autoregistration be triple graphical (Self-aligned Triple Patterned)
Technique or autoregistration quadruple are graphical (Self-aligned Double Double Patterned, SaDDP)
Technique.
In one embodiment, the formation process of the patterned layer is self-alignment duplex pattern chemical industry skill, bag
Include：In mask material film surface deposited sacrificial film；Patterned photoresist is formed on the expendable film surface
Layer；With the photoresist layer as mask, etch the expendable film is up to exposing mask material film surface
Only, sacrifice layer is formed, and removes photoresist layer；It is graphical in mask material film and sacrificial layer surface deposition
Film；The graphic film is etched back to untill sacrifice layer and mask material film surface is exposed, is being sacrificed
The semiconductor substrate surface of layer both sides forms patterned layer；It is described be etched back to technique after, removal is described
Sacrifice layer.
The technique for etching the semiconductor base is anisotropic dry etch process.The fin 201
Side wall it is vertical relative to the surface of substrate 200 or incline, and when the fin 201 side wall relative to
When the surface of substrate 200 inclines, the bottom size of the fin 201 is more than top dimension.In the present embodiment
In, the side wall of the fin 201 is inclined relative to the surface of substrate 200.
In another embodiment, the fin is formed by the semiconductor layer that etching is formed at substrate surface；
The semiconductor layer is formed at the substrate surface using selective epitaxial depositing operation.The substrate is silicon
Substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, germanium substrate on insulator, glass lined
Bottom or III-V substrate, such as gallium nitride substrate or gallium arsenide substrate etc.；The semiconductor layer
Material is silicon, germanium, carborundum or SiGe.The selection of the substrate and semiconductor layer is unrestricted, energy
Enough selection is suitable to process requirements or the substrate that is easily integrated and is suitable to the material of fin.And, it is described
The thickness of semiconductor layer can be controlled by epitaxy technique, so that the fin that is formed of precise control
Highly.
In the present embodiment, also include：Boundary layer 202 is formed in the substrate 200 and the surface of fin 201.
The material of the boundary layer 202 is silica；The formation process of the boundary layer 202 is oxidation technology；
The thickness of the boundary layer 202 is 5 nanometers~50 nanometers.The oxidation technology is generated including situ steam
(In-Situ Steam Generation, abbreviation ISSG) technique, decoupled plasma oxidation (Decoupled
Plasma Oxidation, abbreviation DPO) technique, free-radical oxidation (Radical Oxidation) technique or
Wet process oxidation technology.
In one embodiment, the formation process of the boundary layer 202 is situ steam generation technique.It is described
The parameter of situ steam generation technique includes：Temperature is 700 DEG C~1200 DEG C, and gas includes hydrogen and oxygen,
Oxygen flow is 1slm~50slm, and hydrogen flowing quantity is 1slm~10slm, and the time is 20 seconds~10 minutes.
The boundary layer 202 that the situ steam generation technique is formed has good gradient coating performance, can make
The boundary layer 202 for being formed closely is covered in the sidewall surfaces of fin 201, and the interface for being formed
The thickness of layer 202 is uniform.
By forming the boundary layer 202, the substrate 200 and the surface of fin 201 can be repaired in preamble
What is be subject to during etching technics and ion implantation technology damages.And, the boundary layer 202 can also
At follow-up removal sacrifice layer or the first barrier layer, the surface for protecting fin 201 and substrate 200.
In the present embodiment, the side wall and top surface of second mask layer 203 also form the boundary layer 202.
Fig. 6 is refer to, sacrifice layer 204 is formed on the surface of the substrate 200, the sacrifice layer 204 is covered
The partial sidewall of the fin 201, and the sacrifice layer 204 surface less than the fin 201 top
Portion surface.
The sacrifice layer 204 is used to defining the side wall of the fin 201 to be needed to adulterate the region of anti-break-through ion.
In the present embodiment, it is described sacrificial because the substrate 200 and the surface of fin 201 also have boundary layer 202
Domestic animal layer 204 is formed at the surface of the boundary layer 202.
The forming step of the sacrifice layer 204 includes：Formed in the substrate 200 and the surface of fin 201
Expendable film, the top of the surface higher than fin 201 of the expendable film；Planarize the expendable film；Flat
After the smoothization expendable film, the expendable film is etched back to, forms surface sacrificial less than the top of fin 201
Domestic animal layer 204.
In the present embodiment, the material of the sacrifice layer 204 is bottom antireflection (Back Anti-Reflection
Coating, abbreviation BARC) material or organic media (ODL) material.The bottom antireflection material
Or organic dielectric material can be formed at substrate using coating process (such as spin coating proceeding or spraying coating process)
200 and the surface of fin 201, and easily enter the groove between adjacent fin 201.Due to the sacrifice
Film is formed using coating process, and the expendable film surface for being formed can not keep flat, and the expendable film
The lowest part on surface needs higher than or is flush to the top surface of second mask layer 203.
Need to remove the sacrifice layer 204 secondly as follow-up, and the bottom antireflection material or organic
Dielectric material is easy to be removed, and is difficult remaining bi-products after removal.
The flatening process is CMP process (CMP)；In the chemically mechanical polishing work
In skill, can be using the top surface of the second mask layer 203 as polishing stop position, described second covers
Film layer 203 can protect the top of the fin 201.It is described be etched back to (etch back) technique for it is each to
The dry etch process of the opposite sex；Technique is etched back to described, the boundary layer 202 can be protected described
The sidewall surfaces of fin 201, and the sacrifice layer for being formed exposed positioned at the partial sidewall surface of fin 201
Boundary layer 202.
Fig. 7 is refer to, after the sacrifice layer 204 is formed, in the sidewall surfaces shape of the fin 201
Into the first barrier layer 205.
Higher than the surface of sacrifice layer 204, first barrier layer 205 is used on the first barrier layer 205 for being formed
In protecting the sidewall surfaces of the fin 201 near top so that follow-up to be formed in first area 210
Doped layer can be doped in the side wall of the bottom of fin 201, and follow-up to second area 220
Side wall of the fin 201 near bottom be doped such that it is able in the fin 201 of first area 210
Anti- punch through region is formed in interior and second area 220 fin 201.
The material on first barrier layer 205 is the one kind or many in silicon nitride, silica or silicon oxynitride
Kind, the material on first barrier layer 205 is required to prevent the first kind in the doped layer that is subsequently formed
Type ion spreads.In the present embodiment, the material on first barrier layer 205 is silicon nitride.
The forming step on first barrier layer 205 includes：In the surface of the sacrifice layer 204 and fin
The side wall and top surface in portion 201 form the first barrier film；First barrier film is etched back to until exposure
Go out sacrifice layer 204 and the top surface of fin 201, form first barrier layer 205.
The formation process of first barrier film includes chemical vapor deposition method, physical gas-phase deposition
Or atom layer deposition process, it is in the present embodiment atom layer deposition process.
The technique that is etched back to is for anisotropic dry etch process；The anisotropic dry etching
The parameter of technique includes：Gas includes carbon fluorine gas and carrier gas, and the carbon fluorine gas include CF4、CHF3、
CH2F2、CH3F, the carrier gas is inert gas, and such as He, gas flow is 50sccm~1000
Sccm, pressure is 2 millitorr~10 millitorrs, 150 watts~800 watts of bias power.
Because the etching direction of the anisotropic dry etch process is perpendicular to the surface of substrate 200, position
It is parallel with etching direction or smaller with the angle in etching direction in the first barrier film of the sidewall surfaces of fin 201,
The first barrier film therefore in the sidewall surfaces of fin 201 will not be etched by etching gas, and in institute
State retained, formation first barrier layer 205 in etching technics.
Fig. 8 is refer to, after first barrier layer 205 is formed, the sacrifice layer 204 is removed (such as
Shown in Fig. 7).
The technique for removing the sacrifice layer 204 is dry etch process, wet-etching technology or cineration technics；
Wherein, the dry etch process can be anisotropic dry etch process or isotropic dry method
Etching technics.In the present embodiment, the technique for removing the sacrifice layer 204 is wet-etching technology.
In the present embodiment, after the sacrifice layer 204 is removed, the interface for also being exposed including removal
Layer 202, the fin of the surface of substrate 200 and first area 210 and second area 220 is exposed with this
201 near bottom sidewall surfaces, wall doping that subsequently can be to the fin 201 near bottom is anti-to be worn
Logical ion.
The technique of the boundary layer 202 exposed described in removal is isotropic dry etch process or wet method
Etching technics.In the present embodiment, the technique of the boundary layer 202 for being exposed described in removal is SICONI
Technique；The parameter of the SICONI techniques includes：Power 10W~100W, frequency is less than 100kHz,
Etching temperature is 40 degrees Celsius~80 degrees Celsius, and pressure is 0.5 support~50 support, and etching gas include NH3、
NF3, He, wherein, NH3Flow be 0sccm~500sccm, NF3Flow be 20sccm~200sccm,
The flow of He is 400sccm~1200sccm, NF3With NH3Flow-rate ratio be 1:20~5:1.
SICONI techniques etch rate in all directions is uniform, it is easy to go deep into adjacent fin 201
Between perform etching, even if the groove depth-to-width ratio between adjacent fin 201 is larger, it is also possible to after making etching
Forerunner's dielectric layer surface of formation is flat.And, when being performed etching using SICONI techniques, to the lining
The sidewall surfaces of the surface of bottom 200 and fin 201 damage smaller, are conducive to reducing in formed device
Leakage current.
Fig. 9 is refer to, after the sacrifice layer 204 (as shown in Figure 7) is removed, in first area 210
The top table of sidewall surfaces, the surface of the first barrier layer 205 and fin 201 that exposes of fin 201
Face is formed has first kind ion in doped layer 206, the doped layer 206.
First kind ion in the doped layer 206 is used for as the anti-break-through ion of first area 210,
After the first kind ion in doped layer 206 is diffused into fin 201 subsequently through annealing process,
Anti- reach through region can be formed in the fin 201 of first area 210.Described first is additionally, since to stop
, higher than the side wall of sacrifice layer 204, the doped layer 206 can be with institute for the covering of layer 205 fin 201
Side wall of the fin 201 near bottom is stated to be in contact, therefore the anti-reach through region for being formed is located at by the sacrifice
In the part fin 201 of the covering of layer 204, i.e., described anti-reach through region is located at the fin 201 near bottom
Region in.
The forming step of the doped layer 206 includes：In the surface of the substrate 200 and the side of fin 201
Wall and top surface form doping；The first mask layer is formed on the doping of the first area 210
207；With first mask layer 207 as mask, the etching removal doping, until exposing substrate
200th, untill the partial sidewall surface of fin 201 and the surface of the first barrier layer 205, in first area
210 form the doped layer 206.
In the present embodiment, first mask layer 207 includes patterned photoresist layer；Described first covers
Film layer 207 is formed using coating process and photoetching process.The technique for etching the doping is anisotropy
Dry etch process.
In the present embodiment, the first area 210 is used to form PMOS transistor, then and described first
Types of ion is N-type ion, and the N-type ion includes phosphonium ion or arsenic ion；It is subsequently formed in first
There is p-type ion, then the N-type ion and p-type in source region and drain region in the fin 201 of region 210
Ion transoid, then be formed at the anti-reach through region of first area 210 can suppress source region and drain region bottom because from
Son spreads and the problem of break-through (punch through) short circuit occurs.
In the present embodiment, the first kind ion in the doped layer 206 is phosphonium ion, the doping
The material of layer 206 is phosphorosilicate glass (PSG) or the non-crystalline silicon or polycrystalline silicon material of doping phosphorus.The doping
The formation process of film is chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process；
In the depositing operation, first kind ion doping can be entered in doping with doping process in situ.
First kind ion doping concentration in the doped layer 206 is 1E15atoms/cm3~1E23
atoms/cm3, the thickness of the doped layer 206 is 1 nanometer~5 nanometers.
In the present embodiment, also include：The second barrier layer 208 is formed on the surface of the doped layer 206；Institute
The material for stating the second barrier layer 208 is silicon nitride.In other embodiments, second barrier layer 208
Material can also be silica or silicon oxynitride.Second barrier layer 208 is used for subsequently to second
When region 220 is doped technique, the doped layer 206 is protected, it is to avoid follow-up doping work
Second Type ion doping is entered the doped layer by skill.
Figure 10 is refer to, after the sacrifice layer 204 (as shown in Figure 7) is removed, to second area
The side wall that 220 fin 201 exposes is doped technique, and the ion of the doping process doping is second
Types of ion.
In the present embodiment, before the doping process is carried out, first mask layer 207 is removed (such as
Shown in Fig. 9).
It is isotropic etc. that technique is doped to the side wall that the fin 201 of second area 220 exposes
Gas ions doping process.The parameter of isotropic plasma doping process includes：Process gas
Including doped source gas and inert gas, the flow of the doped source gas is 1sccm~50sccm, inertia
The flow of gas is 1sccm~50sccm, and process atmospheric pressures are less than or equal to 1mTorr, and plasma source power is
100W~500W, bias power is less than or equal to 1W.Wherein, the doped source gas includes B or B2H6,
The inert gas include He and Ar in one or two.
In the present embodiment, the second area 220 is used to form nmos pass transistor, to second area
The Second Type ion of 220 wall dopings of fin 201 for exposing is p-type ion, the p-type ion bag
Include boron ion or indium ion.In the present embodiment, the side wall of fin 201 for being exposed to second area 220
The Second Type ion of doping is boron ion.
The Second Type ion of the wall doping of fin 201 exposed to second area 220 is used as anti-break-through
After annealing process after ion, the Second Type ion warp, can be in the fin of second area 220
Anti- reach through region is formed in portion 201.The Second Type ion be subsequently formed in the fin of second area 220
Doped ions transoid in source region and drain region in 201 such that it is able to suppress source region and drain region bottom because of doping
Ion spreads and the problem of break-through short circuit occurs.
The energy of isotropic plasma doping process is relatively low so that plasma is subject to electric field
Effect it is smaller, therefore the Second Type ion can be doped on each different directions,
So as to the sidewall surfaces of fin 201 that expose Second Type ion pair second area 220 and
The surface of substrate 200 is injected.
The energy for being additionally, since isotropic plasma doping process is relatively low, the doping work
The damage of sidewall surfaces and the surface of substrate 200 that skill exposes to the fin 201 is smaller.Accordingly,
The doping process can enable Second Type ion accumulate in the sidewall surfaces exposed near fin 201
And in the region on the surface of substrate 200, therefore subsequently need to drive the Second Type by annealing process
Ion fully spreads in the fin 201 of second area 220 in the region of bottom.
In the present embodiment, the Second Type ion in the doping of the second area 220 is N-type ion boron
Ion, and N-type ion is more easy to diffusion because particle size is smaller, therefore, it is possible to described each to same
The plasma doping process of property is doped.
The second area 220 is adulterated anti-break-through ion by isotropic plasma doping process,
And doped layer 206 only is formed in first area 210, without respectively in first area 210 and second area
220 form the different doped layer of material.Even if being located in first area 210 and second area 220 respectively
The distance between adjacent fin 201 is smaller, and the depth-to-width ratio between the adjacent fin 201 is larger, due to
The material of the doped layer 206 is easy to the channel bottom goed deep between the adjacent fin 201, so as to subtract
The small formation process difficulty of the doped layer 206, therefore, it is possible to make the doped layer 206 and fin
210 side walls and the surface of substrate 200 are combined closely.
It is additionally, since and formed in first area 210 and second area 220 that material is different to be mixed without respectively
Diamicton such that it is able to the step of reducing by a photoetching process, simplifies processing step, reduces technique difficult
Degree, reduces process costs.
Figure 11 is refer to, work is doped in formation doped layer 206 and to the fin 201 of second area 220
After skill, annealing process is carried out, drives first kind ion doping to enter the fin 201 of first area 210,
Second Type ion doping is driven to enter the fin 201 of second area 220.
In the present embodiment, before the annealing process is carried out, it is additionally included in the second area 220
The surface of substrate 200, the sidewall surfaces of 220 fin of second area 201, second area 220 first resistance
The surface of barrier 205, the surface of the second barrier layer 208 of first area 210 and the table of the second mask layer 203
Face forms the 3rd barrier layer 230.
3rd barrier layer 230 is used in annealing process, prevent adulterated first kind ion or
There is loss in Second Type ion, can be spread completely with the first kind ion for ensureing adulterated to surface
Enter in the fin 201 and substrate 200 of first area 210, the Second Type ion for being adulterated can be complete
Diffuse into the fin 201 and substrate 200 of second area 220.
The annealing process is spike annealing or rapid thermal annealing；The temperature of the annealing process is 1000 DEG C
~1100 DEG C, the time is 3 seconds~8 seconds.
The annealing process is used to drive the first kind ion in the doped layer 206 to diffuse into the firstth area
In the fin 201 in domain 210, to form anti-reach through region in the fin 201 of first area 210；Meanwhile,
The annealing process accumulates in the surface of 220 substrate of second area 200 and the side wall table of fin 201 for driving
The Second Type ion in face diffuses into the fin 201 of second area 220, in the fin of the second area 220
Anti- reach through region is formed in portion 201.
Figure 12 is refer to, after the annealing process, described (such as Figure 11 of first barrier layer 205 is removed
It is shown) and doped layer 206 (as shown in figure 11).
In the present embodiment, also include：Removal boundary layer 202, the second barrier layer 208 and the 3rd barrier layer
230。
Remove the boundary layer 202, the first barrier layer 205, doped layer 206, the and of the second barrier layer 208
The technique on the 3rd barrier layer 230 is wet-etching technology or dry etch process, in the present embodiment for wet
Method etching technics.
In the present embodiment, remove the boundary layer 202, the first barrier layer 205, doped layer 206,
After second barrier layer 208 and the 3rd barrier layer 230, the groove between adjacent fin 201 can be increased
Depth-to-width ratio, when dielectric layer is subsequently formed, is conducive to the material of dielectric layer to be sufficient filling with groove, energy
Enough make formed dielectric layer dense uniform, and the dielectric layer and fin 201 and the surface of substrate 200
With reference to tightr such that it is able to reduce the leakage current of formed fin formula field effect transistor, device is improved
Yield.
Figure 13 is refer to, first barrier layer 205 (as shown in figure 11) and doped layer 206 is being removed
After (as shown in figure 11), dielectric layer 209, the dielectric layer 209 are formed on the surface of the substrate 200
The partial sidewall surface of the fin 201 is covered, and the surface of the dielectric layer 209 is less than the fin 201
Top surface.
The forming step of the dielectric layer 209 includes：In the substrate 200, the mask of fin 201 and second
203 (as shown in figure 12) surface of layer form deielectric-coating；Planarize the deielectric-coating；It is described in planarization
After deielectric-coating, the deielectric-coating is etched back to until exposing the partial sidewall of fin 201, form medium
Layer 209.
In the present embodiment, after the dielectric layer 209 is formed, second mask layer 203 is removed；
The technique for removing second mask layer 203 is dry etch process or wet-etching technology.
In the present embodiment, the material of the dielectric layer 209 is silica.The formation work of the deielectric-coating
Skill is fluid chemistry gas-phase deposition (FCVD, Flowable Chemical Vapor Deposition).
In other embodiments, the deielectric-coating can also use other chemical vapor deposition methods or physical vapor
Depositing operation is formed；Described other chemical vapor deposition methods include plasma enhanced chemical vapor deposition
Technique (PECVD) or high-aspect-ratio chemical vapor deposition method (HARP).In another embodiment,
The deielectric-coating can also using first using fluid chemistry gas-phase deposition, use high-density plasma afterwards
Deposition (High Density Plasma, abbreviation HDP) technique is formed.
In the present embodiment, the step of fluid chemistry gas-phase deposition includes：The substrate 200,
The surface of 201 and second mask layer of fin 203 forms forerunner's deielectric-coating；Annealing process is carried out, forerunner is situated between
Plasma membrane solidifies, and forms the deielectric-coating.
The material of forerunner's deielectric-coating is siliceous flowable materials；The flowable materials can be containing
One or more condensate of polymerization in Si -- H bond, Si-N keys and Si-O keys.Forerunner's deielectric-coating
Formation process parameter includes：Technological temperature is 60 DEG C~70 DEG C, is 65 DEG C in the present embodiment.
Annealing process in the fluid chemistry gas-phase deposition can be that wet method annealing process or dry method are moved back
Ignition technique；The parameter of the annealing process includes：Temperature is less than or equal to 600 DEG C, and anneal gas include
H2、O2、N2, one or more combination in Ar and He, annealing time is 5 seconds~1 minute.Wherein,
When anneal gas include H2And O2When, the annealing process is wet method annealing process.
The flatening process is CMP process (CMP)；In the present embodiment, describedization
Mechanical polishing process is learned using second mask layer 203 as stop-layer.
The technique for being etched back to the deielectric-coating is isotropic dry etch process, anisotropic dry method
Etching technics or wet-etching technology.In the present embodiment, the technique that is etched back to is done for isotropic
Method etching technics；Isotropic dry etch process is SiCoNi techniques.
SiCoNi techniques etch rate in all directions is uniform, it is easy to go deep into adjacent fin 201
Between perform etching, even if the groove depth-to-width ratio between adjacent fin 201 is larger, it is also possible to after making etching
The surface of dielectric layer 209 of formation is flat.
In the present embodiment, after the dielectric layer 209 is formed, it is developed across the fin 201
Grid structure, the grid structure covers the partial sidewall and top surface of the fin 201；Described
Source region and drain region are formed in the fin 201 of grid structure both sides.
The grid structure includes：Positioned at the pseudo- gate oxide on the surface of fin 201 and positioned at pseudo- grid oxygen
Change the dummy gate layer of layer and insulation surface.The material of the pseudo- gate oxide is silica, formation process
It is thermal oxidation technology or situ steam generation (ISSG) technique；The material of the dummy gate layer is polysilicon,
Formation process includes chemical vapor deposition method and CMP process.
The grid structure can also include being located at the side wall of pseudo- gate oxide and dummy gate layer sidewall surfaces.
The material of the side wall is one or more combination in silica, silicon nitride, silicon oxynitride.The side
Wall is used to define the relative position between source region and drain region and dummy gate layer.
In one embodiment, the forming step in the source region and drain region includes：In the grid structure both sides
Fin 201 in formed opening；Stressor layers are formed in the opening using selective epitaxial depositing operation；
Doped p-type ion or N-type ion in the stressor layers.The material of the stressor layers is carborundum or silicon
Germanium.
After source region and drain region is formed, also include：In the dielectric layer 209 and the surface shape of fin 201
Into interlayer dielectric layer, the interlayer dielectric layer covers the side wall of the grid structure, and the gate dielectric layer
Expose the dummy gate layer；Remove the dummy gate layer and pseudo- gate oxide, the shape in interlayer dielectric layer
Into gate trench；Gate dielectric layer is formed in the inner wall surface of the gate trench；In the gate dielectric layer table
Face forms the grid layer of the full gate trench of filling.Wherein, the material of the gate dielectric layer is k high Jie
Material (dielectric constant is more than 3.9)；The material of the grid layer be metal, the metal include copper,
Tungsten, aluminium or silver.
In one embodiment, also have between the gate dielectric layer and the side wall and top surface of fin 201
Interface oxide layer；The material of the interface oxide layer is silica；The formation process of the interface oxide layer
It can be thermal oxidation technology；The interface oxide layer is used to strengthen the gate dielectric layer and the surface of fin 201
Between bond strength.
In other embodiments, between the grid layer and gate dielectric layer, additionally it is possible to formed work-function layer,
One or more combination in coating (cap layer) and barrier layer (barrier layer).
To sum up, in the present embodiment, the first resistance is formed in the fin side wall for exposing after sacrifice layer is formed
Barrier, after the sacrifice layer is removed, the doped layer for being formed can be covered and once be sacrificed layer covering
First area fin side wall, subsequently by annealing process after, the first kind ion in the doped layer
Can be spread in the fin side wall for being contacted, therefore, it is possible to remove doped layer after by annealing,
So that the groove depth-to-width ratio increase between adjacent fin, is conducive to the follow-up substrate table between adjacent fin
Face forms the dielectric layer of dense uniform.Secondly as first barrier layer expose second area once by
The fin side wall of sacrifice layer covering, the then fin that directly can be exposed to second area by doping process
Wall doping Second Type ion, without being additionally formed the doped layer comprising Second Type ion with to second
Region fin is doped, therefore allows adjacent fin spacing from further diminution, thus improves device close
Degree.Being additionally, since need not be additionally formed the doped layer comprising Second Type ion for second area fin
Portion is doped, additionally it is possible to reduces by a photoetching process such that it is able to Simplified flowsheet step, and saves work
Skill cost.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore guarantor of the invention
Shield scope should be defined by claim limited range.
Claims (18)
1. a kind of forming method of fin formula field effect transistor, it is characterised in that including：
There is provided substrate, the substrate include first area and second area, the first area of the substrate and
Second area surface has fin respectively；
Sacrifice layer is formed in the substrate surface, the sacrifice layer covers the partial sidewall of the fin, and
Top surface of the surface of the sacrifice layer less than the fin；
After the sacrifice layer is formed, the first barrier layer is formed in the sidewall surfaces of the fin；
After first barrier layer is formed, the sacrifice layer is removed；
After the sacrifice layer is removed, sidewall surfaces, the first resistance that the fin in first area exposes
The top surface of barrier surface and fin is formed has first kind ion in doped layer, the doped layer；
After the sacrifice layer is removed, technique is doped to the side wall that the fin of second area exposes,
The ion of the doping process doping is Second Type ion；
It is doped after technique in formation doped layer and to second area fin, carries out annealing process, is driven
Dynamic first kind ion doping enters the fin of first area, drives Second Type ion doping to enter second area
Fin；
After the annealing process, first barrier layer and doped layer are removed.
2. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that described
Having in the fin and substrate in one region has first kind ion in the first well region, first well region；
Having in the fin and substrate of the second area has Equations of The Second Kind in the second well region, second well region
Type ion.
3. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that described to mix
The forming step of diamicton includes：Doping is formed in the side wall and top surface of the substrate surface and fin
Film；The first mask layer is formed on the doping of the first area；With first mask layer to cover
Film, the etching removal doping, until expose substrate, the partial sidewall surface of fin and
Untill first barrier layer surface, the doped layer is formed in first area.
4. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that also include：
The second barrier layer is formed in the doping layer surface.
5. the forming method of fin formula field effect transistor as claimed in claim 4, it is characterised in that described
The material on two barrier layers is silicon nitride.
6. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that described
The material on one barrier layer is silicon nitride.
7. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that to second
The side wall that the fin in region exposes is doped technique for isotropic plasma doping process.
8. the forming method of fin formula field effect transistor as claimed in claim 7, it is characterised in that described each
Parameter to the plasma doping process of the same sex includes：Process gas includes doped source gas and inertia
Gas, the flow of the doped source gas is 1sccm~50sccm, and the flow of inert gas is
1sccm~50sccm, process atmospheric pressures are less than or equal to 1mTorr, and plasma source power is
100W~500W, bias power is less than or equal to 1W.
9. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that also include：
Before the sacrifice layer is formed, boundary layer is formed in the substrate and fin portion surface；The sacrifice layer
It is formed at the interface layer surfaces；After the sacrifice layer is removed, before forming doped layer, removal
The boundary layer for exposing.
10. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that described sacrificial
The forming step of domestic animal layer includes：Expendable film is formed in the substrate and fin portion surface, the expendable film
Top of the surface higher than fin；Planarize the expendable film；After the expendable film is planarized, return
The expendable film is etched, surface is formed less than the sacrifice layer at the top of fin.
The forming method of 11. fin formula field effect transistors as claimed in claim 1, it is characterised in that described sacrificial
The material of domestic animal layer is bottom antireflection material or organic dielectric material.
The forming method of 12. fin formula field effect transistors as claimed in claim 1, it is characterised in that described
The forming step on one barrier layer includes：In the sacrificial layer surface and the side wall and top table of fin
Face forms the first barrier film；First barrier film is etched back to until exposing sacrifice layer and fin top
Surface, forms first barrier layer.
The forming method of 13. fin formula field effect transistors as claimed in claim 1, it is characterised in that described to move back
Ignition technique is spike annealing or rapid thermal annealing；The temperature of the annealing process is 1000 DEG C~1100 DEG C,
Time is 3 seconds~8 seconds.
The forming method of 14. fin formula field effect transistors as claimed in claim 1, it is characterised in that the fin
The top surface in portion has the second mask layer；After first barrier layer and doped layer is removed, go
Except second mask layer.
The forming method of 15. fin formula field effect transistors as claimed in claim 14, it is characterised in that the lining
The forming step of bottom and fin includes：Semiconductor base is provided；In the part table of the semiconductor base
Face forms the second mask layer；With second mask layer as mask, the semiconductor base, shape are etched
Into the substrate and fin.
The forming method of 16. fin formula field effect transistors as claimed in claim 1, it is characterised in that also include：
After first barrier layer and doped layer is removed, dielectric layer is formed in the substrate surface, it is described
Dielectric layer covers the partial sidewall surface of the fin, and the dielectric layer surface less than the fin
Top surface.
The forming method of 17. fin formula field effect transistors as claimed in claim 16, it is characterised in that also include：
After the dielectric layer is formed, the grid structure of the fin is developed across, the grid structure covers
Cover the partial sidewall and top surface of the fin；Source is formed in the fin of the grid structure both sides
Area and drain region.
The forming method of 18. fin formula field effect transistors as claimed in claim 1, it is characterised in that described
One types of ion is N-type ion；The Second Type ion is p-type ion.
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| CN103855015A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | FinFET and manufacturing method thereof |
| US20150044829A1 (en) * | 2013-08-09 | 2015-02-12 | Samsung Electronics Co., Ltd. | Methods of Fabricating Semiconductor Devices Having Punch-Through Stopping Regions |
| CN104795332A (en) * | 2014-01-21 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Fin-type field effect transistor forming method |
| US20150279963A1 (en) * | 2014-03-26 | 2015-10-01 | International Business Machines Corporation | Methods of forming a finfet semiconductor device so as to reduce punch-through leakage currents and the resulting device |
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2015
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| CN103855015A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | FinFET and manufacturing method thereof |
| US20150044829A1 (en) * | 2013-08-09 | 2015-02-12 | Samsung Electronics Co., Ltd. | Methods of Fabricating Semiconductor Devices Having Punch-Through Stopping Regions |
| CN104795332A (en) * | 2014-01-21 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Fin-type field effect transistor forming method |
| US20150279963A1 (en) * | 2014-03-26 | 2015-10-01 | International Business Machines Corporation | Methods of forming a finfet semiconductor device so as to reduce punch-through leakage currents and the resulting device |
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