CN111933572A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN111933572A CN111933572A CN202011073887.9A CN202011073887A CN111933572A CN 111933572 A CN111933572 A CN 111933572A CN 202011073887 A CN202011073887 A CN 202011073887A CN 111933572 A CN111933572 A CN 111933572A
- Authority
- CN
- China
- Prior art keywords
- silicon oxide
- oxide layer
- nitrogen
- groove
- doped silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention provides a semiconductor structure and a manufacturing method thereof, comprising the following steps: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a groove; sequentially forming a first silicon oxide layer and a nitrogen-doped silicon oxide layer on the bottom and the side wall of the groove; etching and removing part of the nitrogen-doped silicon oxide layer to expose the first silicon oxide layer positioned at the bottom of the groove; and forming a second silicon oxide layer which covers the surface of the nitrogen-doped silicon oxide layer on the side wall of the groove and the surface of the exposed first silicon oxide layer and fills the groove. Because the growth rate of the second silicon dioxide on the first silicon oxide layer is greater than that on the silicon oxynitride layer, the growth rate of the second silicon dioxide at the bottom of the groove is greater than that of the silicon oxynitride layer on the side wall, and the phenomenon that the cavity defect is generated due to premature sealing caused by the fact that the second silicon dioxide layer on the side wall of the groove grows too fast is avoided.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.
Background
As the demand for high integration and high performance of integrated circuits increases, semiconductor technology is moving towards technology nodes of smaller feature sizes. Currently, in the manufacturing technology of semiconductor devices, trench filling is often required to complete the preparation of the semiconductor structure and the whole device structure.
However, in the existing filling technology, whether chemical deposition or material growth is used for filling, when a trench with a large aspect ratio is encountered, the filling and sealing phenomena are easy to occur in advance during filling, so that void defects are generated, and the electrical performance and reliability of the device are affected.
Disclosure of Invention
The present invention is directed to a semiconductor structure and a method for fabricating the same, so as to solve the technical problem of void defect generated during trench filling.
To solve the above technical problem, the present invention provides a method for fabricating a semiconductor structure, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a groove;
sequentially forming a first silicon oxide layer and a nitrogen-doped silicon oxide layer on the bottom and the side wall of the groove;
etching and removing part of the nitrogen-doped silicon oxide layer to expose the first silicon oxide layer positioned at the bottom of the groove; and the number of the first and second groups,
and forming a second silicon oxide layer which covers the surface of the nitrogen-doped silicon oxide layer on the side wall of the groove and the surface of the exposed first silicon oxide layer and fills the groove.
Optionally, the first silicon oxide layer and the nitrogen-doped silicon oxide layer are formed in the same machine.
Optionally, the tool includes a first process chamber and a second process chamber, wherein the first silicon oxide layer is formed in the first process chamber, and the nitrogen-doped silicon oxide layer is formed in the second process chamber.
Optionally, the first silicon oxide layer is grown by using an in-situ steam oxidation reaction process.
Optionally, the nitrogen-doped silicon oxide layer is grown by a decoupled plasma nitridation process or an annealing process in a nitrogen-containing environment.
Optionally, when the nitrogen-doped silicon oxide layer is formed by a decoupled plasma nitridation process, after the step of forming the nitrogen-doped silicon oxide layer, performing a post-nitridation annealing process on the nitrogen-doped silicon oxide layer.
Optionally, the second silicon dioxide layer is grown by using a high aspect ratio process.
Optionally, the step of forming the second silicon dioxide layer includes a first high aspect ratio deposition process, a second high aspect ratio deposition process, and a third high aspect ratio deposition process, where gas flows adopted by the first high aspect ratio deposition process, the second high aspect ratio deposition process, and the third high aspect ratio deposition process are different.
Optionally, in the step of removing a part of the nitrogen-doped silicon oxide layer by etching, the etching process is a dry etching process.
Based on the same inventive concept, the present invention also provides a semiconductor structure, comprising:
a semiconductor substrate having a trench therein;
a first silicon oxide layer covering the bottom and the side wall of the trench;
the nitrogen-doped silicon oxide layer covers the surface of the first silicon oxide layer on the side wall of the groove;
and the second silicon dioxide layer covers the surface of the nitrogen-doped silicon oxide layer positioned on the side wall of the groove and the surface of the first silicon oxide layer positioned at the bottom of the groove and fills the groove.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a semiconductor structure and a manufacturing method thereof.A first silicon oxide layer is formed on the side wall of a groove, a nitrogen-doped silicon oxide layer covering the first silicon oxide layer is formed, and a first silicon oxide layer is formed at the bottom of the groove; and forming a second silicon oxide layer on the surface of the nitrogen-doped silicon oxide layer on the side wall of the groove and the surface of the first silicon oxide layer at the bottom of the groove, and filling the groove. Because the growth rate of the second silicon dioxide on the first silicon oxide layer is greater than that on the silicon oxynitride layer, the growth rate of the second silicon dioxide at the bottom of the groove is greater than that of the silicon oxynitride layer on the side wall, and the phenomenon that the cavity defect is generated due to premature sealing caused by the fact that the second silicon dioxide layer on the side wall of the groove grows too fast is avoided. The first silicon oxide layer and the nitrogen-doped silicon oxide layer are formed by different process chambers of the same machine, so that the process steps of other machines are not required to be added, and the process efficiency is improved.
Drawings
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure in an embodiment of the present invention;
FIGS. 2-8 are schematic structural diagrams corresponding to methods of fabricating semiconductor structures according to embodiments of the present invention;
wherein 101-substrate, 102-etch stop layer, 1021-pad oxide layer, 1022-pad nitride layer, 103-trench, 104-first silicon oxide layer, 105-nitrogen doped silicon oxide layer, 106-first part of second silicon oxide layer, 107-second part of second silicon oxide layer, 108-third part of second silicon oxide layer.
Detailed Description
The semiconductor structure and the method for fabricating the same according to the present invention will be described in detail with reference to the accompanying drawings and embodiments. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As shown in fig. 1, a method for fabricating a semiconductor structure according to an embodiment of the present invention includes:
step S10, providing a semiconductor substrate, wherein the semiconductor substrate is provided with a groove;
step S20, forming a first silicon oxide layer and a nitrogen-doped silicon oxide layer on the bottom and the side wall of the groove in sequence;
step S30, etching and removing part of the nitrogen-doped silicon oxide layer to expose the first silicon oxide layer at the bottom of the groove;
step S40, forming a second silicon oxide layer covering the surface of the nitrogen-doped silicon oxide layer on the sidewall of the trench and the exposed surface of the first silicon oxide layer, and filling up the trench.
Because the growth rate of the silicon oxide on the first silicon oxide layer is greater than that of the nitrogen-doped silicon oxide layer, the growth rate of the silicon oxide at the bottom of the groove is greater than that of the silicon oxide on the side wall of the groove, and therefore the phenomenon of sealing in advance due to the fact that the silicon oxide on the side wall of the groove grows too fast can be avoided, and further the defect of cavities can be avoided.
Example one
The following describes a method for fabricating a semiconductor structure according to an embodiment of the present invention in detail with reference to fig. 2 to 8.
First, step S10 is executed, and referring to fig. 2, a semiconductor substrate 101 having a plurality of trenches 103 is provided. For simplicity, only one trench is shown in FIG. 2.
The semiconductor substrate 101 may be single crystal silicon or polycrystalline silicon, or may be a semiconductor material such as silicon, germanium, silicon germanium, or gallium arsenide, or may be a composite structure such as silicon on insulator. A person skilled in the art may select the type of the semiconductor substrate 101 according to the semiconductor devices formed on the semiconductor substrate 101, and therefore the type of the semiconductor substrate 101 should not limit the scope of the present invention.
In an embodiment, the trench 103 serves as an isolation structure to provide isolation for active regions on two sides of the trench 103, and a MOS transistor or a fin field effect transistor may be formed on the active regions on two sides of the trench 103.
The trench 103 may be formed in the semiconductor substrate 101 using an etching process (dry etching or wet etching process). When the trench 103 is formed by an etching process, the pad oxide layer 1021 and the pad nitride layer 1022 may be sequentially formed on the semiconductor substrate 101 as an etching stop layer 102 to protect the semiconductor substrate 101, and then the etching process is performed to form the trench 103.
The trench 103 may have vertical sidewalls or may have non-vertical sidewalls. The method for manufacturing the semiconductor structure according to the embodiment of the present invention is not particularly limited to the shape and size of the trench 103, but particularly, when the trench 103 has a vertical sidewall and a high aspect ratio, the semiconductor structure formed by the method for manufacturing the semiconductor structure according to the embodiment of the present invention has a significant effect on improving the void defect.
Next, step S12 is performed, referring to fig. 3 and 4, a first silicon oxide layer 104 and a nitrogen-doped silicon oxide layer 105 are sequentially formed on the bottom and the sidewall of the trench 103. The material of the first silicon oxide layer 104 may be silicon dioxide, and the material of the nitrogen-doped silicon oxide layer 105 may be SiOxNy。
The first silicon oxide layer 104 and the nitrogen-doped silicon oxide layer 105 may be formed in a same tool, the tool comprising at least a first process chamber and a second process chamber, wherein the first silicon oxide layer 104 is formed in the first process chamber, for example, and the nitrogen-doped silicon oxide layer 105 is formed in the second process chamber, for example.
Specifically, the first silicon oxide layer 104 may be formed using an In Situ vapor Generation (ISSG) process or a Thermal chemical vapor deposition (TCVD, Thermal CVD) process. In this embodiment the first silicon oxide layer 104 is grown using an in-situ steam generation process, the first silicon oxide layer 104 having a thickness of 50 a-200 a. The first silicon oxide layer 104 can repair the substrate lattice defect in the trench 103 and improve the pressure on the bottom surface of the trench 103, and can also protect the substrate surface in the trench 103 to prevent the substrate from being damaged by the subsequent filling process.
In the in-situ steam generation process, the temperature of the production process can be set according to actual needs, and preferably, the temperature of the production process is 800-1100 ℃.
In the in-situ steam generation process, the time of the production process can be set according to actual needs, and preferably, the time of the production process is 10s-50 s.
In the in-situ steam generation process, the gas of the production process is N2O and H2The gas flow can be set according to actual needs, and preferably, the gas flow is 20slm to 100slm and 0to 1 slm.
In the in-situ steam generation process, the gas pressure of the production process can be set according to actual needs, and preferably, the gas pressure is 10 torr to 50 torr.
The nitrogen-doped silicon oxide layer 105 may be formed by implanting nitrogen plasma into the first silicon oxide layer 104 using a Decoupled Plasma Nitridation (DPN) process. A DPN process is to generate a nitrogen plasma with a high density but a very small electron temperature using RF (radio frequency) and drive the nitrogen plasma into a surface layer (e.g., 1 a-10 a) of the first silicon oxide layer 104, thereby forming the nitrogen-doped silicon oxide layer 105 at the surface layer of the first silicon oxide layer 104.
And injecting nitrogen plasma into the first silicon oxide layer 104 by adopting a decoupling plasma nitridation process at the power of 0W-2 kw. Of course, in other examples, the power may be adjusted to other values according to actual needs. In the decoupled plasma nitridation process, the nitrogen doping concentration of the nitrogen-doped silicon oxide layer 105 can be set according to actual needs, and preferably, the doping concentration of the nitrogen-doped silicon oxide layer 105 is 1E15/cm2-7E15/cm2。
After the nitrogen-doped silicon oxide layer 105 is formed, a plasma nitridation annealing Process (PNA) is performed, and the resulting semiconductor structure is placed in a nitrogen-oxygen mixed atmosphere to be annealed. This process is mainly used to repair the lattice loss in the first silicon oxide layer 104 and to adjust the distribution of the nitrogen plasma.
In the plasma nitridation annealing process, the temperature of the annealing treatment can be set according to actual needs, and preferably, the temperature of the annealing treatment is 800-1100 ℃.
In the plasma nitridation annealing process, the time of the annealing treatment can be set according to actual needs, and preferably, the time of the annealing treatment is 50s-200 s.
In the plasma nitridation annealing process, the pressure of the process chamber for annealing treatment can be set according to actual needs, and preferably, the pressure of the process chamber for annealing treatment is 20torr to 100 torr.
In one embodiment, when performing the plasma nitridation annealing process, the obtained semiconductor structure may be placed in a PNA process chamber, and a mixed gas of nitrogen and oxygen is introduced into the process chamber, and then the process chamber is heated, and after the temperature in the process chamber reaches an annealing temperature (e.g., 800 ℃ -1100 ℃), the temperature is maintained for a certain time (e.g., 50s-200 s) so that nitrogen plasma is diffused in the first silicon oxide layer 104 to form the nitrogen-doped silicon oxide layer 105, and finally the temperature is reduced to room temperature.
In a preferred embodiment, the first silicon oxide layer 104, the nitrogen-doped silicon oxide layer 105 and the PNA process are performed in different process chambers of a same tool, thereby preventing unnecessary contamination of the semiconductor structure when the semiconductor structure enters or exits from multiple tools.
Next, the nitrogen-doped silicon oxide layer on the sidewall of the trench in this embodiment replaces the growth control layer on the sidewall of the trench in the prior art, and the sidewall of the trench in the prior art needs to use an ALD process to grow the control layer.
In step S30, referring to fig. 5, a portion of the nitrogen-doped silicon oxide layer 105 is removed by etching to expose the first silicon oxide layer 104 at the bottom of the trench 103.
In this step, a dry etching process may be used to remove a portion of the nitrogen-doped silicon oxide layer 105, when the nitrogen is dopedWhen the material of the hetero-silicon oxide layer 105 is selected to be silicon oxynitride, the main gas for etching may be CF4And may also comprise O2、CO、Ar、CHF3One or more of them.
Next, step S40 is executed, and referring to fig. 6-8 in particular, a High Aspect Ratio Process (HARP) may be used to form a second silicon oxide layer, where the second silicon oxide layer includes a first portion of the second silicon oxide layer, a second portion of the second silicon oxide layer, and a third portion of the second silicon oxide layer, and is formed by a first High Aspect Ratio deposition Process, a second High Aspect Ratio deposition Process, and a third High Aspect Ratio deposition Process, respectively, where gas flow rates adopted by the first High Aspect Ratio deposition Process, the second High Aspect Ratio deposition Process, and the third High Aspect Ratio deposition Process are different.
In a specific implementation, a first high aspect ratio deposition process may be used to form a first portion 106 of a second silicon oxide layer, where the first portion 106 of the second silicon oxide layer covers the surface of the nitrogen-doped silicon oxide layer 105 on the sidewall of the trench 103 and the exposed surface of the first silicon oxide layer 104. The first portion 106 of the second silicon dioxide layer is thinner, the first portion 106 of the second silicon dioxide layer within the trench 103 having a thickness of, for example, 500 a-1000 a. In the first high aspect ratio deposition process, the process gas comprises TEOS (tetraethylorthosilicate) and O3Preferably, the TEOS flow is first introduced into 500sccm-1500sccm and then increased to 1000sccm-3000sccm, O3The flow rate is 10000sccm-30000 sccm.
In particular, a second high aspect ratio deposition process may be used to form a second portion 107 of the second silicon dioxide layer, where the second portion 107 of the second silicon dioxide layer covers the first portion 106 of the second silicon dioxide layer. A second portion 107 of the second silicon dioxide layer within the trench 103 has a thickness from 500 a-1500 a, the trench 103 being filled. Of course, in other embodiments, the second portion 107 of the second silicon dioxide layer may not fill the trench 103. In the second high aspect ratio deposition process, the process gas comprises TEOS and O3, preferably, the TEOS flow is 1500sccm to 3500sccm, O3The flow rate is 10000sccm-30000 sccm.
In particular, a third portion 108 of the second silicon dioxide layer may be formed by a third high aspect ratio deposition process, wherein the third portion 108 of the second silicon dioxide layer covers the second portion 107 of the second silicon dioxide layer. The third portion 108 of the second silicon dioxide layer over the trench 103 is thicker than the first portion 106 of the second silicon dioxide layer and the second portion 107 of the second silicon dioxide layer, for example, 2000 a-5000 a. In the third high aspect ratio deposition process, the process gas comprises TEOS, O3And O2Preferably, the TEOS flow rate is 4000sccm to 7000sccm, O3The flow rate is 10000sccm-30000sccm, O2The flow rate is 10000sccm-20000 sccm.
The process temperature in the first high aspect ratio deposition process, the second high aspect ratio deposition process and the third high aspect ratio deposition process may be set according to actual needs, and preferably, in this embodiment, the process temperature is 400 ℃ to 800 ℃.
The pressure of the first high aspect ratio deposition process, the second high aspect ratio deposition process and the third high aspect ratio deposition process may be set according to actual needs, and preferably, in this embodiment, the pressure of the processes is 400torr to 1000 torr.
When the second silicon oxide layer is formed, the growth rate of the second silicon oxide layer on the surface of the first silicon oxide layer 104 is greater than that on the nitrogen-doped silicon oxide layer 105, that is, the growth rate of the second silicon oxide layer at the bottom of the trench 103 is greater than that of the second silicon oxide layer on the side wall of the trench 103, so that the phenomenon of premature sealing caused by the fact that the silicon oxide layer on the side wall of the trench 103 grows too fast can be avoided, and further, the generation of void defects can be avoided.
Meanwhile, the first silicon oxide layer 104, the nitrogen-doped silicon oxide layer 105 and the PNA process are formed in different process chambers of the same machine, so that the semiconductor structure is prevented from being polluted by entering and exiting a plurality of machines.
The nitrogen-doped silicon oxide layer 105 is formed by a decoupled plasma nitridation process, so that the physical thickness of the side wall of the trench 103 is not increased, the aspect ratio of the trench 103 is not increased, and the filling difficulty of the trench 103 is not increased.
In this embodiment, when the nitrogen-doped silicon oxide layer 105 at the bottom of the trench 103 is removed by etching, the topography of the top corner of the trench 103 is not damaged, and the electrical performance of the device is not affected.
Example two
The difference from the first embodiment is that, in step S20, the nitrogen-doped silicon oxide layer 105 is formed by using an NO annealing process that is performed by using gaseous NO and SiO in the first silicon oxide layer 1042Reaction to produce SiOxNyIn this embodiment, the nitrogen-doped silicon oxide layer 105 is SiOxNy。
In the NO annealing process, the temperature of the annealing treatment may be set according to actual needs, and preferably, in this embodiment, the temperature of the annealing treatment is 800 ℃ to 1100 ℃.
In the NO annealing process, the time of the annealing treatment may be set according to actual needs, and preferably, in this embodiment, the time of the annealing treatment is less than 70 s.
In the NO annealing process, the pressure of the annealing process may be set according to actual needs, and preferably, in this embodiment, the pressure of the annealing process is 500torr to 1000 torr.
In the NO annealing process, the gas flow rate of the annealing treatment may be set according to actual needs, and preferably, in this embodiment, the gas flow rate of the annealing treatment is 1slm to 5 slm.
In this embodiment, the nitrogen-doped silicon oxide layer 105 is formed by an NO annealing process, and a PNA process is not required after this step, and the NO annealing process in this embodiment implements the decoupled plasma nitridation process and the PNA process in the first embodiment, thereby saving the process time and improving the production efficiency.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, similar parts between the embodiments may be referred to each other, and different parts between the embodiments may also be used in combination with each other, which is not limited by the present invention.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method for fabricating a semiconductor structure, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a groove;
sequentially forming a first silicon oxide layer and a nitrogen-doped silicon oxide layer on the bottom and the side wall of the groove;
etching and removing part of the nitrogen-doped silicon oxide layer to expose the first silicon oxide layer positioned at the bottom of the groove; and the number of the first and second groups,
and forming a second silicon oxide layer which covers the surface of the nitrogen-doped silicon oxide layer on the side wall of the groove and the surface of the exposed first silicon oxide layer and fills the groove.
2. The method of claim 1, wherein the first silicon oxide layer and the nitrogen-doped silicon oxide layer are formed in a same tool.
3. The method of claim 2, wherein the tool comprises a first process chamber and a second process chamber, wherein the first silicon oxide layer is formed in the first process chamber and the nitrogen-doped silicon oxide layer is formed in the second process chamber.
4. The method of claim 3, wherein the first silicon oxide layer is grown using an in-situ steam oxidation process.
5. The method of claim 3, wherein the nitrogen doped silicon oxide layer is grown using a decoupled plasma nitridation process or an annealing process in a nitrogen containing ambient.
6. The method of fabricating a semiconductor structure of claim 5, wherein, when forming the nitrogen-doped silicon oxide layer using a decoupled plasma nitridation process, the step of forming the nitrogen-doped silicon oxide layer further comprises performing a post nitridation annealing process on the nitrogen-doped silicon oxide layer.
7. The method of claim 1, wherein the second silicon dioxide layer is grown using a high aspect ratio process.
8. The method of claim 7, wherein the step of forming the second silicon dioxide layer comprises a first high aspect ratio deposition process, a second high aspect ratio deposition process, and a third high aspect ratio deposition process, wherein the first high aspect ratio deposition process, the second high aspect ratio deposition process, and the third high aspect ratio deposition process use different gas flows.
9. The method for manufacturing a semiconductor structure according to claim 1, wherein in the step of removing a portion of the nitrogen-doped silicon oxide layer by etching, the etching process is a dry etching process.
10. A semiconductor structure, comprising:
a semiconductor substrate having a trench therein;
a first silicon oxide layer covering the bottom and the side wall of the trench;
the nitrogen-doped silicon oxide layer covers the surface of the first silicon oxide layer on the side wall of the groove;
and the second silicon dioxide layer covers the surface of the nitrogen-doped silicon oxide layer positioned on the side wall of the groove and the surface of the first silicon oxide layer positioned at the bottom of the groove and fills the groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011073887.9A CN111933572A (en) | 2020-10-10 | 2020-10-10 | Semiconductor structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011073887.9A CN111933572A (en) | 2020-10-10 | 2020-10-10 | Semiconductor structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111933572A true CN111933572A (en) | 2020-11-13 |
Family
ID=73334978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011073887.9A Pending CN111933572A (en) | 2020-10-10 | 2020-10-10 | Semiconductor structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111933572A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115799160A (en) * | 2023-01-09 | 2023-03-14 | 广州粤芯半导体技术有限公司 | Semiconductor structure and method for making the same |
| CN115985842A (en) * | 2023-01-28 | 2023-04-18 | 和舰芯片制造(苏州)股份有限公司 | Method for improving deformation of deep groove process wafer and wafer |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080268608A1 (en) * | 2007-04-25 | 2008-10-30 | Hynix Semiconductor Inc. | Method of fabricating a flash memory device |
| CN102097356A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Method for making shallow trench isolation structure |
| CN107706090A (en) * | 2017-09-22 | 2018-02-16 | 德淮半导体有限公司 | Fleet plough groove isolation structure, semiconductor structure and preparation method thereof |
| CN110211918A (en) * | 2019-05-30 | 2019-09-06 | 德淮半导体有限公司 | The production method and semiconductor structure of semiconductor structure |
-
2020
- 2020-10-10 CN CN202011073887.9A patent/CN111933572A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080268608A1 (en) * | 2007-04-25 | 2008-10-30 | Hynix Semiconductor Inc. | Method of fabricating a flash memory device |
| CN102097356A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Method for making shallow trench isolation structure |
| CN107706090A (en) * | 2017-09-22 | 2018-02-16 | 德淮半导体有限公司 | Fleet plough groove isolation structure, semiconductor structure and preparation method thereof |
| CN110211918A (en) * | 2019-05-30 | 2019-09-06 | 德淮半导体有限公司 | The production method and semiconductor structure of semiconductor structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115799160A (en) * | 2023-01-09 | 2023-03-14 | 广州粤芯半导体技术有限公司 | Semiconductor structure and method for making the same |
| CN115985842A (en) * | 2023-01-28 | 2023-04-18 | 和舰芯片制造(苏州)股份有限公司 | Method for improving deformation of deep groove process wafer and wafer |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4009243B2 (en) | Semiconductor process | |
| US11749756B2 (en) | Method for manufacturing semiconductor device | |
| US7786016B2 (en) | Methods of uniformly removing silicon oxide and a method of removing a sacrificial oxide | |
| US6949447B2 (en) | Method for fabricating isolation layer in semiconductor device | |
| JPH06314777A (en) | Manufacture of semiconductor device | |
| KR100637689B1 (en) | Method for forming contact of semiconductor device using solid phase epitaxy | |
| KR20110104482A (en) | Gapfill improvement with low etch rate dielectric liners | |
| US20060237766A1 (en) | Semiconductor device using solid phase epitaxy and method for fabricating the same | |
| JPH02304947A (en) | Manufacture of semicowductor device | |
| US7238588B2 (en) | Silicon buffered shallow trench isolation | |
| CN109585291A (en) | The forming method of semiconductor structure | |
| KR100390919B1 (en) | Method for fabricating semiconductor device | |
| CN111933572A (en) | Semiconductor structure and manufacturing method thereof | |
| US10879111B1 (en) | Dielectric plugs | |
| CN114899097A (en) | Shielding gate trench device field oxide and manufacturing method of shielding gate trench device | |
| JP5119604B2 (en) | Manufacturing method of semiconductor device | |
| KR20050003019A (en) | Fabricating method of semiconductor device adopting nf3 high density plasma oxide layer | |
| KR100678465B1 (en) | Method of forming selective epitaxial semiconductor layer | |
| CN115799160A (en) | Semiconductor structure and method for making the same | |
| CN114420632A (en) | Method for manufacturing semiconductor device | |
| CN104851802B (en) | A kind of semiconductor devices and preparation method thereof | |
| US20110008972A1 (en) | Methods for forming an ald sio2 film | |
| CN112017953B (en) | Epitaxial growth method | |
| WO2024146046A1 (en) | Preparation method for semiconductor structure, semiconductor structure and memory | |
| KR100524802B1 (en) | Semiconductor device having contact plug formed using double selective epitaxial growth and method for fabrication of the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20201113 |