CN104851802B - A kind of semiconductor devices and preparation method thereof - Google Patents

A kind of semiconductor devices and preparation method thereof Download PDF

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Publication number
CN104851802B
CN104851802B CN201410051810.XA CN201410051810A CN104851802B CN 104851802 B CN104851802 B CN 104851802B CN 201410051810 A CN201410051810 A CN 201410051810A CN 104851802 B CN104851802 B CN 104851802B
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dummy gate
layer
formed
metal
metal gates
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CN201410051810.XA
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CN104851802A (en
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卜伟海
陈勇
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中芯国际集成电路制造(上海)有限公司
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Abstract

The present invention provides a kind of semiconductor devices and preparation method thereof, manufacturing process according to the present invention proposes a kind of new method for forming metal gates filling, utilize the oxidation rate difference of the polysilicon layer of different levels of doping, to form dummy gate wide at the top and narrow at the bottom, the dummy gate structure is conducive to the filling of metal gates, the production method adds the filling capacity of metal gates, and the technique of making metal gates is become simple.Meanwhile production method of the invention performance compatible with high k dielectric layer/metal gate process is good, the polysilicon gate extremely dummy gate structure in NFET and PFET regions, so doping situation can be adjusted freely.

Description

A kind of semiconductor devices and preparation method thereof

Technical field

The present invention relates to semiconductor fabrication process, in particular to one kind in rear metal gate technique(metal gate last process)The middle method for forming electrode.

Background technology

With the continuous development of semiconductor technology, the raising of performance of integrated circuits is mainly by constantly reducing integrated circuit The size of device is realized with improving its speed.At present, due in high device density, high-performance and low cost is pursued half Conductor industry has advanced to nanometer technology process node, particularly when dimensions of semiconductor devices drops to 20nm or following, half The preparation of conductor device is limited be subject to various physics limits.It is rear high for the CMOS with more advanced technology node K/ metal gates(high-k and metal gate last)Technology is had been widely used in cmos device, with partly leading The width of the increasingly reduction of gate groove of body device size is also less and less, this will influence to form metal gate electrode thin film stacked structure The difficulty of technique and increase metal gate material fill process.

Main devices in integrated circuit (IC) especially super large-scale integration are metal oxide semiconductcor field effects Answer transistor(MOS), with the maturation of semiconductor integrated circuit industrial technology increasingly, the rapid hair of ultra-large integrated circuit Exhibition, have higher performance and more powerful integrated circuit requirement bigger component density, and between all parts, element or Size, size and the space of each element itself are also required to further reduce.Currently in order to meet the development of semiconductor technology, Wetting layer formed with different-thickness(Soakage layer)Structure(The structural top side wall is spaced about 10nm)In fill out Fill to form aluminum metal layer to replace metal gates of the prior art.

But for more advanced technology node and meet the manufacture requirement of next generation's integrated circuit, in gap filling The Ti soakage layers formed before (gap fill) using PVD process form overhang in the trench(overhang), after this will be influenced The space stuffing techniques of continuous aluminum metal layer.Then, there has been proposed using cobalt(Co)Soakage layer replaces Ti soakage layers, cobalt infiltration Layer can alleviate the problem of forming overhang in the trench, but cobalt soakage layer is a kind of for rear high K/ metal gate process New material, this will introduce impurity in the metal gate structure of formation, its control for pollutant and high K/ metal gates In chemical mechanical milling tech all bring very big difficult and new challenge.

It is, therefore, desirable to provide a kind of production method of new semiconductor devices, to solve the problems of the prior art.

The content of the invention

A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed Key feature and essential features, do not mean that the protection domain for attempting to determine technical solution claimed more.

In order to solve the problems in the existing technology, the present invention proposes a kind of production method of semiconductor devices, wraps Include:Semiconductor substrate is provided;Grid oxic horizon, dummy gate material layer and hard mask are sequentially formed on the semiconductor substrate Layer, wherein, doping process is performed while the dummy gate material layer is formed, so that the dummy gate material layer is mixed Miscellaneous concentration is gradually reduced from bottom to top;The hard mask layer and the dummy gate material layer are etched, to form the first virtual grid Pole;Perform oxidation technology, first dummy gate of oxidized portion is to form from bottom to top gradually thinning oxide layer;Remove The oxide layer, to form the second dummy gate wide at the top and narrow at the bottom;Sidewall structure is formed in the both sides of second dummy gate; Interlayer dielectric layer is formed on the semiconductor substrate, performs flatening process to expose second dummy gate.

Preferably, it is additionally included in execution planarisation step and removes second dummy gate and positioned at described second afterwards The step of grid oxic horizon below dummy gate is to form metal gates groove.

Preferably, it is additionally included in be formed after the metal gates groove and high K is filled in the metal gates groove is situated between The step of electric layer and metal gate layers are to form metal gates.

Preferably, the doping step is performed using doping process in situ or injection technology.

Preferably, it is additionally included in and performs the step of oxidation technology performs source drain extension regions injection afterwards.

Preferably, it is additionally included in form the step of sidewall structure forms source/drain afterwards.

Preferably, the etch step is performed using anisotropic etch process.

Preferably, the oxide layer is removed using diluted hydrofluoric acid.

The invention also provides a kind of semiconductor devices, the semiconductor devices includes manufacturing using above-mentioned either method Metal gate structure, the metal gate structure is metal gate structure wide at the top and narrow at the bottom.

In conclusion manufacturing process proposes a kind of new method for forming metal gates filling according to the present invention, utilize The oxidation rate difference of the polysilicon layer of different levels of doping, to form dummy gate wide at the top and narrow at the bottom, the dummy gate structure Be conducive to the filling of metal gates, which adds the filling capacity of metal gates, and makes making metal gates Technique becomes simple.Meanwhile production method of the invention performance compatible with high k dielectric layer/metal gate process is good, in NFET and Polysilicon gate extremely dummy gate structure in PFET regions, so doping situation can be adjusted freely.

Brief description of the drawings

The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair Bright embodiment and its description, principle used to explain the present invention.In attached drawing:

Figure 1A-Fig. 1 F are the correlation step for the method that metal gate structure is made according to the embodiment of one aspect of the invention Schematic cross sectional view;

Fig. 2 is the flow chart for the method that metal gate structure is made according to the embodiment of one aspect of the invention.

Embodiment

In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into Row description.

In order to thoroughly understand the present invention, detailed step will be proposed in following description, to explain proposition of the present invention Method.Obviously, execution of the invention is not limited to the specific details that the technical staff of semiconductor applications is familiar with.The present invention Preferred embodiment be described in detail as follows, but except these detailed description in addition to, the present invention can also have other embodiment.

It should be appreciated that when the term " comprising " and/or " including " is used in this specification, it is indicated described in presence Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety, Step, operation, element, component and/or combinations thereof.

In the following, the detailed step of the method for formation metal gate structure proposed by the present invention is described with reference to Figure 1A-Fig. 1 F.

First, as shown in Figure 1A, there is provided Semiconductor substrate 100, Semiconductor substrate 100 may include any semi-conducting material, This semi-conducting material may include but be not limited to:Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and other III- V or group Ⅱ-Ⅵ compound semiconductor.Semiconductor substrate 100 can also include organic semiconductor or such as Si/SiGe, insulator Upper silicon(SOI)Or SiGe on insulator(SGOI)Layered semiconductor.

In a specific embodiment of the invention, the Semiconductor substrate 100 selects single crystal silicon material to form.Partly led described Formed with isolation structure in body substrate 100, in the present embodiment, the isolation structure isolates (STI) structure for shallow trench.Described half Various traps (well) structure is also formed with conductor substrate 100, to put it more simply, being omitted in diagram.

Grid oxic horizon 101 is formed on a semiconductor substrate 100, and grid oxic horizon 101 can pass through thermal oxide, chemical gas Mutually deposit(CVD)Or oxynitridation process is formed.Grid oxic horizon 101 can include following any conventional dielectric:SiO2、 SiON, SiON2 and other similar oxides including perofskite type oxide.Wherein, the material of gate oxide 101 is preferred With silicon oxynitride, generation type uses chemical vapour deposition technique.

Dummy gate material layer 102 is formed on grid oxic horizon 101, the material of dummy gate material layer 102 is preferably not The polysilicon of doping.In a specific embodiment of the invention, low-pressure chemical vapor phase deposition can be selected in the forming method of polysilicon (LPCVD) technique.Forming the process conditions of the polysilicon includes:Reacting gas is silane (SiH4), the flow of the silane Scope can be 100~200 cc/mins (sccm), such as 150sccm;Temperature range can be taken the photograph for 700~750 in reaction chamber Family name's degree;It can be 250~350 milli millimetress of mercury (mTorr) to react cavity pressure, such as 300mTorr;May be used also in the reacting gas Including buffer gas, the buffer gas can be helium or nitrogen, the range of flow of the helium and nitrogen can be 5~20 liters/ Minute (slm), such as 8slm, 10slm or 15slm.

Preferably, doping process in situ or injection technology are performed when forming dummy gate material layer 102.Specifically , while dummy gate material layer 102 are formed, doping process in situ or injection technology are performed with dummy gate Concentration gradient is formed in material layer 102, concentration is gradually reduced dummy gate material layer 102 from bottom to top.

Exemplarily, while dummy gate material layer 102 are formed, doping in situ can be carried out with virtual grid Concentration gradient is formed in pole material layer 102, concentration is gradually reduced from top to bottom.In embodiments of the present invention, arsine can be passed through AsH3, phosphine PH3Or borine BH3Deng impurity gas, doping concentration in situ can be 1014To 1020Atom/cm3.For extension gas The difference of body, can also use other impurity gas, in one embodiment of the invention, form 102 gas of dummy gate material layer The flow of body and impurity gas and technique, temperature etc. have relation, needed for different temperature and technique to epitaxial gas and The flow of impurity gas is changed, these should all be included in the protection scope of the present invention.

Exemplarily, while dummy gate material layer 102 are formed, ion implantation technology can be carried out with void Intend forming concentration gradient in gate material layers 102, concentration is gradually reduced from top to bottom.In embodiments of the present invention, ion implanting Technique be:Injection ion beam energy is 10KV~50KV, ion dose 1e14~1e20Atom/cm2, the angle of inclination of injection Scope is 0 °~10 °.

Hard mask layer 103 is formed in dummy gate material layer 102, the material of hard mask layer 103 can be nitride, nitrogen oxygen Compound, the oxide rich in silicon, fluorine-containing silica(FSG), the silica of carbon doping(black diamond)Deng such as class As material, as the hard mask layer during subsequent etching.Hard mask layer, which can use, to be included but not limited to:Chemical vapor is sunk The method of product method and physical vapor deposition methods is formed.The preferred silica of material of wherein hard mask layer, hard mask layer Thickness is 100 angstroms to 1000 angstroms.

As the embodiment of the present invention, dielectric antireflective coatings are sequentially formed on hard mask layer 103 (DARC), bottom antireflective coating(BARC)With patterned photoresist layer.

Photoetching process is used to etch the hard mask layer 103 and dummy gate material layer 102 to form grid 104 and position Hard mask layer 103 ' on grid 104, exposes grid oxic horizon 101, as shown in Figure 1B, by lithography mask version by grid knot The pattern transfer of structure is used as mask etching hard mask layer 103 and dummy gate material layer on hard mask layer using photoresist layer 102, remove the photoresist layer.

Dry ecthing method can be used or the hard mask layer 103 and dummy gate material are etched using wet etch method Layer 102.Traditional deep dry etch process, for example, reactive ion etching, ion beam etching, plasma etching, laser ablation or these Any combination of method.Single lithographic method can be used, or more than one lithographic method can also be used, preferably Ground, dry ecthing method can use the anisotropic etch process based on carbon fluoride gas.

In of the invention one specifically embodiment, using plasma etching, etching gas can use CF4(Four Fluorocarbons).Specifically, low pressure and highdensity plasma gas can be simultaneously produced using relatively low RF energy to realize dry method Etching.The etching gas used are for the flow of carbon tetrafluoride etching gas:100~200 cc/mins (sccm);Instead It can be 30~50mTorr to answer room pressure, and the time of etching is 10~15 seconds, and power is 50~100W, bias power 0W

As shown in Figure 1 C, using oxidation(reoxidation)Process above-mentioned semiconductor device structure, not by hard mask After the covering of layer 103 ' and the 104 oxidized process of grid exposed, the grid 104 of part is oxidized to oxide layer 105, shape Into oxide layer from bottom to top gradually it is thinning.There is different oxidations rate using the grid 104 of different levels of doping, to be formed Dummy gate 104 ' wide at the top and narrow at the bottom.

In the specific embodiment of the present invention, the silicon exposed in grid 104 is aoxidized using oxidation technology, to aoxidize The material in the grid 104 of part is consumed in journey to form oxide layer 105.Oxidation technology can be film by wet hot oxidation technique or dry Thermal oxidation technology, alternatively, can be by carrying out oxidation technology in the atmosphere of oxygen source such as molecular oxygen or/and ozone.

In the embodiment of the present invention, using plasma etching, etching gas can use and be based on oxygen Gas.Specifically, low pressure and highdensity plasma gas can be simultaneously produced using relatively low RF energy to realize polycrystalline The dry etching of silicon.The etching gas used can also be passed through some inert gases as addition gas for the gas based on oxygen Machine, the flow of etching gas are:200~300 cc/mins (sccm);It can be 30~50mTorr to react room pressure, The time of etching is 15~20 seconds, and power is 100~200W.

It should be noted that the method for above-mentioned oxidation is exemplary, it is not limited to the method, this area other As long as method can realize the purpose, the present invention is can be applied to, details are not described herein.

Then, the source-drain area expansion area in the active area of the both sides of dummy gate 104 ' carries out ion implantation technology, at this Foreign matter of phosphor is selected in embodiment, is formed in the surfaces of active regions of Semiconductor substrate 100 by ion implanted impurity phosphorus and is relatively lightly doped N-type injection zone, as source and drain extension.

As shown in figure iD, removing oxide layer 105 is removed, to expose not oxidized dummy gate 104 ', can be used diluted Hydrofluoric acid and phosphoric acid remove removing oxide layer 105, and in the specific embodiment of the present invention, removing oxide layer is removed using diluted hydrofluoric acid 105, the concentration ratio of diluted hydrofluoric acid is 2%, and the time of reaction is 1 minute, can immerse Semiconductor substrate(dip)Hydrogen fluorine In acid solution.

It should be noted that it is exemplary that the method for removing oxide layer 105 is gone in above-mentioned execution, it is not limited to the side Method, as long as this area other methods can realize the purpose, can be applied to the present invention, details are not described herein.

On a semiconductor substrate 100 with spacer material layer is formed on dummy gate 104 ', using anisotropic etch process Etch the spacer material layer, with the both sides of dummy gate 104 ' on a semiconductor substrate 100 formed sidewall structure 106A, 106B。

The sidewall structure material can be a kind of in silica, silicon nitride, silicon oxynitride or they combine and form.Make For an optimal enforcement mode of the present embodiment, the sidewall structure is silica, silicon nitride collectively constitutes, and concrete technology is: The first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer are formed on a semiconductor substrate, can use heat treatment work Skill, chemical vapor deposition etc., then form sidewall structure using engraving method.It is preferred that side is formed using chemical vapor deposition method Wall construction, the reaction temperature of the chemical vapor deposition method are 500 DEG C to 800 DEG C, the reaction time for 10 minutes to 10 it is small when.

Sidewall structure is formed on each side wall of grid.Sidewall structure includes nitride, oxynitride or their group Close, be by depositing and etching formation.Sidewall structure can have different thickness, but be measured since basal surface, side wall The thickness of structure is usually 10nm to 30nm.

Dry ecthing method can be used wet etch method can also to be used to form sidewall structure.Dry ecthing method can use and be based on fluorine Change the anisotropic etch process of carbon gas.Wet etch method can use hydrofluoric acid solution, such as buffer oxide etch agent or hydrogen Fluoric acid buffer solution.

After the dummy gate 104 ' and sidewall structure 106A, 106B is formed, ion implantation technology is carried out, with void Intend forming regions and source/drain in the Semiconductor substrate 100 around grid 104 '.And then rapid thermal annealing process is carried out, The doping in regions and source/drain is activated using 900 to 1050 DEG C of high temperature, and is repaired at the same time in each ion implantation technology In be damaged semiconductor substrate surface lattice structure.In addition, also visible product demand and feature are considered.Specifically, can be with The source-drain area is formed by ion implanting or the method for diffusion, as it is further preferably, carry out ion implanting or A step of thermal annealing being can further include after person's diffusion.

The annealing steps are usually to be placed in the substrate under the protection of high vacuum or high-purity gas, are heated to certain Temperature carries out rapid temperature annealing (RTA) technique, is preferably nitrogen or inert gas in high-purity gas of the present invention, described fast The temperature of fast thermal annealing process step is 800-1200 DEG C, is preferably 1050 DEG C, the thermal anneal step time is 1-300s. As further preferably, the rapid thermal annealing selected in the present invention, can select one kind in following several ways:Pulse Laser short annealing, the short annealing of pulsed electron book, ion beam short annealing, continuous wave laser short annealing and incoherent width Band light source(Such as halogen lamp, arc lamp, graphite heating)Short annealing etc., but it is not limited to examples cited.

Then, interlevel dielectric deposition 107 is formed on a semiconductor substrate 100(ILD), interlayer dielectric layer 107 is formed in On Semiconductor substrate 100, dummy gate 104 ' and side wall 106A, 106B.The interlayer dielectric layer 107 can be silicon oxide layer, bag Include what is formed using thermal chemical vapor deposition (thermal CVD) manufacturing process or high-density plasma (HDP) manufacturing process There are the material layer of doped or undoped silica, such as undoped silica glass (USG), phosphorosilicate glass (PSG) or boron phosphorus Silica glass (BPSG).In addition, interlayer dielectric layer can also be the spin cloth of coating-type glass (spin-on- for adulterating boron or adulterating phosphorus Glass, SOG), doping phosphorus tetraethoxysilane (PTEOS) or adulterate boron tetraethoxysilane (BTEOS).

After interlevel dielectric deposition 107, a planarisation step can also be further included, semiconductor manufacturing can be used Conventional flattening method realizes the planarization on surface in field.It is flat that the non-limiting examples of the flattening method include machinery Smoothization method and chemically mechanical polishing flattening method.Chemically mechanical polishing flattening method is more often used.The planarisation step Stop on the dummy gate 104 ' and side wall 106A, 106B.

To those skilled in the art, covering firmly above dummy gate 104 ' is eliminated in planarisation step Film layer 103 ' is it will be apparent that not just being discussed in detail herein.,

Then, as referring to figure 1E, dummy gate 104 ' and the grid oxic horizon below dummy gate 104 ' are removed 101 expose Semiconductor substrate 100 to form metal valley 108.Specifically, in an embodiment of the present invention, dry etching is selected Either wet etching or dry-wet mixing close etching to remove dummy gate 104 ' and the grid below dummy gate 104 ' Oxide layer 101 is to form metal gates groove 108.Wherein, the dry etching is included in reacting gas metal reaction chamber Remote plasma is used before(remote plasma)Technique or microwave(microwave)Technique forms ionized gas, with Avoid producing plasma damage to Semiconductor substrate.

When selecting dry etching, HBr can be selected as main etch gas;Further include as etching make-up gas O2 or Ar, it can improve the quality of etching.Or wet etching is selected, when selecting wet etching, select KOH and tetramethyl hydrogen Aoxidize ammonia(TMAH)In one or more, the present invention select KOH be etched, preferred mass fraction is in the present invention The KOH of 5-50% is etched, while strictly controls the temperature of the etching process, and preferred etch temperature is 20-60 in this step ℃。

Preferably, removal dummy gate 104 ' and the grid oxic horizon 101 below dummy gate 104 ' are formed Metal valley 108, the structure of metal valley 108 is wide at the top and narrow at the bottom, and the filling which is conducive to metal gates is formed.

As shown in fig. 1F, filling forms high k dielectric layer/metal gate structure 109 in metal gates groove 108, specifically The bottom deposit in metal gates groove 108 form boundary layer and high k dielectric layer, then deposited metal material and planarize. In one embodiment of this invention, the metal gates are formed by depositing multiple film stacks.The film includes work(interface Layer, hafnium layer and metal material layer.The hafnium forms the gate dielectric, is used for example in HfO2Middle introducing The elements such as Si, Al, N, La, Ta simultaneously optimize the ratio of each element obtained hafnium etc..The side for forming gate dielectric Method can be physical gas-phase deposition or atom layer deposition process.In an embodiment of the present invention, in the SiO2Boundary layer Upper formation HfAlON gate dielectrics, its thickness are 15 to 60 angstroms.The metal material layer can with the method for CVD or PVD into Row deposition.After conductive layer formation, anneal under 300-500 degree celsius temperatures.What it was reacted in containing nitrogen environment Time is 10-60 minutes.The planarization of conductive layer is finally carried out, metal gates are formed to remove the conductive layer beyond groove 109。

With reference to Fig. 2, the flow chart that an embodiment according to the present invention makes the method for metal gate structure is illustrated therein is, is used In the flow for schematically illustrating whole manufacturing process.

In step 201, there is provided Semiconductor substrate, sequentially forms grid oxic horizon on the semiconductor substrate, in grid Gate material layers are formed in the oxide layer of pole, doping in situ or injection technology is carried out at the same time, is formed in gate material layers and covered firmly Film layer;

In step 202, the hard mask layer and gate material layers are etched, to form the first dummy gate;

In step 203, oxidation technology is performed, the first dummy gate of oxidized portion is to form oxide layer;

In step 204, the oxide layer is removed to form the second dummy gate, in the both sides of second dummy gate Form sidewall structure;

In step 205, interlayer dielectric layer is formed on the semiconductor substrate, performs flatening process;

In step 206, the second dummy gate and grid oxic horizon below the second dummy gate are removed to be formed Metal gates groove;

In step 207, filling forms high k dielectric layer/metal gates in metal gates groove.

Production method according to the present invention also proposed a kind of semiconductor devices, and the semiconductor devices includes metal gates Structure, the metal gate structure are metal gate structure wide at the top and narrow at the bottom.

In conclusion manufacturing process proposes a kind of new method for forming metal gates filling according to the present invention, utilize The oxidation rate difference of the polysilicon layer of different levels of doping, to form dummy gate wide at the top and narrow at the bottom, the dummy gate structure Be conducive to the filling of metal gates, which adds the filling capacity of metal gates, and makes making metal gates Technique becomes simple.Meanwhile production method of the invention performance compatible with high k dielectric layer/metal gate process is good, in NFET and Polysilicon gate extremely dummy gate structure in PFET regions, so doping situation can be adjusted freely.

The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art Member is it is understood that the invention is not limited in above-described embodiment, teaching according to the present invention can also be made more kinds of Variants and modifications, these variants and modifications are all fallen within scope of the present invention.

Claims (9)

1. a kind of production method of semiconductor devices, including:
Semiconductor substrate is provided;
Grid oxic horizon, dummy gate material layer and hard mask layer are sequentially formed on the semiconductor substrate,
Wherein, doping process is performed while the dummy gate material layer is formed, so that the dummy gate material layer Doping concentration is gradually reduced from bottom to top;
The hard mask layer and the dummy gate material layer are etched, to form the first dummy gate, wherein different levels of doping First dummy gate there is different oxidations rate;
Perform oxidation technology, first dummy gate of oxidized portion is to form from bottom to top gradually thinning oxide layer;
The oxide layer is removed, to form the second dummy gate wide at the top and narrow at the bottom;
Sidewall structure is formed in the both sides of second dummy gate;
Interlayer dielectric layer is formed on the semiconductor substrate, performs flatening process to expose second dummy gate.
2. according to the method described in claim 1, described the is removed after planarisation step it is characterized in that, being additionally included in and performing Two dummy gates and the grid oxic horizon below second dummy gate are to form the step of metal gates groove Suddenly.
3. according to the method described in claim 2, it is characterized in that, it is additionally included in be formed after the metal gates groove in institute State and the step of high k dielectric layer and metal gate layers are to form metal gates is filled in metal gates groove.
4. according to the method described in claim 1, it is characterized in that, using described in doping process in situ or injection technology execution Adulterate step.
5. according to the method described in claim 1, it is characterized in that, be additionally included in the source that performs after the oxidation technology that performs/ The step of leaking expansion area injection.
6. according to the method described in claim 1, it is characterized in that, be additionally included in the source that formed that to be formed after the sidewall structure/ The step of drain electrode.
7. according to the method described in claim 1, walked it is characterized in that, performing the etching using anisotropic etch process Suddenly.
8. according to the method described in claim 1, it is characterized in that, the oxide layer is removed using diluted hydrofluoric acid.
9. a kind of semiconductor devices, it is characterised in that the semiconductor devices is included using such as either one in claim 1-8 The metal gate structure of method manufacture, the metal gate structure is metal gate structure wide at the top and narrow at the bottom.
CN201410051810.XA 2014-02-14 2014-02-14 A kind of semiconductor devices and preparation method thereof CN104851802B (en)

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Citations (2)

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Publication number Priority date Publication date Assignee Title
CN1400653A (en) * 2001-08-03 2003-03-05 旺宏电子股份有限公司 Method for preventing formation of polysilicon longitudinal beam in internal storage component
CN102956454A (en) * 2011-08-19 2013-03-06 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof

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US8076735B2 (en) * 2009-10-02 2011-12-13 United Microelectronics Corp. Semiconductor device with trench of various widths

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1400653A (en) * 2001-08-03 2003-03-05 旺宏电子股份有限公司 Method for preventing formation of polysilicon longitudinal beam in internal storage component
CN102956454A (en) * 2011-08-19 2013-03-06 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof

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