JP5119604B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a structure using silicon germanium embedded beside a gate as a source / drain.

  In a semiconductor device including a MOS transistor, a technique for improving carrier mobility by applying stress to a silicon substrate is actively used. As one of such techniques, for example, in a p-type MOS transistor (PMOS), a silicon germanium (SiGe) layer having a lattice constant larger than that of silicon (Si) is used as the source / drain (S / D) of the transistor. A method of applying stress to the channel region formed by epitaxial growth has been proposed (for example, see Non-Patent Document 1 below).

  In manufacturing the semiconductor device having such a configuration, for example, the following steps are performed according to the flowchart of FIG. 7 as follows. First, an element isolation region is formed on the surface side of the silicon substrate, and a gate electrode having an offset insulating film provided thereon is formed through the gate insulating film so as to cross over the active region isolated in the element isolation region. Insulating sidewalls are formed on these sidewalls (step S201). The process up to this point is performed in the same manner as in a normal MOS process.

  Then, after covering the area other than the PMOS area with a resist pattern, so-called recess etching is performed in which the silicon substrate portion exposed to the active area in the PMOS area is dug by etching using the resist pattern and the offset insulating film and sidewalls as a mask ( Step S202). Next, the resist pattern is removed by ashing (step S203). Thereafter, cleaning using a mixed chemical solution of sulfuric acid and hydrogen peroxide (so-called SH cleaning) is performed (step S204), and further cleaning using a mixed chemical solution of ammonia and hydrogen peroxide (so-called SC-1 cleaning) is performed (step S204). S205). Next, overetching is performed to remove the damage caused by the recess etching in step S202 by using dilute hydrofluoric acid (DHF) together with a natural oxide film generated by ashing or subsequent cleaning (step S206).

  After the above, an S / D is formed by epitaxially growing a SiGe layer on the surface etched by recess etching and overetched (step S207).

P. Bai et al., “A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57μm2 SRAM Cell”, Institute of Electrical and Electronics Engineers (IEEE), nternational Electron Devices Meeting ( IEDM), December 2004, p.657-660

  In the manufacturing method as described above, dilute hydrofluoric acid (DHF) is used as a pretreatment for epitaxially growing the SiGe layer to form the S / D, in a process for removing the recess etching damage together with the natural oxide film. Over-etching is performed (FIG. 7, step S206). However, the damage generated during the recess etching often reaches a deeper position than the natural oxide film. For this reason, even if the natural oxide film is etched with dilute hydrofluoric acid, damage at a deeper position than the natural oxide film cannot be removed, and the damaged layer remains on the surface on which the SiGe layer is epitaxially grown, resulting in a good crystalline state. The SiGe layer cannot be epitaxially grown.

  Further, dilute hydrofluoric acid (DHF) has a very high etching rate with respect to a silicon oxide film formed by a deposition film forming method such as a CVD method, and has an etching rate of a silicon oxide film grown by an oxidation process such as a thermal oxide film. 5 to 7 times that of 1. For this reason, in the above-described step S206, while the natural oxide film is removed, the element isolation and the etching of the silicon oxide film constituting the sidewall proceed excessively, and the processed shape of the device deteriorates. In order to prevent this, if the amount of overetching with dilute hydrofluoric acid is reduced, the natural oxide film cannot be removed, and the epitaxial growth of the SiGe layer becomes difficult.

  Therefore, the present invention can sufficiently remove the damage caused by the recess etching without deteriorating the processing shape of the device, thereby sufficiently epitaxially growing the SiGe layer having a good crystalline state on the etched surface obtained by recess etching the silicon substrate. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can be made to operate.

In order to achieve such an object, the semiconductor device manufacturing method of the present invention sequentially performs the following steps. First, in the first step, a gate electrode is formed on a silicon substrate via a gate insulating film. Next, in a second step, a resist pattern having a shape that opens a portion where the silicon substrate is dug is formed on the silicon substrate. Thereafter, in a third step, the surface layer of the silicon substrate is dug down by etching using the gate electrode and the resist pattern as a mask. Thereafter, in a fourth step, an oxide film is grown on the surface of the dug silicon substrate by an oxidation process including an ashing process . In the next fifth step, the oxide film is removed by a surface gas etching reaction in which a process of supplying hydrofluoric acid gas and ammonia gas and a subsequent heat treatment are performed. Then, in the sixth step after repeating the oxidation process by the wet process to grow the oxide film and the fifth process of removing the oxide film twice or more, the oxide film in the fifth process A silicon germanium (SiGe) layer is epitaxially grown on the surface from which is removed.

In the method of manufacturing a semiconductor device having such a configuration, after the recess etching ( third step) for etching and etching the surface of the silicon substrate using the gate electrode as a mask, the surface of the etched silicon substrate is oxidized ( fourth step). And the removal of the oxide film grown by this oxidation treatment ( fifth step) is repeated two or more times. Thereby, even if the damage caused by the etching in the third step has reached a deep position, the damage can be completely removed by repeating the growth and removal of the oxide film.

Moreover, in the surface gas etching reaction performed as the removal of the oxide film ( fifth step), the etching rate of the deposited silicon oxide is slower than the etching rate of the silicon oxide grown by the oxidation treatment. Therefore, the silicon oxide film deposited on the silicon substrate is not excessively etched, and the processed shape of the device is favorably maintained.

  As described above, according to the method of manufacturing a semiconductor device of the present invention, it is possible to sufficiently remove the damage caused by the recess etching while maintaining the processed shape of the device. In addition, it is possible to sufficiently epitaxially grow a SiGe layer having a good crystalline state. As a result, a semiconductor device in which the channel region is distorted by the SiGe layer and the carrier mobility is sufficiently improved can be realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In each embodiment, a method for manufacturing a semiconductor device will be described based on cross-sectional process diagrams of FIGS. 2 to 4 and further using respective flowcharts showing process steps characteristic to each embodiment.

<First Embodiment>
In the first embodiment, the manufacturing method will be described using the cross-sectional process diagrams of FIGS. 2 to 4 in the order of steps S1 to S9 in the flowchart of FIG.

  First, in step S1, components such as a gate electrode are formed on the surface side of the silicon substrate.

  In this case, first, as shown in FIG. 2A, a silicon substrate 1 made of single crystal silicon is prepared, and an element isolation 3 is formed on the surface side thereof. At this time, for example, a trench is formed on the surface side of the silicon substrate 1, and an element isolation 3 having an STI (shallow trench isolation) structure in which an insulating film is buried in the trench is formed. For example, a silicon oxide film (hereinafter referred to as HDP film) deposited by HDP (high density plasma) -CVD (chemical vapor deposition) is used as the insulating film filling the trench.

  Next, the gate electrode 7 made of polysilicon is patterned through the gate insulating film 5 so as to cross over the active region 1a of the silicon substrate 1 separated by the element isolation 3. At this time, the material films constituting the gate insulating film 5, the gate electrode 7, and the offset insulating film 9 are stacked so that the offset insulating film 9 is provided on the gate electrode 7. Pattern etching is performed.

  Next, insulating sidewalls 11 are formed on the sidewalls of the gate insulating film 5, the gate electrode 7, and the offset insulating film 9. The sidewall 11 is formed as a three-layer structure including a TEOS film 11-1, a silicon nitride film 11-2, and a TEOS film 11-3. Here, the TEOS film 11-1 is a silicon oxide film deposited by a CVD method using a TEOS (tetraethoxy silane) gas.

  In order to form the sidewall 11 having such a three-layer structure, first, a TEOS film 11-1 and a silicon nitride film 11-2 are sequentially formed so as to cover the offset insulating film 9 and the subsequent layers. Next, the silicon nitride film 11-2 and the underlying TEOS film 11-1 are etched back until the silicon substrate 1 is exposed. Thereafter, a TEOS film 11-3 is further formed in a state of covering the offset insulating film 9, the TEOS film 11-1 and the silicon nitride film 11-2 left on the sidewall after the etch back, and until the silicon substrate 1 is exposed. The TEOS film 11-3 is etched back. As a result, the sidewall 11 having the illustrated three-layer structure is obtained.

  Next, in step S2, recess etching is performed to dig up the surface of the silicon substrate.

  In this case, first, as shown in FIG. 2B, a resist pattern 21 is formed on the silicon substrate 1 so as to expose the PMOS region 1p and cover other regions such as the NMOS region 1n.

  Then, recess etching for digging the surface layer of the silicon substrate 1 is performed by etching using the resist pattern 21 and the offset insulating film 9 on the gate electrode 7 and the sidewall 11 in the PMOS region 1p as a mask (FIG. 4, step S2). . In this recess etching, isotropic etching is performed so that the dug pattern 23 is extended to the lower side of the sidewall 11.

  Next, in step S3, as shown in FIG. 2C, a process of removing the resist pattern 21 from the upper part of the silicon substrate 1 is performed. Here, the resist pattern 21 is removed by an ashing process.

  Next, in step S4, cleaning using a mixed chemical solution of sulfuric acid and hydrogen peroxide (so-called SH cleaning) is performed as cleaning after the ashing process described above, and in step S5, a mixed chemical solution of ammonia and hydrogen peroxide is used. Cleaning using so-called SC-1 cleaning is performed.

  The series of resist pattern removal and cleaning processes shown in steps S3 to S4 as described above all act as an oxidation process for oxidizing the silicon substrate 1. As a result of these oxidation treatments, an oxide film (silicon oxide film) 25 grows on the bottom surface of the dug pattern 23.

Thereafter, in step S6, as shown in FIG. 3 (4), the oxide film 25 grown on the bottom surface of the dug pattern 23 is supplied with hydrofluoric acid (HF) gas and ammonia (NH ₃ ) gas. And a surface gas etching reaction (Chemical Oxide Remover: COR) for performing a subsequent heat treatment.

In the COR process, first, HF / NH ₃ gas is introduced into the first processing chamber, and an oxide film formed on the surface of the silicon substrate 1 is etched by a chemical reaction by these gases.

The process conditions in the first processing chamber at this time are as follows.
Processing chamber pressure: 1.3 to 4.0 Pa
HF flow rate: 10-50 sccm
NH ₃ flow rate: 10 to 50 sccm
Ar (carrier gas) flow rate: 50-100 sccm
Substrate temperature: 20-40 ° C

After the above treatment, a film altered by the reaction between the HF / NH ₃ gas and the oxide film remains on the etched surface.

Therefore, the silicon substrate 1 processed with the above-described HF / NH ₃ gas is immediately transferred into the second processing chamber and is thermally processed in a non-oxidizing atmosphere. As a result, the altered film remaining on the surface of the silicon substrate 1 is sublimated and removed. Then, the oxide film 25 grown on the exposed surface of the silicon substrate 1 (the bottom surface of the dug pattern 23) is removed by such chemical reaction by gas supply and sublimation removal of the altered film by heat treatment.

The process conditions in the second processing chamber at this time are as follows.
Atmosphere in processing chamber: N ₂
Processing chamber pressure: 66-93 Pa
Substrate temperature: 100-200 ° C

  In the oxide film removal by the series of COR processes as described above, the etching rate of the deposited silicon oxide is slower than the etching rate of the silicon oxide grown by the oxidation treatment. For example, when the etching amount of the thermal oxide film is 1, the etching amount of the TEOS film is about 0.5 to 1.0. On the other hand, in wet etching using dilute hydrofluoric acid (DHF), the etching amount of the TEOS film is about 5 to 7 when the etching amount of the thermal oxide film is 1.

  Next, in step S7, it is determined whether or not the COR process performed in the previous step S6 is the first time.

  If it is determined to be the first time (Yes), the process returns to the oxidation process, and as shown in FIG. 3 (5), the oxide film 27 is grown again on the bottom surface of the dug pattern 23 by the oxidation process. Perform the process. At this time, for example, the process may return to the ashing process in step S3, and the oxide film 27 may be further grown by performing steps S4 and S5, or the process may return to the SH cleaning in step S4.

  Thereafter, the step of removing the oxide film by the COR process in step S6 is performed again. As a result, as shown in FIG. 3 (6), the oxide film 27 grown by re-oxidation is removed to expose the silicon substrate 1 on the bottom surface of the dug pattern 23.

  Thereafter, in step S7, it is determined that the previous COR process is not the first time (No), and the process proceeds to the next step S8. In step S8, it is determined whether or not the damage on the bottom surface of the dug pattern has been removed. Here, the number of times that the damage applied to the bottom surface of the dug pattern by the recess etching in Step S2 is removed by repeating Steps S3 (or Step S4) to Step S6 is experimentally obtained in advance. It may be determined that the damage has been removed when the required number of times has been repeated.

  In step S8, the process returns to step S3 (or step S4) until step S8 is repeated until it is determined that the damage is removed, and the process is repeated until step S8. If the damage is removed (Yes), the process proceeds to the next step S9. move on.

  Thereafter, in step S9, as shown in FIG. 4, the SiGe layer 29 is epitaxially grown in the dug pattern 23 from which the oxide film (27) has been removed by the COR process, thereby forming the source / drain (S / D). At this time, a cover film for preventing the formation of the SiGe layer in another region is provided as necessary.

  As described above, after epitaxially growing the S / D made of the SiGe layer 29 on the surface side of the silicon substrate 1, a compressive stress was applied to the channel region by introducing p-type impurities into the S / D. A PMOS 31 is obtained. Here, an N-type MOS transistor can be obtained by introducing an n-type impurity into the S / D instead of the p-type impurity.

  According to the above manufacturing method, after the recess etching (S2) in which the surface of the silicon substrate 1 described with reference to FIG. 2 (2) is etched and dug, as shown in FIGS. 2 (3) to 3 (6). The structure is such that the oxidation process of the surface of the silicon substrate 1 dug down and the removal of the oxide film grown by this oxidation process are repeated twice or more. Thereby, even if the damage caused by the recess etching reaches a deep position, the damage can be completely removed by repeating the growth and removal of the oxide film.

  Moreover, in the COR process (surface gas etching reaction) performed as the removal of the oxide film (S6), the etching rate of the silicon oxide deposited as described above is higher than the etching rate of the silicon oxide grown by the oxidation treatment. slow. Therefore, the sidewall 11 and the element isolation 3 using the silicon oxide film deposited on the silicon substrate 1 are not excessively etched in the oxide film removing step (S6), and the device is processed. Good accuracy can be maintained.

  From the above, according to the manufacturing method of the first embodiment, it is possible to sufficiently remove the damage caused by the recess etching while maintaining the processed shape of the device, whereby the etched surface where the silicon substrate 1 is recess-etched. It becomes possible to sufficiently epitaxially grow the SiGe layer 29 having a good crystalline state. As a result, it is possible to realize a semiconductor device (PMOS 31) in which the channel region is distorted by the SiGe layer 29 formed as S / D and the carrier mobility is sufficiently improved.

Second Embodiment
FIG. 5 is a flowchart for explaining the manufacturing method of the second embodiment. The manufacturing method of the second embodiment shown in this figure is different from the manufacturing method of the first embodiment described with reference to the flowchart of FIG. 1 in that the second and subsequent oxidation treatments are changed to ozone treatment. Other procedures are the same as those in the first embodiment.

  That is, steps S1 to S6 in FIG. 5 are performed in the same manner as in the first embodiment described above. Thereafter, when it is determined in step S7 that the previous COR process is the first time (Yes), and in the next step S8, it is determined that damage on the bottom surface of the dug pattern has not been removed (No). Advances to step S10.

In step S10, an oxidation process using, for example, ozone (O ₃ ) is performed. Thereby, as shown in FIG. 3 (5), the step of growing the oxide film 27 on the bottom surface of the dug pattern 23 is performed again. Here ozone (O ₃₎ as an oxidizing treatment with the wet treatment, ozone (O ₃₎ exposing the bottom surface of the ozone (O ₃₎ a dug purely ozone water by dissolving pattern 23 plasma cleaning, more ozone It may be an oxidation process for supplying (O ₃ ) vapor.

In step S10, instead of the oxidation treatment using ozone (O ₃ ), RIE (Reactive Ion Etching) using oxygen gas (O ₂ ) or hydrochloric acid / hydrogen peroxide mixture (SC-2) is used. The used wet treatment may be performed.

  Thereafter, the step of removing the oxide film by the COR process in step S6 is performed again. As a result, as shown in FIG. 3 (6), the oxide film 27 grown by re-oxidation is removed to expose the silicon substrate 1 on the bottom surface of the dug pattern 23.

Hereinafter, the oxidation process using ozone (O ₃ ) in step S10 and the removal of the oxide film by the COR process in step S6 are performed until it is determined in step S8 that the damage on the bottom surface of the dug pattern has been removed (Yes). repeat. If the damage is removed in step S8 (Yes), the process proceeds to the next step S9.

  In step S9, as in the first embodiment, as shown in FIG. 4, the SiGe layer 29 is epitaxially grown to form the source / drain (S / D), and a p-type impurity is further introduced into the S / D. As a result, a PMOS 31 in which compressive stress is applied to the channel region is obtained. Here, an N-type MOS transistor can be obtained by introducing an n-type impurity into the S / D instead of the p-type impurity.

  Even in the manufacturing method of the second embodiment described above, after the recess etching (S2) for etching and digging the surface of the silicon substrate 1 described with reference to FIG. 2 (2), FIG. 2 (3) to FIG. As shown in (6), the oxidation treatment of the surface of the silicon substrate 1 dug down and the removal of the oxide film grown by this oxidation treatment by the COR process are repeated twice or more. For this reason, it is possible to completely remove the damage caused by the recess etching as in the first embodiment, and it is possible to maintain the device processing accuracy satisfactorily. As in the first embodiment, a semiconductor device (PMOS 31) in which the channel region is distorted by the SiGe layer 29 formed as S / D and the carrier mobility is sufficiently improved can be realized.

  Furthermore, in the manufacturing method according to the second embodiment, the wet process is selected in the oxidation process (S10), so that the oxidation process is uniformly performed on the entire surface of the silicon substrate 1 without depending on the density of the pattern to be oxidized. It becomes possible to do. In addition, by appropriately selecting the oxidation treatment method in the oxidation treatment (S10), it is possible to adjust the number of repetitions of the oxidation treatment (S10) and the oxide film removal (S6) necessary for removing damage caused by the recess etching. It is.

<Third Embodiment>
FIG. 6 is a flowchart for explaining the manufacturing method according to the third embodiment. The manufacturing method of the third embodiment shown in this figure is different from the manufacturing method of the second embodiment described with reference to the flowchart of FIG. 5 in the step of removing the resist after the recess etching in step S2. The procedure is the same as in the second embodiment.

  That is, as resist removal after step S2, SH spin cleaning using a mixed chemical solution of sulfuric acid and hydrogen peroxide in step S4 ′ and SC-1 using a mixed chemical solution of ammonia and hydrogen peroxide in step S5 ′. Perform spin cleaning. In the cleaning using these chemical solutions, the effect of removing the resist is improved by adopting a single-type spin cleaning.

  Then, after the resist removal by the continuous spin cleaning in the above step S4 ′ and the subsequent step S5 ′, steps 6 to S10 are performed in the same manner as described in the second embodiment, and finally in step S9. The S / D is formed by epitaxially growing the SiGe layer.

  Even in the manufacturing method of the third embodiment described above, after the recess etching (S2) for etching and etching the surface of the silicon substrate 1 described with reference to FIG. 2 (2), FIG. 2 (3) to FIG. As shown in (6), the oxidation treatment of the surface of the silicon substrate 1 dug down and the removal of the oxide film grown by this oxidation treatment by the COR process are repeated twice or more. For this reason, it is possible to completely remove the damage caused by the recess etching as in the first embodiment, and it is possible to maintain the device processing accuracy satisfactorily. As in the first embodiment, a semiconductor device (PMOS 31) in which the channel region is distorted by the SiGe layer 29 formed as S / D and the carrier mobility is sufficiently improved can be realized.

  Furthermore, in the manufacturing method according to the third embodiment, the wet process is selected in the oxidation process (S10), so that the oxidation process is uniformly performed on the entire surface of the silicon substrate 1 without depending on the density of the pattern to be oxidized. In addition, by appropriately selecting an oxidation treatment method in the oxidation treatment (S10), an oxidation treatment (S10) and an oxide film removal (S6) necessary for removing damage caused by the recess etching are selected. It is possible to adjust the number of repetitions of ()) in the same manner as in the second embodiment.

  Further, in the manufacturing method of the third embodiment, since the resist removal is also performed only by the wet process, the effect of the resist removal and the effect of the oxidation process in this step are obtained on the entire surface of the silicon substrate 1 by the pattern density. It is possible to obtain evenly without depending on.

  In the manufacturing method of the third embodiment, in this step S10, batch type SH cleaning and batch type SC-1 spin cleaning may be performed in this order.

Furthermore, in the manufacturing method of the third embodiment, when it is determined that the first time is determined in Step S7 (Yes), and further, it is determined in Step S8 that the damage is not removed (No), You may return to S4 '. Then, instead of the oxidation treatment with ozone (O ₃ ) in step S10, SH spin cleaning S4 ′ and SC-1 spin cleaning S5 ′ may be performed in this order.

3 is a flowchart showing a method for manufacturing the semiconductor device of the first embodiment. It is sectional drawing (the 1) explaining the manufacturing method of the semiconductor device of embodiment. FIG. 6 is a cross-sectional process diagram (part 2) illustrating the method for manufacturing the semiconductor device of the embodiment. It is sectional process drawing (the 3) explaining the manufacturing method of the semiconductor device of embodiment. It is a flowchart which shows the manufacturing method of the semiconductor device of 2nd Embodiment. 10 is a flowchart illustrating a method for manufacturing a semiconductor device according to a third embodiment. It is a flowchart which shows the conventional method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 3 ... Element isolation (HDP film), 5 ... Gate insulating film, 7 ... Gate electrode, 11 ... Side wall, 11-1 ... TEOS film, 11-3 ... TEOS film, 21 ... Resist pattern, 25 , 27 ... oxide film, 29 ... SiGe layer, 31 ... PMOS

Claims (4)

A first step of forming a gate electrode on a silicon substrate via a gate insulating film;
A second step of forming on the silicon substrate a resist pattern having a shape that opens a portion where the silicon substrate is dug down;
A third step of digging a surface layer of the silicon substrate by etching using the gate electrode and the resist pattern as a mask;
A fourth step of growing an oxide film on the surface of the dug down silicon substrate by oxidation treatment;
A fifth step of removing the oxide film by a surface gas etching reaction in which a treatment for supplying hydrofluoric acid gas and ammonia gas and a subsequent heat treatment are performed;
A sixth step of epitaxially growing a silicon germanium layer on the surface from which the oxide film has been removed after repeating the fourth step and the fifth step twice or more;
Wherein in the fourth step after the third step, have rows removal process of the resist pattern by the oxidation process including ashing,
Wherein in the fourth step after the fifth step, the method of manufacturing a semiconductor device, characterized in that intends row the oxidation treatment in a wet processing. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the fourth step and the fifth step are repeated until damage to the surface layer of the silicon substrate caused by the etching in the third step is removed. In the manufacturing method of the semiconductor device according to claim 1,
Prior to the third step, a step of forming a sidewall on the side wall of the gate electrode using a deposited silicon oxide film is performed. In the manufacturing method of the semiconductor device according to claim 1,
Prior to the first step, a step of forming element isolation on the surface side of the silicon substrate using a deposited silicon oxide film is performed.

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