CN102097356A - Method for making shallow trench isolation structure - Google Patents
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- CN102097356A CN102097356A CN 200910201189 CN200910201189A CN102097356A CN 102097356 A CN102097356 A CN 102097356A CN 200910201189 CN200910201189 CN 200910201189 CN 200910201189 A CN200910201189 A CN 200910201189A CN 102097356 A CN102097356 A CN 102097356A
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- insulating oxide
- shallow trench
- isolation structure
- oxide
- plough groove
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Abstract
The invention discloses a method for making a shallow trench isolation structure, which comprises the following steps of: providing a semiconductor substrate on which a pad oxide layer and a corrosion blocking layer are sequentially formed, wherein a shallow trench is formed in the semiconductor substrate; forming a lining oxide layer on the inner wall of the shallow trench; fully filling a first insulating oxide layer and a second insulating oxide layer into the shallow trench; performing an annealing process; filling a third insulating oxide layer into the shallow trench to the predetermined height; and removing the corrosion blocking layer and the pad oxide layer to form the shallow trench isolation structure. Hollowness generated on the shallow trench isolation structure is extremely small, and the depth of the hollowness is less than 50 angstroms, so the performance of a semiconductor device is not affected.
Description
Technical field
The present invention relates to the making field of semiconductor device, relate in particular to the manufacture method of fleet plough groove isolation structure.
Background technology
Along with reducing of integrated circuit size, the device of forming circuit must be placed more thick and fast, to adapt to the confined space available on the chip.Because present research is devoted to increase the density of active device on the unit are of Semiconductor substrate, becomes more important so the effective insulation between circuit is isolated.
Shallow trench isolation has multinomial technology and electrical isolation advantage from (STI) technology, comprises reducing the integrated level that the area that takies crystal column surface increases device simultaneously, keeps surface flatness and less channel width erosion etc.Therefore, the following element of present 0.18 μ m for example the active area isolation layer of MOS circuit adopt shallow ditch groove separation process to make mostly.Concrete processing step is as follows:
With reference to figure 1, on Semiconductor substrate 100, form pad oxide 102, the method that forms pad oxide 102 is a thermal oxidation method, the material of pad oxide 102 is specially silicon dioxide; Form corrosion barrier layer 104 with Low Pressure Chemical Vapor Deposition on pad oxide 102, the pad oxide 102 that is used for below the protection of subsequent etching process is avoided corrosion, and wherein the material of corrosion barrier layer 104 is a silicon nitride etc.; Then, on corrosion barrier layer 104, form photoresist layer (not shown),, on photoresist layer, form and follow-up shallow trench corresponding opening through overexposure, developing process with spin-coating method; With the photoresist layer is mask, via opening, with dry etching method etching corrosion barrier layer 104 and pad oxide 102 to exposing Semiconductor substrate 100; After removing photoresist layer with ashing method, be mask with corrosion barrier layer 104 and pad oxide 102, with dry etching method etching semiconductor substrate 100, form shallow trench 106.
With reference to figure 2, adopt the Semiconductor substrate silicon in the thermal oxidation method oxidation shallow trench 106, form lining oxide layer 108, the material of described lining oxide layer 108 is a silicon dioxide; Then, by using high density plasma CVD method (HDPCVD) or high-aspect-ratio technology (HARP, High Aspect RatioProcess) on corrosion barrier layer 104, forms insulating oxide 110, and with the full shallow trench 106 of insulating oxide 110 fillings, described insulating oxide layer material preferred oxygen silicon.
As shown in Figure 3, after having deposited insulating oxide 110, insulating oxide 110 is not smooth, and insulating oxide 110 is carried out planarization to exposing corrosion barrier layer 104, as adopting the insulating oxide 110 on the CMP (Chemical Mechanical Polishing) process removing corrosion barrier layer 104; Remove corrosion barrier layer 104 and pad oxide 102 with wet etching method, form fleet plough groove isolation structure 120.
Existing shallow trench isolation from manufacture method specifically to please refer to application number be described in 200410057166 the disclosed technical scheme of Chinese patent application.
But, along with the semiconductor device integrated level is more and more higher, it is imperfect that the shallow trench that adopts high density plasma CVD method (HDPCVD) to fill high-aspect-ratio more and more is easy to generate filling, produce the possibility in hole and slit therein, met with serious challenge for making complete shallow trench.Therefore, in order to address the above problem, adopt high-aspect-ratio technology (HARP, High Aspect Ratio Process) under inferior condition of normal pressure, to fill shallow trench, high-aspect-ratio technology divided for three steps shallow trench was filled usually, avoided producing in the shallow trench defectives such as hole and slit.
Yet, because the gas flow ratio difference that three step depositions of high-aspect-ratio technology adopt, finish in deposition, after carrying out annealing process, divide the shrinkage rates of the insulating oxide that three steps filled also can be different, the insulating oxide surface irregularity after can causing filling be through producing the depression of the degree of depth greater than 230 dusts on fleet plough groove isolation structure after the CMP (Chemical Mechanical Polishing) process, this defective can be amplified by follow-up acid tank etch process, and then influences the unfailing performance of device.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method of fleet plough groove isolation structure, prevents to produce on the fleet plough groove isolation structure depression.
For addressing the above problem, the invention provides a kind of manufacture method of fleet plough groove isolation structure, comprising: the Semiconductor substrate that is formed with pad oxide and corrosion barrier layer successively is provided, wherein is formed with shallow trench in the Semiconductor substrate; Form lining oxide layer at the shallow trench inwall; In shallow trench, fill first insulating oxide and second insulating oxide, and shallow trench is filled full; Carry out annealing process; In shallow trench, fill the 3rd insulating oxide and shallow trench is filled to predetermined altitude; Remove corrosion barrier layer and pad oxide, form fleet plough groove isolation structure.
Optionally, described annealing process is rapid thermal annealing or furnace annealing or laser annealing.
Optionally, described annealing temperature is smaller or equal to 1100 ℃, and annealing time is more than or equal to 30 minutes.
Optionally, described method of filling first insulating oxide and second insulating oxide in shallow trench is a high-aspect-ratio technology.
Optionally, the material of described first insulating oxide, second insulating oxide, the 3rd insulating oxide is siliceous oxide.
Optionally, described formation first insulating oxide adopts inferior aumospheric pressure cvd, and the gas of reaction is O
3And TEOS, its flow-rate ratio is greater than 20: 1.
Optionally, described formation second insulating oxide adopts inferior aumospheric pressure cvd, and reacting gas is O
3And TEOS, its flow-rate ratio is greater than 10: 1.
Optionally, described formation the 3rd insulating oxide adopts highdensity plasma chemical vapor deposition, and employed gas is SiH4 and O2, and its flow-rate ratio is less than 1: 2.
Compared with prior art, the present invention has the following advantages: deposited second insulating oxide in shallow trench after, carry out annealing process, make the surfacing of first insulating oxide and second insulating oxide, density improves.
Further, when subsequent deposition the 3rd insulating oxide, employing be the high density plasma CVD method, the film quality of the method growth is relatively good, does not need to carry out annealing process.Avoid different final the 3rd insulating oxide surface irregularities that cause of shrinkage rates like this owing to each insulating oxide, after CMP (Chemical Mechanical Polishing) process, it is minimum to produce depression on fleet plough groove isolation structure, and the degree of depth can not influence performance of semiconductor device less than 50 dusts.
Description of drawings
Fig. 1 to Fig. 3 is the existing schematic diagram that forms fleet plough groove isolation structure;
Fig. 4 the present invention forms the embodiment flow chart of fleet plough groove isolation structure;
Fig. 5 to Figure 10 is the embodiment schematic diagram that the present invention forms fleet plough groove isolation structure.
Embodiment
When prior art forms fleet plough groove isolation structure, because the gas flow ratio difference that three step depositions of high-aspect-ratio technology adopt, finish in deposition, after carrying out annealing process, the shrinkage rates of the insulating oxide that three steps of branch fill also can be different, insulating oxide surface irregularity after can causing filling produces the depression of the degree of depth greater than 230 dusts on fleet plough groove isolation structure after the process CMP (Chemical Mechanical Polishing) process, and then can cause device reliability energy variation.
The present invention improves technology, idiographic flow as shown in Figure 4, execution in step S101 provides the Semiconductor substrate that is formed with pad oxide and corrosion barrier layer successively, wherein is formed with shallow trench in the Semiconductor substrate; Execution in step S102 forms lining oxide layer at the shallow trench inwall; Execution in step S103 fills first insulating oxide and second insulating oxide in shallow trench, and shallow trench is filled full; Execution in step S104 carries out annealing process; Execution in step S105 fills the 3rd insulating oxide and shallow trench is filled to predetermined altitude in shallow trench; Execution in step S106 removes corrosion barrier layer and pad oxide, forms fleet plough groove isolation structure.
The present invention carries out annealing process deposited second insulating oxide in shallow trench after, make the surfacing of first insulating oxide and second insulating oxide, and density improves.When subsequent deposition the 3rd insulating oxide, avoid different final the 3rd insulating oxide surface irregularities that cause of shrinkage rates owing to each insulating oxide, after CMP (Chemical Mechanical Polishing) process, it is minimum to produce depression on fleet plough groove isolation structure, the degree of depth can not influence performance of semiconductor device less than 50 dusts.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fig. 5 to Figure 10 is the embodiment schematic diagram that the present invention forms fleet plough groove isolation structure.As shown in Figure 5, provide Semiconductor substrate 200, described Semiconductor substrate 200 can be semi-conducting materials such as silicon, germanium or silicon-on-insulator; Form pad oxide 202 on Semiconductor substrate 200, the method that forms pad oxide 202 is a thermal oxidation method, and the material of pad oxide 202 is specially silicon dioxide; On pad oxide 202, form corrosion barrier layer 204 with Low Pressure Chemical Vapor Deposition or plasma auxiliary chemical vapor deposition method; the pad oxide 202 that is used for below the protection of subsequent etch process is avoided corrosion; wherein the material of corrosion barrier layer 220 is a silicon nitride, generally adopts chemical vapour deposition technique to form.
Then, form photoresist layer (not shown) with spin-coating method on corrosion barrier layer 204, through technologies such as overexposure, developments, form opening on photoresist layer, the zone of aperture position correspondence is an isolated area, and all the other are active area; With the photoresist layer is mask, via opening, to exposing Semiconductor substrate 200, forms the zone of shallow trench with dry etching method etching corrosion barrier layer 204 and pad oxide 202 in advance; With corrosion barrier layer 204 is mask, and etching semiconductor substrate 200 forms shallow trench 206 to desired depth.
Except that present embodiment, can also be on corrosion barrier layer 204 form anti-reflecting layer with the plasma enhanced chemical vapor deposition method earlier, in order to preventing in the post-exposure process, prevent that the light reflection from causing exposure uneven and protect the rete below it to avoid the light influence; And then on anti-reflecting layer the spin coating photoresist layer.
As shown in Figure 6, remove photoresist layer with ashing method earlier, and then remove residual photoresist layer with the wet etching method; Semiconductor substrate 200 is put into vacuum reaction chamber, and aerating oxygen in reative cell forms lining oxide layer 208 at shallow trench 206 inwalls, and the material of described lining oxide layer 208 is a silicon dioxide.
Except that embodiment, also can feed nitrogen and oxygen simultaneously, form lining oxide layer 208.
In the present embodiment, the thickness of lining oxide layer 208 is 20 dusts～100 dusts.Its thickness is concrete because factors such as the flow decision of aerating oxygen.
As shown in Figure 7, with high-aspect-ratio technology (HARP, High Aspect Ratio Process) adopting chemical vapour deposition technique to form first insulating oxide 210 in shallow trench and on the corrosion barrier layer 204 under the inferior normal pressure, the material of described first insulating oxide 210 is a silicon dioxide, its thickness that is positioned on the corrosion barrier layer 204 is 500 dusts～800 dusts, but be not limited to this, concrete numerical value can correspondingly be made adjustment according to different depth-to-width ratios.
In the present embodiment, the gas that forms 210 employings of first insulating oxide is O
3(ozone) and TEOS (tetraethoxysilane), wherein O
3With the flow-rate ratio of TEOS be greater than 20: 1.
Continuation is with reference to figure 7, with high-aspect-ratio technology (HARP, High Aspect Ratio Process) on first insulating oxide 210 that adopts chemical vapour deposition technique under the inferior normal pressure in shallow trench and corrosion barrier layer 204, form second insulating oxide 212, and second insulating oxide 212 is filled full shallow trench; The material of described second insulating oxide 212 is a silicon dioxide, its thickness that is positioned on first insulating oxide 210 of corrosion barrier layer top is more than 1000 dusts, and final thickness need make second insulating oxide 212 in the shallow trench highly be positioned at the upper edge of corrosion barrier layer 220.
In the present embodiment, the gas that forms 212 employings of second insulating oxide is O
3(ozone) and TEOS (tetraethoxysilane), wherein O
3With the flow-rate ratio of TEOS be greater than 10: 1.
In the present embodiment, described inferior normal pressure is that atmospheric pressure is 50 holders～600 holders.
As shown in Figure 8, it is indoor 214 that the Semiconductor substrate 200 that will comprise shallow trench, is formed with insulating oxide is put into anneal chamber, carries out annealing process, makes the surfacing of first insulating oxide 210 and second insulating oxide 212, and density improves.When making subsequent deposition the 3rd insulating oxide, avoid different final the 3rd insulating oxide surface irregularities that cause of shrinkage rates owing to each insulating oxide, after CMP (Chemical Mechanical Polishing) process, it is minimum to produce depression on fleet plough groove isolation structure, and the degree of depth is less than 50 dusts.
In the present embodiment, annealing process is rapid thermal annealing or furnace annealing or laser annealing.Described annealing temperature is smaller or equal to 1100 ℃, and annealing time is greater than 30 minutes.
Present embodiment deposited second insulating oxide 212 in shallow trench after, carries out annealing process, makes the surfacing of first insulating oxide 210 and second insulating oxide 212, and density improves.
As shown in Figure 9, with Semiconductor substrate 200 from the indoor taking-up of anneal chamber; Form the 3rd insulating oxide 216 with highdensity plasma chemical vapor deposition on second insulating oxide 212, the material of described the 3rd insulating oxide 216 is a silicon dioxide, and its thickness on second insulating barrier 212 is more than 5000 dusts.
In the present embodiment, the gas that forms 216 employings of the 3rd insulating oxide is SiH
4And O
2, its flow-rate ratio is less than 1: 2.
Present embodiment adopts the high density plasma CVD method to form the 3rd insulating oxide 216, and the film quality of the method growth is relatively good, does not need to carry out annealing process.Avoid different final the 3rd insulating oxide 216 surface irregularities that cause of shrinkage rates like this owing to each insulating oxide.
With reference to Figure 10, after having deposited the 3rd insulating oxide 216, the 3rd insulating oxide 216 is not smooth, the 3rd insulating oxide 216, second insulating oxide 212 and first insulating oxide 210 are carried out planarization until exposing corrosion barrier layer 204, and described flatening process is chemical mechanical polishing method for example.Except that the foregoing description method, can also be to adopt chemical mechanical polishing method to be polished to the 3rd insulating oxide 216 surfaces to be a flat structures, to adopt etching technics to be etched to then and expose corrosion barrier layer 204 to the open air.
Continuation is removed corrosion barrier layer 204 and pad oxide 202 successively with reference to Figure 10, forms fleet plough groove isolation structure 220.The technology of removing corrosion barrier layer 204 for example adopts the wet etch method that contains the pentavalent hot phosphoric acid solution.The technology of removing pad oxide 202 generally also adopts wet etch method, for example adopts hydrofluoric acid solution to carry out etching.
Fleet plough groove isolation structure 220 surfacings of adopting the present embodiment method to form.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (8)
1. the manufacture method of a fleet plough groove isolation structure is characterized in that, comprising:
The Semiconductor substrate that is formed with pad oxide and corrosion barrier layer successively is provided, wherein is formed with shallow trench in the Semiconductor substrate;
Form lining oxide layer at the shallow trench inwall;
In shallow trench, fill first insulating oxide and second insulating oxide, and shallow trench is filled full; Carry out annealing process;
In shallow trench, fill the 3rd insulating oxide and shallow trench is filled to predetermined altitude;
Remove corrosion barrier layer and pad oxide, form fleet plough groove isolation structure.
2. the manufacture method of fleet plough groove isolation structure according to claim 1 is characterized in that, described annealing process is rapid thermal annealing or furnace annealing or laser annealing.
3. the manufacture method of fleet plough groove isolation structure according to claim 2 is characterized in that, described annealing temperature is smaller or equal to 1100 ℃, and annealing time is more than or equal to 30 minutes.
4. the manufacture method of fleet plough groove isolation structure according to claim 1 is characterized in that, described method of filling first insulating oxide and second insulating oxide in shallow trench is a high-aspect-ratio technology.
5. the manufacture method of fleet plough groove isolation structure according to claim 1 is characterized in that, the material of described first insulating oxide, second insulating oxide, the 3rd insulating oxide is siliceous oxide.
6. the manufacture method of fleet plough groove isolation structure according to claim 5 is characterized in that, described formation first insulating oxide adopts inferior aumospheric pressure cvd, and the gas of reaction is O
3And TEOS, its flow-rate ratio is greater than 20: 1.
7. the manufacture method of fleet plough groove isolation structure according to claim 5 is characterized in that, described formation second insulating oxide adopts inferior aumospheric pressure cvd, and reacting gas is O
3And TEOS, its flow-rate ratio is greater than 10: 1.
8. the manufacture method of fleet plough groove isolation structure according to claim 5 is characterized in that, described formation the 3rd insulating oxide adopts highdensity plasma chemical vapor deposition, and employed gas is SiH4 and O2, and its flow-rate ratio is less than 1: 2.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200910201189 CN102097356B (en) | 2009-12-15 | 2009-12-15 | Method for making shallow trench isolation structure |
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|---|---|---|---|
| CN 200910201189 CN102097356B (en) | 2009-12-15 | 2009-12-15 | Method for making shallow trench isolation structure |
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| CN102097356A true CN102097356A (en) | 2011-06-15 |
| CN102097356B CN102097356B (en) | 2013-03-27 |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102881626A (en) * | 2011-07-15 | 2013-01-16 | 中芯国际集成电路制造(上海)有限公司 | Shallow trench isolation structure and manufacturing method thereof |
| CN103199052A (en) * | 2013-04-09 | 2013-07-10 | 上海华力微电子有限公司 | Manufacturing method for shallow trench isolation structure |
| CN103489821A (en) * | 2013-09-29 | 2014-01-01 | 武汉新芯集成电路制造有限公司 | Method for filling groove with high aspect ratio |
| CN111933572A (en) * | 2020-10-10 | 2020-11-13 | 晶芯成(北京)科技有限公司 | Semiconductor structure and manufacturing method thereof |
| CN112366205A (en) * | 2020-11-09 | 2021-02-12 | 长江存储科技有限责任公司 | Semiconductor device and preparation method thereof |
| CN113223995A (en) * | 2021-04-25 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Method for forming shallow trench isolation structure |
| CN114334791A (en) * | 2020-09-30 | 2022-04-12 | 长鑫存储技术有限公司 | Semiconductor structure forming method and semiconductor structure |
| CN114334791B (en) * | 2020-09-30 | 2024-10-25 | 长鑫存储技术有限公司 | Method for forming semiconductor structure and semiconductor structure |
-
2009
- 2009-12-15 CN CN 200910201189 patent/CN102097356B/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102881626A (en) * | 2011-07-15 | 2013-01-16 | 中芯国际集成电路制造(上海)有限公司 | Shallow trench isolation structure and manufacturing method thereof |
| CN103199052A (en) * | 2013-04-09 | 2013-07-10 | 上海华力微电子有限公司 | Manufacturing method for shallow trench isolation structure |
| CN103489821A (en) * | 2013-09-29 | 2014-01-01 | 武汉新芯集成电路制造有限公司 | Method for filling groove with high aspect ratio |
| CN103489821B (en) * | 2013-09-29 | 2016-08-10 | 武汉新芯集成电路制造有限公司 | A kind of fill method of high aspect ratio trench quite |
| CN114334791A (en) * | 2020-09-30 | 2022-04-12 | 长鑫存储技术有限公司 | Semiconductor structure forming method and semiconductor structure |
| CN114334791B (en) * | 2020-09-30 | 2024-10-25 | 长鑫存储技术有限公司 | Method for forming semiconductor structure and semiconductor structure |
| CN111933572A (en) * | 2020-10-10 | 2020-11-13 | 晶芯成(北京)科技有限公司 | Semiconductor structure and manufacturing method thereof |
| CN112366205A (en) * | 2020-11-09 | 2021-02-12 | 长江存储科技有限责任公司 | Semiconductor device and preparation method thereof |
| CN113223995A (en) * | 2021-04-25 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Method for forming shallow trench isolation structure |
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|---|---|
| CN102097356B (en) | 2013-03-27 |
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