CN114420632A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN114420632A CN114420632A CN202210327828.2A CN202210327828A CN114420632A CN 114420632 A CN114420632 A CN 114420632A CN 202210327828 A CN202210327828 A CN 202210327828A CN 114420632 A CN114420632 A CN 114420632A
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- 238000000034 method Methods 0.000 title claims abstract description 73
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 230000008569 process Effects 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 37
- 238000000151 deposition Methods 0.000 claims abstract description 35
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 32
- 230000008021 deposition Effects 0.000 claims abstract description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 239000012495 reaction gas Substances 0.000 claims description 14
- 238000006243 chemical reaction Methods 0.000 claims description 10
- -1 fluorine ions Chemical class 0.000 claims description 8
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 230000009471 action Effects 0.000 claims description 5
- 229910052731 fluorine Inorganic materials 0.000 claims description 5
- 239000011737 fluorine Substances 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 229910000077 silane Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000007789 sealing Methods 0.000 abstract description 6
- 239000000463 material Substances 0.000 description 11
- 238000002955 isolation Methods 0.000 description 7
- 239000007789 gas Substances 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- WQLQSBNFVQMAKD-UHFFFAOYSA-N methane;silicon Chemical compound C.[Si] WQLQSBNFVQMAKD-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
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- Inorganic Chemistry (AREA)
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Abstract
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate, and forming a groove in the substrate; forming a first insulating layer by adopting a first high-density plasma chemical vapor deposition process, and covering the side wall and the bottom of the groove; etching to remove a part of the thickness of the first insulating layer; sequentially repeating the deposition step and the etching step of the first insulating layer until the first insulating layer is filled with the groove; and forming a second insulating layer by adopting a second high-density plasma chemical vapor deposition process. According to the invention, after a part of the first insulating layer is formed, the first insulating layer with a part of thickness is etched and removed to remove the overhang formed at the corner of the groove, and then the deposition step and the etching step of the first insulating layer are sequentially repeated until the groove is filled with the first insulating layer, so that the excessive overhang can be prevented to avoid sealing the groove, and thus, a cavity is prevented from being formed in the groove, and the electrical property of the semiconductor device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a semiconductor device.
Background
Shallow Trench Isolation (STI) is usually used to isolate active areas of semiconductor devices. As the semiconductor process enters the deep submicron era, the size of the shallow trench isolation structure is correspondingly reduced, the aspect ratio of the shallow trench isolation structure is increased, and in the process of forming the shallow trench isolation structure, in order to improve the filling property, High Density Plasma Chemical Vapor Deposition (HDPCVD) is generally adopted to fill the insulating material.
Fig. 1 to 4 illustrate a method for forming a shallow trench isolation structure in the prior art. As shown in fig. 1, a substrate 10 is provided, a first liner layer 11 and a hard mask layer 12 are sequentially formed on the substrate 10, the hard mask layer 12 is patterned, and the first liner layer 11 and the substrate 10 are etched by using the hard mask layer 12 as a mask to form a trench 13. Next, referring to fig. 2, a second liner layer 14 is formed, wherein the second liner layer 14 covers the sidewalls and the bottom of the trench 13 and covers the upper surface of the hard mask layer 12. Then, referring to fig. 3, the trench 13 is filled with an insulating material, and the trench 13 is filled at a lower deposition rate to form the first insulating layer 15, where the lower deposition rate can improve the filling degree of the trench 13 and avoid the occurrence of defects such as voids. Finally, referring to fig. 4, the trench 13 is completely filled with a faster deposition rate to form the second insulating layer 16, and the faster deposition rate can increase the filling speed. Generally, the second insulating layer 16 is made of the same material as the first insulating layer 15, and is formed by a high density plasma chemical vapor deposition process, and the deposition rate is mainly adjusted by adjusting parameters such as reaction temperature, gas flow rate, and the like.
However, the film growth rate is different at each position due to the difference of the arrival angles of the bottom, the side wall and the top of the trench, and the arrival angles at each position are shown in fig. 5. The larger the angle of arrival, the faster the film growth rate, and conversely the slower the film growth rate, so that when filling a trench with a high aspect ratio, an overhang may be generated at the corner of the trench due to the fast film growth rate at the corner. With the increase of the depth-to-width ratio of the trench, it is very easy to form a void in the trench due to the overhang seal, thereby adversely affecting the electrical performance of the semiconductor device.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which is used for improving the defect of a cavity in a groove and improving the electrical property of the semiconductor device.
In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of:
providing a substrate, and forming a groove in the substrate;
forming a first insulating layer by adopting a first high-density plasma chemical vapor deposition process, wherein the first insulating layer covers the side wall and the bottom of the groove;
etching to remove part of the thickness of the first insulating layer;
sequentially repeating the deposition step of the first insulating layer and the etching step of the first insulating layer until the first insulating layer is filled in the groove; and the number of the first and second groups,
and forming a second insulating layer by adopting a second high-density plasma chemical vapor deposition process, wherein the second insulating layer covers the first insulating layer.
Optionally, the reaction gas of the first high-density plasma chemical vapor deposition process includes: oxygen, silane, and hydrogen.
Optionally, the material of the first insulating layer includes silicon oxide, and the material of the second insulating layer includes silicon oxide.
Optionally, the method for removing a part of the thickness of the first insulating layer by etching includes: and introducing nitrogen trifluoride into the reaction chamber, and under the action of the radio frequency generator, ionizing fluorine ions by the nitrogen trifluoride, wherein the fluorine ions react with the silicon oxide to remove part of the thickness of the first insulating layer.
Optionally, before forming the trench, the method further includes: sequentially forming a first liner layer and a hard mask layer on the substrate; the trench extends through the hard mask layer and the first liner layer into the substrate.
Optionally, after forming the second insulating layer, the method further includes:
planarizing the second insulating layer and the first insulating layer until the hard mask layer is exposed;
and removing the hard mask layer.
Optionally, after forming the trench and before forming the first insulating layer, the method further includes: forming a second liner layer covering the side wall and the bottom of the groove; the first insulating layer covers the second pad layer.
Optionally, the first liner layer is made of silicon oxide, the second liner layer is made of silicon oxide, and the hard mask layer is made of silicon nitride.
Optionally, the reaction gas of the second high-density plasma chemical vapor deposition process is the same as the reaction gas of the first high-density plasma chemical vapor deposition process, and a flow rate of the reaction gas of the second high-density plasma chemical vapor deposition process is greater than a flow rate of the reaction gas of the first high-density plasma chemical vapor deposition process.
Optionally, the depositing step of the first insulating layer and the etching step of the first insulating layer are repeated once.
In summary, the manufacturing method of a semiconductor device provided by the present invention includes providing a substrate, forming a trench in the substrate, forming a first insulating layer by a first high density plasma chemical vapor deposition process, wherein the first insulating layer covers a sidewall and a bottom of the trench, etching to remove a portion of the thickness of the first insulating layer, sequentially repeating the deposition step of the first insulating layer and the etching step of the first insulating layer until the trench is filled with the first insulating layer, and forming a second insulating layer by a second high density plasma chemical vapor deposition process, wherein the second insulating layer covers the first insulating layer. According to the invention, after a part of first insulating layer is formed, the first insulating layer with a part of thickness is etched and removed to remove the overhang formed at the corner of the groove, and then the deposition step of the first insulating layer and the etching step of the first insulating layer are sequentially repeated until the groove 130 is filled with the first insulating layer, so that the excessive overhang can be prevented to avoid sealing the groove, and thus, a cavity is prevented from being formed in the groove, and the electrical property of the semiconductor device is improved.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention.
Fig. 1-4 illustrate a method for forming a shallow trench isolation structure according to the prior art.
Fig. 5 is a schematic view of the angle of arrival at each location of the trench.
Fig. 6 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the invention.
Fig. 7-11 are schematic structural diagrams illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the invention.
In fig. 1 to 4:
10-a substrate; 11-a first cushion layer; 12-a hard mask layer; 13-a trench; 14-a second cushion layer; 15-a first insulating layer; 16-second insulating layer.
In fig. 7 to 11:
100-a substrate; 110-a first liner layer; 120-hard mask layer; 130-a trench; 140-a second liner layer; 150-a first insulating layer; 160-second insulating layer.
Detailed Description
When the first insulating layer is formed in the trench, since the growth rate of the first insulating layer at the corner is faster than that of the sidewall and the bottom, an overhang of the first insulating layer is generated at the corner of the trench, that is, the thickness of the first insulating layer generated at the corner is greater than that of the first insulating layer at the rest positions. The increasing amount of overhang tends to seal the trench and create voids within the trench.
The inventor finds that after a part of first insulating layer is formed in the groove, the first insulating layer with a part of thickness is removed by back etching, a part of overhang of the first insulating layer can be removed, then the first insulating layer is deposited and etched, and the steps of depositing and etching are repeated continuously, so that the phenomenon that the overhang at the corner of the groove is too much can be prevented, the groove is sealed, and a cavity is prevented from being formed in the groove.
Through further research, the inventors provide a method for manufacturing a semiconductor device, comprising: providing a substrate, and forming a groove in the substrate; forming a first insulating layer by adopting a first high-density plasma chemical vapor deposition process, wherein the first insulating layer covers the side wall and the bottom of the groove; etching to remove part of the thickness of the first insulating layer; sequentially repeating the deposition step of the first insulating layer and the etching step of the first insulating layer until the first insulating layer is filled in the groove; and forming a second insulating layer by adopting a second high-density plasma chemical vapor deposition process, wherein the second insulating layer covers the first insulating layer.
According to the invention, after a part of first insulating layer is formed, the first insulating layer with a part of thickness is etched and removed to remove the overhang formed at the corner of the groove, and then the deposition step of the first insulating layer and the etching step of the first insulating layer are sequentially repeated until the groove is filled with the first insulating layer, so that excessive overhang can be prevented to avoid sealing the groove, and thus, a cavity is prevented from being formed in the groove, and the electrical property of the semiconductor device is improved.
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, features defined as "first," "second," and "third" may explicitly or implicitly include one or at least two of the features unless the content clearly dictates otherwise.
Fig. 6 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the invention.
As shown in fig. 6, the method for manufacturing the semiconductor device includes the following steps:
s1: providing a substrate, and forming a groove in the substrate;
s2: forming a first insulating layer by adopting a first high-density plasma chemical vapor deposition process, wherein the first insulating layer covers the side wall and the bottom of the groove;
s3: etching to remove part of the thickness of the first insulating layer;
s4: sequentially repeating the deposition step of the first insulating layer and the etching step of the first insulating layer until the first insulating layer is filled in the groove;
s5: and forming a second insulating layer by adopting a second high-density plasma chemical vapor deposition process, wherein the second insulating layer covers the first insulating layer.
Fig. 7 to fig. 11 are schematic structural diagrams of steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 6 and fig. 7 to fig. 11.
In step S1, referring to fig. 7, a substrate 100 is provided, and a trench 130 is formed in the substrate 100.
The material of the substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC), or Silicon On Insulator (SOI), Germanium On Insulator (GOI); or may be other materials such as group III-V compounds such as gallium arsenide. In the present embodiment, the material of the substrate 100 is preferably single crystal silicon (Si). Components may also be formed within the substrate 100, such as: PMOS transistors, NMOS transistors, resistors, capacitors, inductors, etc.
In this embodiment, first, a first liner layer 110 and a hard mask layer 120 may be sequentially formed on the substrate 100. For example, a first liner layer 110 may be formed on the substrate 100 by a high temperature oxidation method, and then a hard mask layer 120 may be formed on the first liner layer 110 by a chemical vapor deposition method. The first liner layer 110 is made of, but not limited to, silicon oxide, and the hard mask layer 120 is made of, but not limited to, silicon nitride. The hard mask layer 120 functions to protect the underlying first liner layer 110 and the substrate 100 from the etching gas during subsequent etching to form a trench.
Next, the hard mask layer 120, the first liner layer 110, and the substrate 100 are etched to form a trench 130. For example, a photoresist layer (not shown) may be formed on the hard mask layer 120 through a spin coating process, the photoresist layer is exposed and developed to form a patterned photoresist layer, then the hard mask layer 120, the first liner layer 110 and a portion of the substrate 100 are sequentially etched using the patterned photoresist layer as a mask to form a trench 130, and the trench 130 penetrates through the hard mask layer 120 and the first liner layer 110 and extends into the substrate 100. The patterned photoresist layer may then optionally be removed using an oxygen ion ashing or the like process.
Next, in the present embodiment, referring to fig. 8, a second liner layer 140 may be further formed, where the second liner layer 140 covers the sidewalls and the bottom of the trench 130. The second liner layer 140 may also cover the upper surface of the hard mask layer 120. The second liner layer 140 is used to avoid the problems of poor adhesion between the first insulating layer and the substrate 100 exposed by the sidewall of the trench 130, easy occurrence of voids, and large stress due to mismatch between the first insulating layer and the substrate material of the sidewall of the trench 130 when the first insulating layer is directly formed in the trench 130, and can repair the damage to the substrate of the sidewall of the trench 130 during the etching process to form the trench 130. The second liner layer 140 may be formed by a thermal oxidation method, such as dry oxygen oxidation, moisture oxidation, wet oxygen oxidation, or the like, or other suitable methods. The material of the second liner layer 140 includes, but is not limited to, silicon oxide.
Please refer to fig. 9 for steps S2 and S3. Specifically, in step S2, a first high density plasma chemical vapor deposition process is used to form a first insulating layer 150, and the first insulating layer 150 covers the sidewalls and the bottom of the trench 130.
The first insulating layer 150 is formed by using a high density plasma chemical vapor deposition method, and the material of the first insulating layer 150 includes, but is not limited to, silicon oxide.
The first high density plasma chemical vapor deposition process is carried out simultaneously with the deposition of the thin film and the sputtering of the plasma. And introducing reaction gases into the reaction chamber, wherein the reaction gases comprise oxygen (O2), silicon methane (SiH 4) and hydrogen. Oxygen and silane are used as raw material gases to react to generate silicon oxide. The hydrogen gas is used as etching gas, and is dissociated into hydrogen ions under the action of the radio frequency generator, and the hydrogen ions vertically bombard the surface of the substrate 100 under the action of the bias voltage.
In this embodiment, only a portion of the thickness of the first insulating layer 150 is deposited, and the first insulating layer 150 covers the sidewalls and the bottom of the trench 130, but does not need to fill the trench 130. Due to the relatively fast deposition rate at the corners of the trench 130, an overhang of the first insulating layer 150 may be formed at the corners, but since only a partial thickness of the first insulating layer 150 is formed, the overhang may not yet close the trench 130.
In step S3, the first insulating layer 150 is etched to remove a portion of the thickness.
Specifically, nitrogen trifluoride (NF) is introduced into the reaction chamber3) Under the action of the rf generator, nitrogen trifluoride ionizes to form fluorine ions, which react with silicon oxide to remove a portion of the thickness of the first insulating layer 150. The overhang formed in the previous step is removed in this step, or partially removed.
Step S3 may be performed in the same reaction chamber as step S2 or in a different reaction chamber.
In step S4, referring to fig. 10, the deposition step of the first insulating layer 150 and the etching step of the first insulating layer 150 are sequentially repeated until the first insulating layer 150 fills the trench.
Specifically, the steps S2 and S3 are sequentially repeated, that is, after the step S3 is performed, the steps S2 and S3 are performed, and the steps may be repeated several times until the first insulating layer 150 fills the trench. The number of repetitions may be determined according to the aspect ratio of the trench 130, for example, the deposition step of the first insulating layer 150 and the etching step of the first insulating layer 150 may be repeated once, that is, after step S1 is executed, step S2 and step S3 are executed, and then step S2 and step S3 are executed, at this time, the trench 130 is filled with the first insulating layer 150. Since the deposition of the first insulating layer 150 is completed in steps, after a portion of the first insulating layer 150 is deposited, the first insulating layer 150 with a portion of the thickness is removed by etching, which can prevent excessive overhang from sealing the trench 130, thereby preventing a void from being formed in the trench 130, and thus improving the electrical performance of the semiconductor device.
In this embodiment, the deposition step of the first insulating layer 150 and the etching step of the first insulating layer 150 are repeated once. For example, the depth of the trench 130 is 8000 a, the deposition of the first insulating layer 150 can be completed in two times, first, the first deposition of the first insulating layer 150 is performed, the deposition thickness of the first insulating layer 150 is 5000 a, and at this time, due to the faster deposition rate, the corner of the trench 130 is already formed with the overhang of the first insulating layer 150; a first etch of the first insulating layer 150 is then performed to remove the first insulating layer to a thickness of 1000 angstroms, during which the overhangs formed at the corners of the trenches 130 are also largely removed. Then, a second deposition of the first insulating layer 150 is performed, and the first insulating layer 150 with a thickness of 5000 angstroms is deposited again, in the process, the overhang at the corner of the trench 130 is formed again, but the overhang is already greatly reduced by etching compared with the process of depositing the first insulating layer to fill up the trench 130 at one time; and then, etching the first insulating layer 150 for the second time, and etching and removing the first insulating layer 150 with the thickness of 1000 angstroms again, wherein most of the overhang formed at the corner of the trench 130 is also removed, and at this time, the first insulating layer 150 is already filled in the trench 130.
The filling of the trench 130 with the first insulating layer 150 means that the upper surface of the first insulating layer 150 is flush with the upper surface of the hard mask layer 120, or the upper surface of the first insulating layer 150 is close to the upper surface of the hard mask layer 120 and slightly higher or lower than the upper surface of the hard mask layer 120. In the case that the hard mask layer 120 and the first liner layer 110 do not need to be formed, the step of filling the trench 130 with the first insulating layer 150 means that the upper surface of the first insulating layer 150 is flush with the upper surface of the substrate 100, or the upper surface of the first insulating layer 150 is close to the upper surface of the substrate 100 and slightly higher or lower than the upper surface of the substrate 100.
In step S5, please refer to fig. 11, a second high density plasma cvd process is used to form a second insulating layer 160, and the second insulating layer 160 covers the first insulating layer 150.
The second insulating layer 160 is formed using a high density plasma chemical vapor deposition process. The material of the second insulating layer 160 is the same as that of the first insulating layer 150. In this embodiment, the material of the second insulating layer 160 includes, but is not limited to, silicon oxide.
The reaction gas of the second high-density plasma chemical vapor deposition process is the same as the reaction gas of the first high-density plasma chemical vapor deposition process, and the flow rate of the reaction gas of the second high-density plasma chemical vapor deposition process is greater than that of the reaction gas of the first high-density plasma chemical vapor deposition process. And adjusting the deposition rate by adjusting parameters such as reaction temperature, so that the deposition rate of the second high-density plasma chemical vapor deposition process is greater than that of the first high-density plasma chemical vapor deposition process, thereby completing the deposition of the second insulating layer 160.
Then, the second insulating layer 160 and the first insulating layer 150 may be planarized until the hard mask layer 120 is exposed, and then the hard mask layer 120 may be removed to form a shallow trench isolation structure.
After forming a part of the first insulating layer 150, the invention performs etching to remove a part of the thickness of the first insulating layer 150 to remove the overhang formed at the corner of the trench 130, and then repeats the deposition step of the first insulating layer 150 and the etching step of the first insulating layer 150 in sequence until the trench 130 is filled with the first insulating layer 150, thereby preventing the overhang from being too much to avoid sealing the trench 130, and avoiding forming a cavity in the trench 130, thereby improving the electrical performance of the semiconductor device.
In summary, the manufacturing method of a semiconductor device provided by the present invention includes providing a substrate, forming a trench in the substrate, forming a first insulating layer by a first high density plasma chemical vapor deposition process, wherein the first insulating layer covers a sidewall and a bottom of the trench, etching to remove a portion of the thickness of the first insulating layer, sequentially repeating the deposition step of the first insulating layer and the etching step of the first insulating layer until the trench is filled with the first insulating layer, and forming a second insulating layer by a second high density plasma chemical vapor deposition process, wherein the second insulating layer covers the first insulating layer. According to the invention, after a part of first insulating layer is formed, the first insulating layer with a part of thickness is etched and removed to remove the overhang formed at the corner of the groove, and then the deposition step of the first insulating layer and the etching step of the first insulating layer are sequentially repeated until the groove 130 is filled with the first insulating layer, so that the excessive overhang can be prevented to avoid sealing the groove, and thus, a cavity is prevented from being formed in the groove, and the electrical property of the semiconductor device is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method for manufacturing a semiconductor device is characterized by comprising the following steps:
providing a substrate, and forming a groove in the substrate;
forming a first insulating layer by adopting a first high-density plasma chemical vapor deposition process, wherein the first insulating layer covers the side wall and the bottom of the groove;
etching to remove part of the thickness of the first insulating layer;
sequentially repeating the deposition step of the first insulating layer and the etching step of the first insulating layer until the first insulating layer is filled in the groove; and the number of the first and second groups,
and forming a second insulating layer by adopting a second high-density plasma chemical vapor deposition process, wherein the second insulating layer covers the first insulating layer.
2. The method of claim 1, wherein the reaction gas of the first HDP-CVD process comprises: oxygen, silane, and hydrogen.
3. The method according to claim 2, wherein the first insulating layer comprises silicon oxide, and the second insulating layer comprises silicon oxide.
4. The method of claim 3, wherein the step of etching away a portion of the thickness of the first insulating layer comprises: and introducing nitrogen trifluoride into the reaction chamber, and under the action of the radio frequency generator, ionizing fluorine ions by the nitrogen trifluoride, wherein the fluorine ions react with the silicon oxide to remove part of the thickness of the first insulating layer.
5. The method of claim 1, further comprising, prior to forming the trench: sequentially forming a first liner layer and a hard mask layer on the substrate; the trench extends through the hard mask layer and the first liner layer into the substrate.
6. The method of claim 5, further comprising, after forming the second insulating layer:
planarizing the second insulating layer and the first insulating layer until the hard mask layer is exposed;
and removing the hard mask layer.
7. The method of claim 6, wherein after forming the trench and before forming the first insulating layer, further comprising: forming a second liner layer covering the side wall and the bottom of the groove; the first insulating layer covers the second pad layer.
8. The method of claim 7, wherein the first liner layer comprises silicon oxide, the second liner layer comprises silicon oxide, and the hard mask layer comprises silicon nitride.
9. The method according to claim 2, wherein the reaction gas of the second HDP-CVD process is the same as the reaction gas of the first HDP-CVD process, and a flow rate of the reaction gas of the second HDP-CVD process is greater than a flow rate of the reaction gas of the first HDP-CVD process.
10. The method according to claim 1, wherein the step of depositing the first insulating layer and the step of etching the first insulating layer are repeated once.
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Cited By (1)
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