CN108630526A - A method of improving interlayer dielectric layer cavity - Google Patents
A method of improving interlayer dielectric layer cavity Download PDFInfo
- Publication number
- CN108630526A CN108630526A CN201810416000.8A CN201810416000A CN108630526A CN 108630526 A CN108630526 A CN 108630526A CN 201810416000 A CN201810416000 A CN 201810416000A CN 108630526 A CN108630526 A CN 108630526A
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- China
- Prior art keywords
- dielectric layer
- coating
- interlayer dielectric
- oxide skin
- oxide
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- 239000010410 layer Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000011229 interlayer Substances 0.000 title claims abstract description 27
- 239000011248 coating agent Substances 0.000 claims abstract description 36
- 238000000576 coating method Methods 0.000 claims abstract description 36
- 239000001301 oxygen Substances 0.000 claims abstract description 16
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 16
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 238000002360 preparation method Methods 0.000 claims abstract description 6
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000009751 slip forming Methods 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 239000007789 gas Substances 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000012535 impurity Substances 0.000 abstract description 14
- 230000000694 effects Effects 0.000 abstract description 5
- 238000011282 treatment Methods 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000001556 precipitation Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- -1 oxygen Nitride Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001376 precipitating effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02334—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment in-situ cleaning after layer formation, e.g. removing process residues
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of methods in solution interlayer dielectric layer cavity, applied in semiconductor fabrication process, it is used on the outside of gate structure and forms side wall and silicide interlayer dielectric layer laminated film, the first oxide skin(coating) of one first predetermined thickness is formed in laminated film outer surface, it returns and carves the first oxide skin(coating), it is passed through oxygen in the first oxide layer surface and continues a predetermined time for being not less than 15 seconds, oxide skin(coating) is continuously formed in the first oxide layer surface, to complete the preparation process of interlevel oxide dielectric layer.Technical scheme of the present invention will pass through oxygen treatments applied technique, impurity in control gate gap is taken away by oxygen flow to achieve the effect that between clean control gate gap, the cavity that interlayer dielectric layer is avoided in removal impurity generates, and reduces product defects, improves product yield.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of methods improving interlayer dielectric layer cavity.
Background technology
Include inter-level dielectric in the technique for preparing control gate in existing nonvolatile semiconductor memory manufacturing process
Depositing operation, for precipitating inter-level dielectric in the interval region of control gate and top.In existing inter-level dielectric depositing operation,
Residual impurity is very easy between control gate, the impurity that prior art can not completely in clean groove, impurity can be follow-up
Cavity is formed in technique, leads to occur defect in interlayer medium film.Remaining impurity, which may result in, between control gate connects
Being connected between contact hole, the short circuit of circuit is formed, the reduction of yield is caused.
Meanwhile successively decreasing with device size, control gate gap are also gradually reduced, and the depth-to-width ratio in the gap is caused to become more
Greatly, further such that the impurity in control gate gap is more difficult to remove.Therefore, in the memory manufacturing process being constantly progressive,
Strong influence is produced to product yield.
Invention content
For the above-mentioned problems in the prior art, a kind of method for being intended to improve interlayer dielectric layer cavity is now provided.
Specific technical solution is as follows：
A method of improving interlayer dielectric layer cavity, is applied in semiconductor fabrication process, includes the following steps：
Step S1：One semiconductor structure for completing the gate structure preparation process with control gate is provided；
Step S2：Side wall and silicide interlayer dielectric layer laminated film are formed on the outside of the gate structure；
Step S3：The first oxide skin(coating) of one first predetermined thickness is formed in the laminated film outer surface；
Step S4：It returns and carves first oxide skin(coating), to remove first oxide skin(coating) of one second predetermined thickness；
Step S5：It is passed through oxygen in first oxide layer surface and continues a predetermined time for being not less than 15 seconds, with
Remain on the residue between the gate structure when removing back quarter first oxide skin(coating)；
Step S6：Oxide skin(coating) is continuously formed in first oxide layer surface, to complete interlevel oxide dielectric layer
Preparation process.
Preferably, in the step S5, the predetermined time is 15-30 seconds.
Preferably, in the step S5, the predetermined time is 20 seconds.
Preferably, in the step S3, first predetermined thickness is 1200A.
Preferably, in the step S4, second predetermined thickness is 130A.
Preferably, in the step S3, the first oxide skin(coating) material is silica.
Preferably, it in the step S4, is returned using gas of nitrogen trifluoride and carves first oxide skin(coating).
Preferably, in the step S3, first oxide skin(coating) is formed using chemical vapor deposition method.
Preferably, the chemical vapor deposition method deposits first oxidation by the mixed gas of monosilane and oxygen
Nitride layer.
Preferably, in the step S6, the oxide skin(coating) for continuing deposition is silica；And/or in the step S6, continue
The thickness of the oxide skin(coating) of deposition is 800A.
Above-mentioned technical proposal has the following advantages that or advantageous effect：
Using in interlayer dielectric layer precipitation process, silicon oxide precipitation process is divided into two parts and is carried out, in pilot process
Oxygen is passed through using semicon-ductor structure surface so that the impurity in control gate gap can be taken away by oxygen flow to reach cleaning
Effect between clean control gate gap, the cavity that interlayer dielectric layer is avoided in removal impurity generate, reduce product defects, carry
High product yield.
Description of the drawings
With reference to appended attached drawing, more fully to describe the embodiment of the present invention.However, appended attached drawing be merely to illustrate and
It illustrates, and is not meant to limit the scope of the invention.
Fig. 1 is a kind of flow chart for the embodiment of the method improving interlayer dielectric layer cavity of the present invention.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art obtained under the premise of not making creative work it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The invention will be further described in the following with reference to the drawings and specific embodiments, but not as limiting to the invention.
In a kind of preferred embodiment of the present invention, according to Fig. 1, a method of improving interlayer dielectric layer cavity, answers
For in semiconductor fabrication process, including the following steps：
Step S1：One semiconductor structure for completing the gate structure preparation process with control gate is provided；
Step S2：Side wall and silicide interlayer dielectric layer laminated film are formed on the outside of gate structure；
Step S3：The first oxide skin(coating) of one first predetermined thickness is formed in laminated film outer surface；
Step S4：It returns and carves the first oxide skin(coating), to remove the first oxide skin(coating) of one second predetermined thickness；
Step S5：It is passed through oxygen in the first oxide layer surface and continues a predetermined time for being not less than 15 seconds, with removal
Remain on the residue between gate structure when returning the first oxide skin(coating) of quarter；
Step S6：Oxide skin(coating) is continuously formed in the first oxide layer surface, to complete the system of interlevel oxide dielectric layer
Standby technique.
Specifically, in the present embodiment, carried out using silicon oxide precipitation process is divided into two parts, in pilot process using to
First oxide layer surface is passed through oxygen so that the impurity in control gate gap can be taken away dry to reach cleaning by oxygen flow
Effect between net control gate gap.
Quarter processing is carried out back using to the first oxide skin(coating), the impurity of the first oxide layer surface can be removed, and will
Already present hole is opened in first oxide skin(coating) so that oxygen treatments applied technique thereafter can will be in hole and the first oxide
The impurity of layer surface cleans up.
On the outside of control gate by chemical vapour deposition technique be sequentially depositing silica, silicon nitride, silica, silicon oxynitride,
Silicon nitride is to form side wall and silicide interlayer dielectric layer laminated film, the i.e. laminated film of SPACER+ILD SIN.
In a kind of preferred embodiment of the present invention, in step S5, the predetermined time is 15-30 seconds.
It specifically,, can be effectively by semiconductor structure using the oxygen treatment processes of above-mentioned duration in the present embodiment
Impurity in groove and gap blows off, and achievees the effect that avoid impurity.
In a kind of preferred embodiment of the present invention, in step S5, the predetermined time is 20 seconds.
In a kind of preferred embodiment of the present invention, in step S3, the first predetermined thickness is 1200A.
In a kind of preferred embodiment of the present invention, in step S4, the second predetermined thickness is 130A.
In a kind of preferred embodiment of the present invention, in step S3, the first oxide skin(coating) material is silica.
In a kind of preferred embodiment of the present invention, in step S4, is returned using gas of nitrogen trifluoride and carve the first oxide skin(coating).
Specifically, in the present embodiment, after gas of nitrogen trifluoride returns quarter processing so that residual in the groove of semiconductor structure
Fluorine gas (F2) gas, it is removed using subsequent oxygen treatments applied.
In a kind of preferred embodiment of the present invention, in step S3, the first oxide is formed using chemical vapor deposition method
Layer.
In a kind of preferred embodiment of the present invention, chemical vapor deposition method is heavy by the mixed gas of monosilane and oxygen
The first oxide skin(coating) of product.
In a kind of preferred embodiment of the present invention, in step S6, the oxide skin(coating) for continuing deposition is silica；And/or step
In rapid S6, the thickness for continuing the oxide skin(coating) of deposition is 800A.
In a kind of preferred embodiment of the present invention, semiconductor structure is made using following processing step：One is provided to have been formed
The silicon chip of FGS floating gate structure, and silica, silicon nitride, silica are sequentially depositing to form ONO films in silicon chip surface；To silicon chip table
Face deposit polycrystalline silicon, and photoetching and chemical etching are carried out to form control gate to polysilicon.
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.
Claims (10)
1. a kind of method improving interlayer dielectric layer cavity, is applied in semiconductor fabrication process, which is characterized in that including following
Step：
Step S1：One semiconductor structure for completing the gate structure preparation process with control gate is provided；
Step S2：Side wall and silicide interlayer dielectric layer laminated film are formed on the outside of the gate structure；
Step S3：The first oxide skin(coating) of one first predetermined thickness is formed in the laminated film outer surface；
Step S4：It returns and carves first oxide skin(coating), to remove first oxide skin(coating) of one second predetermined thickness；
Step S5：It is passed through oxygen in first oxide layer surface and continues a predetermined time for being not less than 15 seconds, with removal
Remain on the residue between the gate structure when returning quarter first oxide skin(coating)；
Step S6：Oxide skin(coating) is continuously formed in first oxide layer surface, to complete the system of interlevel oxide dielectric layer
Standby technique.
2. the method according to claim 1 for improving interlayer dielectric layer cavity, which is characterized in that in the step S5, institute
It is 15-30 seconds to state the predetermined time.
3. the method according to claim 1 for improving interlayer dielectric layer cavity, which is characterized in that in the step S5, institute
It is 20 seconds to state the predetermined time.
4. the method according to claim 1 for improving interlayer dielectric layer cavity, which is characterized in that in the step S3, institute
It is 1200A to state the first predetermined thickness.
5. the method according to claim 1 for improving interlayer dielectric layer cavity, which is characterized in that in the step S4, institute
It is 130A to state the second predetermined thickness.
6. the method according to claim 1 for improving interlayer dielectric layer cavity, which is characterized in that in the step S3, institute
It is silica to state the first oxide skin(coating) material.
7. the method according to claim 6 for improving interlayer dielectric layer cavity, which is characterized in that in the step S4, adopt
It is returned with gas of nitrogen trifluoride and carves first oxide skin(coating).
8. the method according to claim 6 for improving interlayer dielectric layer cavity, which is characterized in that in the step S3, adopt
First oxide skin(coating) is formed with chemical vapor deposition method.
9. the method according to claim 6 for improving interlayer dielectric layer cavity, which is characterized in that the chemical vapor deposition
Technique deposits first oxide skin(coating) by the mixed gas of monosilane and oxygen.
10. the method according to claim 1 for improving interlayer dielectric layer cavity, which is characterized in that in the step S6, after
The oxide skin(coating) of continuous deposition is silica；And/or in the step S6, the thickness for continuing the oxide skin(coating) of deposition is 800A.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810416000.8A CN108630526B (en) | 2018-05-03 | 2018-05-03 | Method for improving cavity of interlayer dielectric layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810416000.8A CN108630526B (en) | 2018-05-03 | 2018-05-03 | Method for improving cavity of interlayer dielectric layer |
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| CN108630526A true CN108630526A (en) | 2018-10-09 |
| CN108630526B CN108630526B (en) | 2020-11-06 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20050112869A1 (en) * | 2003-11-21 | 2005-05-26 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device |
| CN1779903A (en) * | 2004-10-20 | 2006-05-31 | 国际商业机器公司 | Oxidation sidewall image transfer patterning method |
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| CN103928326A (en) * | 2013-01-10 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | Method of forming transistor |
| CN105448647A (en) * | 2014-07-29 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method for reducing Bump defect in hydrogenated amorphous carbon film layer |
| CN106298490A (en) * | 2016-10-20 | 2017-01-04 | 武汉华星光电技术有限公司 | A kind of method solving dry etching processing procedure gate layer residual and dry etching manufacturing method thereof |
-
2018
- 2018-05-03 CN CN201810416000.8A patent/CN108630526B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1271179A (en) * | 1999-04-16 | 2000-10-25 | 国际商业机器公司 | Process for oxide corroding of high selective neck ring |
| US20020064936A1 (en) * | 2000-11-27 | 2002-05-30 | Park Wan-Jae | Method of forming interlevel dielectric layer of semiconductor device |
| CN1577751A (en) * | 2003-07-10 | 2005-02-09 | 应用材料有限公司 | Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode |
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| US20050112869A1 (en) * | 2003-11-21 | 2005-05-26 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device |
| CN1779903A (en) * | 2004-10-20 | 2006-05-31 | 国际商业机器公司 | Oxidation sidewall image transfer patterning method |
| CN1941297A (en) * | 2005-09-28 | 2007-04-04 | 联华电子股份有限公司 | Production of strain silicon transistor |
| CN101840882A (en) * | 2009-03-20 | 2010-09-22 | 中芯国际集成电路制造(上海)有限公司 | Shallow slot isolation method |
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| CN108630526B (en) | 2020-11-06 |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |