CN110690112A - Forming surface planarization structure and method using reverse pitch doubling process - Google Patents
Forming surface planarization structure and method using reverse pitch doubling process Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
Abstract
The invention provides a surface planarization structure formed by a reverse pitch doubling process and a method, wherein the method comprises the following steps: forming a reverse interval mask layer, a first mask layer, a lateral etching interval sacrificial layer and a first etching pattern on a semiconductor substrate; etching the side etching interval sacrificial layer and the first mask layer through the first etching pattern to form a second etching pattern; forming a spacing layer and a second mask layer on the surface of the second etching graph; removing the part of the second mask layer higher than the spacing layer; etching the spacing layer and the side etching spacing sacrificial layer on the first mask layer to expose the inner side surface of the spacing layer on the first mask layer; etching the spacing layer on the side of the first mask layer through the inner side surface to form a first groove; and etching the reverse interval mask layer through the first groove to form a second groove, wherein two sides of the second groove are provided with first protruding structures with flat surfaces. The invention solves the problem that the effective area of the traditional active area is reduced because the top of the active area is uneven.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and more particularly, to a method and structure for forming a surface planarization using a reverse pitch doubling process.
Background
In the field of semiconductor integrated circuits, the fabrication of an active region is an essential step in the fabrication of a semiconductor device, and the fabrication method of a conventional active region is generally shown in fig. 1 to 6:
as shown in fig. 1, an insulating layer 102, an etching stop layer 103 and an etching pattern 104 are sequentially formed on a semiconductor substrate 101 from bottom to top; then, as shown in fig. 2, a spacer material layer 105 is formed on the surface of the etching stop layer 103 and the surface of the etching pattern 104; then, as shown in fig. 3, the spacer material layer 105 in the horizontal direction is removed by an anisotropic etching process; then, as shown in fig. 4, the etching pattern 104 is removed; finally, as shown in fig. 5 and 6, the etching stop layer 103, the insulating layer 102 and the semiconductor substrate 101 are sequentially etched by using the spacer material layer 105 in the vertical direction as a mask pattern, so as to form an active region 106 in the semiconductor substrate 101.
As shown in fig. 5 and 6, when the active region 106 is formed on the semiconductor substrate 101 by the conventional method, the top of the spacer material layer 105 (the spacer material layer in the vertical direction) on both sides of the etching pattern 104 is in an arc shape, that is, the top of the spacer material layer 105 on both sides of the etching pattern 104 is not flat, so that the top of the active region 106 formed by using the etching pattern as a mask pattern is not flat, thereby reducing the effective area of the active region 106.
Therefore, a new method and structure for surface planarization using reverse pitch doubling process is needed to solve the above-mentioned problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a surface planarization structure and method using reverse pitch doubling process, which is used to solve the problem of the conventional method for fabricating active areas that the top of the active area is not flat, and thus the effective area of the active area is reduced.
To achieve the above and other related objects, the present invention provides a method for forming a surface planarization structure using a reverse pitch doubling process, the method comprising:
s1: providing a semiconductor substrate, sequentially forming a reverse interval mask layer, a first mask layer and a lateral etching interval sacrificial layer from bottom to top on the semiconductor substrate, and forming a first etching pattern on the lateral etching interval sacrificial layer;
s2: carrying out pattern etching on the side etching interval sacrificial layer and the first mask layer by taking the first etching pattern as a mask pattern until the reverse interval mask layer is exposed, so as to form a second etching pattern on the reverse interval mask layer; forming a spacing layer and a second mask layer from inside to outside in sequence at least on the top surface and the side surface of the second etching pattern;
s3: removing the part of the second mask layer higher than the spacing layer until the spacing layer is exposed on the top surface of the second etching pattern;
s4: etching the spacing layer and the side etching spacing sacrificial layer on the first mask layer until the inner side face of the spacing layer on the first mask layer is exposed;
s5: etching the spacing layer positioned on the side edge of the first mask layer through the inner side surface of the spacing layer on the first mask layer until the reverse spacing mask layer is exposed, so as to form a first groove between the first mask layer and the second mask layer; and
s6: etching the reverse interval mask layer through the first groove to form a second groove and first protruding structures located on two sides of the second groove in the reverse interval mask layer; wherein the first protrusion structure has a flat surface.
Optionally, the forming method further includes S7: and at least removing the first mask layer and the second mask layer on the upper surface of the reverse interval mask layer.
Optionally, the forming method further includes S8: and etching the semiconductor substrate through the second groove to form a third groove and second protruding structures positioned on two sides of the third groove in the semiconductor substrate, wherein the second protruding structures are provided with flat surfaces.
Optionally, the S1 further includes: forming a third mask layer between the semiconductor substrate and the reverse interval mask layer; the S8 further includes: etching the third mask layer through the second groove until the semiconductor substrate is exposed, so as to form a final groove on the semiconductor substrate; and etching the semiconductor substrate through the final groove to form a third groove in the semiconductor substrate.
Optionally, when the second bump structure includes an active region, the forming method further includes S9: and filling an insulating material in the third groove to form a shallow trench isolation structure.
Optionally, the S1 further includes: sequentially forming an insulating layer and an etching stop layer from bottom to top between the semiconductor substrate and the reverse spacer mask layer, wherein S8 further includes: and etching and removing the insulating layer and the etching stop layer.
Optionally, the thickness of the undercut spacing sacrificial layer is not greater than 50% of the thickness of the first mask layer, so that the aspect ratio of the second etched pattern is greater than or equal to 3.
Optionally, the aspect ratio of the second etching pattern is greater than or equal to 5.
Optionally, in S2, the second etching pattern is formed by a single dry etching process.
Optionally, the etching gas of the dry etching process comprises carbon tetrafluoride and oxygen, wherein the gas flow rate of the carbon tetrafluoride is between 100sccm and 200sccm, and the gas flow rate of the oxygen is between 5sccm and 15 sccm; the pressure of the reaction chamber of the dry etching process is between 30mT and 50mT, the source power is between 200W and 300W, and the bias voltage is between 100V and 200V.
Optionally, a material of the first mask layer is selected from one of a group consisting of a photoresist, an organic anti-reflection layer material, an inorganic anti-reflection layer material and amorphous carbon, and a material of the undercut spacer sacrificial layer is selected from one of a group consisting of an organic anti-reflection layer material, an inorganic anti-reflection layer material and amorphous carbon.
Optionally, the material of the first mask layer includes a photoresist, and the material of the undercut interval sacrificial layer includes an organic anti-reflection layer material.
Optionally, in S3, a dry etching process is used to remove a portion of the second mask layer higher than the spacer layer, where an etching gas of the dry etching process includes carbon tetrafluoride and oxygen, a gas flow rate of the carbon tetrafluoride is between 100 seem and 200 seem, a gas flow rate of the oxygen is between 5 seem and 15 seem, a pressure of a reaction chamber of the dry etching process is between 30mT and 50mT, a source power is between 200W and 300W, and a bias voltage is between 100V and 200V.
Optionally, in S3, a chemical mechanical polishing process is used to remove a portion of the second mask layer higher than the spacer layer.
Optionally, in S4, a dry etching process is used to remove the spacer layer and the undercut spacer sacrificial layer on the first mask layer, and an etching gas of the dry etching process includes carbon tetrafluoride, trifluoromethane and oxygen, where a gas flow rate of the carbon tetrafluoride is between 100sccm and 200sccm, a gas flow rate of the trifluoromethane is between 100sccm and 300sccm, a gas flow rate of the oxygen is between 5sccm and 15sccm, a pressure of a reaction chamber of the dry etching process is between 5mT and 15mT, a source power is between 300W and 400W, and a bias voltage is between 200V and 250V.
Optionally, a dry etching process is adopted in S5 to form the first recess, and etching gas of the dry etching process includes carbon tetrafluoride, trifluoromethane, oxygen and argon, wherein a gas flow rate of the carbon tetrafluoride is between 100sccm and 200sccm, a gas flow rate of the trifluoromethane is between 100sccm and 200sccm, a gas flow rate of the oxygen is between 10sccm and 20sccm, a gas flow rate of the argon is between 50sccm and 100sccm, a pressure of a reaction chamber of the dry etching process is between 10mT and 15mT, a source power is between 300W and 500W, and a bias voltage is between 200V and 300V.
Optionally, an etching selection ratio of the spacer layer to the reverse space mask layer is greater than an etching selection ratio of the second mask layer to the reverse space mask layer, and is greater than an etching selection ratio of the first mask layer to the reverse space mask layer.
Optionally, the material of the spacer layer is selected from one of the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and silicon oxycarbonitride, the material of the first mask layer is selected from one of the group consisting of photoresist, organic anti-reflection layer material, inorganic anti-reflection layer material and amorphous carbon, and the material of the second mask layer is selected from one of the group consisting of photoresist, organic anti-reflection layer material, inorganic anti-reflection layer material and amorphous carbon.
Optionally, the material of the spacer layer includes silicon nitride, the material of the first mask layer includes photoresist, and the material of the second mask layer includes photoresist.
Optionally, in S6, a dry etching process is used to form the second recess, where the etching gas of the dry etching process includes chlorine gas and oxygen gas, where a gas flow rate of the chlorine gas is between 30sccm and 50sccm, a gas flow rate of the oxygen gas is between 50sccm and 70sccm, a pressure of a reaction chamber of the dry etching process is between 5mT and 15mT, a source power is between 300W and 500W, and a bias voltage is between 100V and 200V.
Optionally, the depth of the second groove is between 30nm and 50 nm.
Optionally, the method for forming the first etching pattern in S1 includes: forming a photoresist layer on the upper surface of the side etching interval sacrificial layer, and photoetching the photoresist layer to form a pre-etched pattern on the side etching interval sacrificial layer; and performing width trimming on the pre-etched pattern by adopting an etching process so as to form a first etched pattern on the side etching interval sacrificial layer.
Optionally, the width of the first etching pattern is smaller than the minimum feature size of the photolithography process, and the width of the first etching pattern is the same as the width of the second groove and the width of the first protrusion structure.
Optionally, the width of the first etching pattern is equal to half of the minimum feature size of the photolithography process.
The present invention also provides a surface planarization structure, comprising: the semiconductor device comprises a semiconductor substrate, a reverse interval mask layer formed on the semiconductor substrate, a groove formed in the reverse interval mask layer and protruding structures formed on two sides of the groove; wherein the raised structure has a flat surface.
Optionally, the depth of the groove is between 30nm and 50 nm.
Optionally, the structure further comprises: and the insulating layer, the etching stop layer and the third mask layer are sequentially formed between the semiconductor substrate and the reverse interval mask layer from bottom to top.
Optionally, the groove and the protruding structure both extend into the semiconductor substrate, wherein the protruding structure on both sides of the groove in the semiconductor substrate has a flat surface.
Optionally, the width of the groove is the same as the width of the protruding structure, and is smaller than the minimum feature size of the photolithography process.
Optionally, the width of the groove is the same as the width of the protruding structure, and is equal to half of the minimum feature size of the photolithography process.
Optionally, the raised structure in the semiconductor substrate comprises an active region.
Optionally, the structure further comprises: and the insulating layer is filled in the groove in the semiconductor substrate.
As described above, the method and the structure for surface planarization by reverse pitch doubling according to the present invention have the following advantages: according to the forming method, through the arrangement of the reverse spacing mask layer, the first mask layer, the undercut spacing sacrificial layer and the second mask layer, the effect of unevenness on the top of the spacing layer on a subsequent process is eliminated while the second groove is formed in the reverse spacing mask layer through the spacing layer, namely, the first protruding structures on two sides of the second groove are provided with flat surfaces; therefore, when the semiconductor substrate is etched through the second groove to form a third groove, the second protruding structures on two sides of the third groove also have flat surfaces; and further, when the structure is used as an active region, the effective area of the active region is greatly increased.
Drawings
Fig. 1 to 6 are schematic structural diagrams illustrating steps in a conventional active region forming method.
Fig. 7 to 21 are schematic structural views illustrating steps in the method for forming a surface planarization structure according to the present invention.
Description of the element reference numerals
101 semiconductor substrate
102 insulating layer
103 etch stop layer
104 etch pattern
105 spacer material layer
106 active region
201 semiconductor substrate
202 insulating layer
203 etch stop layer
204 third mask layer
205 reverse spacer mask layer
206 first mask layer
207 undercut spacer sacrificial layer
208 photoresist layer
209 pre-etch pattern
210 first etch pattern
211 second etch pattern
212 spacer layer
213 second mask layer
214 medial side
215 first groove
216 second recess
217 first bump structure
218 final groove
219 third groove
220 second bump structure
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 7 to fig. 21. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 7 to 21, the present embodiment provides a method for forming a surface planarization structure by using a reverse pitch doubling process, the method comprising:
s1: providing a semiconductor substrate 201, sequentially forming a reverse interval mask layer 205, a first mask layer 206 and a side etching interval sacrificial layer 207 from bottom to top on the semiconductor substrate 201, and forming a first etching pattern 210 on the side etching interval sacrificial layer 207;
s2: performing pattern etching on the undercut spacing sacrificial layer 207 and the first mask layer 206 by using the first etching pattern 210 as a mask pattern until the reverse spacing mask layer 205 is exposed, so as to form a second etching pattern 211 on the reverse spacing mask layer 205; forming a spacer layer 212 and a second mask layer 213 on at least the top surface and the side surface of the second etched pattern 211 in sequence from inside to outside;
s3: removing the portion of the second mask layer 213 higher than the spacer layer 212 until the spacer layer 212 is exposed on the top surface of the second etching pattern 211;
s4: etching the spacer layer 212 and the undercut spacer sacrificial layer 207 on the first mask layer 206 until an inner side 214 of the spacer layer 212 on the first mask layer 206 is exposed;
s5: etching the spacer layer 212 on the side of the first mask layer 206 through the inner side 214 of the spacer layer 212 on the first mask layer 206 until the reverse spacer mask layer 205 is exposed, so as to form a first groove 215 between the first mask layer 206 and the second mask layer 213; and
s6: etching the reverse space mask layer 205 through the first groove 215 to form a second groove 216 in the reverse space mask layer 205 and first protruding structures 217 located at two sides of the second groove 216; wherein the first protrusion structure 217 has a flat surface.
The method for forming the surface planarization structure by using the reverse pitch doubling process according to the present embodiment will be described in detail with reference to fig. 7 to 21.
As shown in fig. 7 to 9, S1: providing a semiconductor substrate 201, sequentially forming a reverse spacer mask layer 205, a first mask layer 206 and a side etching spacer sacrificial layer 207 from bottom to top on the semiconductor substrate 201, and forming a first etching pattern 210 on the side etching spacer sacrificial layer 207.
As an example, as shown in fig. 7, the S1 further includes: a step of forming a third mask layer 204 between the semiconductor substrate 201 and the reverse spacer mask layer 205, or/and a step of sequentially forming an insulating layer 202 and an etching stop layer 203 from bottom to top between the semiconductor substrate 201 and the reverse spacer mask layer 205. Preferably, in this embodiment, the S1 includes: and sequentially forming an insulating layer 202, an etching stop layer 203 and a third mask layer 204 from bottom to top between the semiconductor substrate 201 and the reverse spacer mask layer 205. Further preferably, in this embodiment, the material of the semiconductor substrate 201 includes silicon (Si); forming the insulating layer 202 on the upper surface of the semiconductor substrate 201 by using a thermal oxidation process, wherein the insulating layer 202 is made of silicon dioxide (SiO)2)；And forming the etching stop layer 203 on the upper surface of the insulating layer 202 by using a chemical vapor deposition process, wherein the material of the etching stop layer 203 comprises silicon nitride (SiN).
As an example, as shown in fig. 7 to 9, the method of forming the first etching pattern 210 includes: forming a photoresist layer 208 on the upper surface of the undercut spacing sacrificial layer 207, and performing photolithography on the photoresist layer 208 to form a pre-etched pattern 209 on the undercut spacing sacrificial layer 207; and performing width trimming on the pre-etched pattern 209 by using an etching process to form a first etched pattern 210 on the side-etched spacer sacrificial layer 207.
Specifically, as shown in fig. 8 and 9, the width W1 of the pre-etched pattern 209 is equal to the minimum feature size F of the photolithography process, and the width W2 of the first etched pattern 210 is smaller than the minimum feature size F of the photolithography process; preferably, in the present embodiment, the width W2 of the first etching pattern 210 is equal to half F/2 of the minimum feature size of the photolithography process.
As shown in fig. 10 to 12, S2: performing pattern etching on the undercut spacing sacrificial layer 207 and the first mask layer 206 by using the first etching pattern 210 as a mask pattern until the reverse spacing mask layer 205 is exposed, so as to form a second etching pattern 211 on the reverse spacing mask layer 205; at least the top surface and the side surface of the second etched pattern 211 are sequentially formed with a spacer layer 212 and a second mask layer 213 from the inside to the outside.
As an example, the thickness of the undercut spacer sacrificial layer 207 is not greater than 50% of the thickness of the first mask layer 206, so that the aspect ratio of the second etched pattern 211 is greater than or equal to 3; preferably, the aspect ratio of the second etched pattern is greater than or equal to 5; this is achieved by increasing the aspect ratio of the spacer layer 212 at the sides of the second etch feature 211 and on the reverse spacer mask layer 205 to facilitate the removal of the spacer layer 212 at the sides of the second etch feature 211 without unduly affecting the integrity of the spacer layer 212 between the reverse spacer mask layer 205 and the second mask layer 213 (see fig. 15).
As an example, as shown in fig. 10The second etching pattern 211 may be formed by one etching; the second etching pattern 211 may also be formed by etching the undercut interval sacrificial layer 207 and the first mask layer 206, respectively, that is, by two times of etching. Preferably, in this embodiment, in S2, the second etching pattern 211 is formed by a single dry etching process; wherein the etching gas of the dry etching process comprises carbon tetrafluoride (CF)4) And oxygen (O)2) Carbon tetrafluoride (CF)4) The gas flow rate of (2) is between 100sccm and 200sccm, oxygen (O)2) The gas flow rate of (2) is between 5sccm and 15 sccm; the pressure of the reaction chamber of the dry etching process is between 30mT and 50mT, the source power is between 200W and 300W, and the bias voltage is between 100V and 200V.
Specifically, the material of the first mask layer 206 is selected from one of the group consisting of photoresist, organic anti-reflection layer (BARC) material, inorganic anti-reflection layer (DARC) material and amorphous carbon, and the material of the undercut spacer sacrificial layer 207 is selected from one of the group consisting of organic anti-reflection layer (BARC) material, inorganic anti-reflection layer (DARC) material and amorphous carbon. Preferably, in the present embodiment, the material of the first mask layer 206 includes photoresist, and the material of the undercut spacer sacrificial layer 207 includes an organic anti-reflective coating (BARC) material.
Specifically, as shown in fig. 10 and 11, the width of the second etching pattern 211 is equal to the width W2 of the first etching pattern 210 and equal to the width of the spacer layer 212; preferably, in this embodiment, the width of the second etching pattern 211 is equal to the width of the spacer layer 212 and equal to half F/2 of the minimum feature size of the photolithography process. It should be noted that the width of the second etching pattern 211 is the width of the first protrusion structure 217 to be formed later, and is also the width of the second protrusion structure 219, so that the setting of the width of the first protrusion structure 217, that is, the setting of the width of the second protrusion structure 219, can be realized by setting the width of the second etching pattern 211; the width of the spacer layer 212 is the width of the second groove 216 to be formed later, that is, the width of the third groove 218, so that the setting of the width of the second groove 216, that is, the width of the third groove 218 can be achieved by setting the width of the spacer layer 212.
As shown in fig. 13, S3: the portions of the second mask layer 213 higher than the spacer layer 212 are removed until the spacer layer 212 is exposed on the top surface of the second etching pattern 211.
As an example, in S3, a dry etching process is used to remove a portion of the second mask layer 213 higher than the spacer layer 212, where an etching gas of the dry etching process includes carbon tetrafluoride (CF)4) And oxygen (O)2) Wherein, carbon tetrafluoride (CF)4) The gas flow rate of (2) is between 100sccm and 200sccm, oxygen (O)2) The gas flow of the dry etching process is between 5 and 15sccm, the pressure of a reaction chamber of the dry etching process is between 30 and 50mT, the source power is between 200 and 300W, and the bias voltage is between 100 and 200V.
As another example, in S3, a chemical mechanical polishing process is used to remove the portion of the second mask layer 213 higher than the spacer layer 212.
As shown in fig. 14, S4: the spacer layer 212 and the undercut spacer sacrificial layer 207 on the first mask layer 206 are etched until the inner side 214 of the spacer layer 212 on the first mask layer 206 is exposed, so as to enlarge the non-forward etching surface area of the first mask layer 206, which is beneficial to the selective etching of the spacer layer 212 on the side of the first mask layer 206 without exposing an etching pattern with an extra mask.
As an example, in S4, the spacer layer 212 and the undercut spacer sacrificial layer 207 on the first mask layer 206 are removed by a dry etching process, where an etching gas of the dry etching process includes carbon tetrafluoride (CF)4) Trifluoromethane (CHF)3) And oxygen (O)2) Wherein, carbon tetrafluoride (CF)4) The gas flow rate of (1) is between 100sccm and 200sccm, and trifluoromethane (CHF)3) The gas flow rate of (2) is between 100sccm and 300sccm, oxygen (O)2) The gas flow rate of (2) is between 5sccm and 15sccm, the dry gas isThe pressure of the reaction chamber of the method etching process is between 5mT and 15mT, the source power is between 300W and 400W, and the bias voltage is between 200V and 250V.
As shown in fig. 15, S5: the spacer layer 212 on the side of the first mask layer 206 is etched through the inner side 214 of the spacer layer 212 on the first mask layer 206 until the reverse spacer mask layer 205 is exposed, so as to form a first groove 215 between the first mask layer 206 and the second mask layer 213.
As an example, in S5, the first groove 215 is formed by using a dry etching process, and an etching gas of the dry etching process includes carbon tetrafluoride (CF)4) Trifluoromethane (CHF)3) Oxygen (O)2) And argon (Ar), wherein carbon tetrafluoride (CF)4) The gas flow rate of (1) is between 100sccm and 200sccm, and trifluoromethane (CHF)3) The gas flow rate of (2) is between 100sccm and 200sccm, oxygen (O)2) The gas flow of the dry etching process is between 10 and 20sccm, the gas flow of argon (Ar) is between 50 and 100sccm, the pressure of a reaction chamber of the dry etching process is between 10 and 15mT, the source power is between 300 and 500W, and the bias voltage is between 200 and 300V.
Specifically, the width of the first groove 215 is equal to the width of the spacer layer 212; preferably, in the present embodiment, the width of the first groove 215 is equal to the width of the spacer layer 212 and equal to half F/2 of the minimum feature size of the photolithography process.
As an example, the etch selectivity of the spacer layer 212 to the back space mask layer 205 is greater than the etch selectivity of the second mask layer 213 to the back space mask layer 205, and is greater than the etch selectivity of the first mask layer 206 to the back space mask layer 205.
Specifically, the material of the spacer layer 212 is selected from silicon oxide (SiO)2) Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), and silicon oxycarbonitride (SiCON), wherein the second mask layer 213 is selected from the group consisting of photoresist, organic anti-reflective coating (BARC) material, and inorganic anti-reflective coating (DA) layerRC) material and amorphous carbon. Preferably, in this embodiment, the material of the spacer layer 212 includes silicon nitride (SiN), and the material of the second mask layer 213 includes photoresist.
As shown in fig. 16, S6: etching the reverse space mask layer 205 through the first groove 215 to form a second groove 216 in the reverse space mask layer 205 and first protruding structures 217 located at two sides of the second groove 216; wherein the first protrusion structure 217 has a flat surface.
As an example, in S6, the second groove 216 is formed by using a dry etching process, and an etching gas of the dry etching process includes chlorine gas (Cl)2) And oxygen (O)2) Wherein, chlorine gas (Cl)2) The gas flow rate of (2) is between 30sccm and 50sccm, oxygen (O)2) The gas flow rate of the dry etching process is between 50sccm and 70sccm, the pressure of a reaction chamber of the dry etching process is between 5mT and 15mT, the source power is between 300W and 500W, and the bias voltage is between 100V and 200V.
Specifically, the depth of the second groove 216 is between 30nm and 50 nm. It should be noted that the depth of the second groove 216 should not be too deep, and if the depth of the second groove 216 is too deep, the surface unevenness of the second mask layer 213 in the previous step is easily introduced onto the second groove 216, so that the surface unevenness is further introduced onto the subsequent third groove 219, resulting in the surface unevenness of the second bump structures 220 on both sides of the subsequently formed third groove 219.
Specifically, the width of the second groove 216 is equal to the width of the first groove 215; preferably, in the present embodiment, the width of the second groove 216 is equal to the width of the first groove 215, and is equal to half F/2 of the minimum feature size of the photolithography process.
As shown in fig. 17, the forming method further includes S7: at least the first mask layer 206 and the second mask layer 213 on the top surface of the reverse spacer mask layer 205 are removed.
As shown in fig. 18 to 21, the forming method further includes S8: etching the semiconductor substrate 201 through the second groove 216 to form a third groove 219 in the semiconductor substrate 201 and second protruding structures 220 located at two sides of the third groove 219, wherein the second protruding structures 220 have a flat surface.
As an example, as shown in fig. 18 to 21, the S8 further includes: etching the third mask layer 204 through the second groove 216 until the semiconductor substrate 201 is exposed, so as to form a final groove 218 on the semiconductor substrate 201; etching the semiconductor substrate 201 through the final groove 218 to form a third groove 219 in the semiconductor substrate 201; and/or etching and removing the insulating layer 202 and the etching stop layer 203. Preferably, in this embodiment, the S8 includes: etching the third mask layer 204 through the second groove 216 until the etch stop layer 203 is exposed, so as to form a final groove 218 on the etch stop layer 203; etching the etch stop layer 203, the insulating layer 202 and the semiconductor substrate 201 by using the final groove 218 to form a third groove 219 in the semiconductor substrate 201 and second protruding structures 220 located at two sides of the third groove 219, wherein the second protruding structures 220 have flat surfaces; and then removing the insulating layer 202 and the etching stop layer 203 on the semiconductor substrate 201.
Specifically, as shown in fig. 18 and 19, the width of the third groove 219 is equal to the width of the final groove 218, and is equal to the width of the second groove 216; preferably, in the present embodiment, the width of the third groove 219 is equal to the width of the final groove 218, equal to the width of the second groove 216, and equal to half F/2 of the minimum feature size of the photolithography process.
As an example, when the second bump structure 220 includes an active region, the forming method further includes S9: an insulating material is filled in the third groove 219 to form a shallow trench isolation structure.
The surface planarization structure formed by the method for forming a surface planarization structure using a reverse pitch doubling process according to this embodiment is shown in fig. 17, and includes: the semiconductor device comprises a semiconductor substrate 201, a reverse space mask layer 205 formed on the semiconductor substrate 201, a groove 216 formed in the reverse space mask layer 205, and a protruding structure 217 formed on two sides of the groove 216; wherein the raised structure 217 has a flat surface.
Illustratively, the depth of the grooves 216 is between 30nm and 50 nm.
As an example, as shown in fig. 17, the structure further includes: an insulating layer 202, an etching stop layer 203 and a third mask layer 204 are sequentially formed between the semiconductor substrate 201 and the reverse spacer mask layer 205 from bottom to top.
As an example, as shown in fig. 19 to 21, the groove 216 and the protruding structure 217 each extend into the semiconductor substrate 201, wherein the protruding structures 220 on both sides of the groove 219 in the semiconductor substrate 201 have a flat surface.
Specifically, the width of the groove 216 is the same as the width of the protruding structure 217, and is smaller than the minimum feature size F of the photolithography process. Preferably, the width of the groove 216 is the same as the width of the protruding structure 217, and is equal to half F/2 of the minimum feature size of the photolithography process.
As an example, the raised structure 220 in the semiconductor substrate 201 includes an active region; the structure further includes: an insulating layer filled in the groove 219 in the semiconductor substrate 201 to form a shallow trench isolation structure.
In summary, the surface planarization structure and method formed by the reverse pitch doubling process of the present invention have the following advantages: according to the forming method, through the arrangement of the reverse spacing mask layer, the first mask layer, the undercut spacing sacrificial layer and the second mask layer, the effect of unevenness on the top of the spacing layer on a subsequent process is eliminated while the second groove is formed in the reverse spacing mask layer through the spacing layer, namely, the first protruding structures on two sides of the second groove are provided with flat surfaces; therefore, when the semiconductor substrate is etched through the second groove to form a third groove, the second protruding structures on two sides of the third groove also have flat surfaces; and further, when the structure is used as an active region, the effective area of the active region is greatly increased. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (32)
1. A method of forming a surface planarization structure using a reverse pitch doubling process, the method comprising:
s1: providing a semiconductor substrate, sequentially forming a reverse interval mask layer, a first mask layer and a lateral etching interval sacrificial layer from bottom to top on the semiconductor substrate, and forming a first etching pattern on the lateral etching interval sacrificial layer;
s2: carrying out pattern etching on the side etching interval sacrificial layer and the first mask layer by taking the first etching pattern as a mask pattern until the reverse interval mask layer is exposed, so as to form a second etching pattern on the reverse interval mask layer; forming a spacing layer and a second mask layer from inside to outside in sequence at least on the top surface and the side surface of the second etching pattern;
s3: removing the part of the second mask layer higher than the spacing layer until the spacing layer is exposed on the top surface of the second etching pattern;
s4: etching the spacing layer and the side etching spacing sacrificial layer on the first mask layer until the inner side face of the spacing layer on the first mask layer is exposed;
s5: etching the spacing layer positioned on the side edge of the first mask layer through the inner side surface of the spacing layer on the first mask layer until the reverse spacing mask layer is exposed, so as to form a first groove between the first mask layer and the second mask layer; and
s6: etching the reverse interval mask layer through the first groove to form a second groove and first protruding structures located on two sides of the second groove in the reverse interval mask layer; wherein the first protrusion structure has a flat surface.
2. The method of forming a surface planarization structure using reverse pitch doubling process as claimed in claim 1, further comprising S7: and at least removing the first mask layer and the second mask layer on the upper surface of the reverse interval mask layer.
3. The method of forming a surface planarization structure using reverse pitch doubling process as claimed in claim 2, further comprising S8: and etching the semiconductor substrate through the second groove to form a third groove and second protruding structures positioned on two sides of the third groove in the semiconductor substrate, wherein the second protruding structures are provided with flat surfaces.
4. The method of claim 3, wherein the step of forming a surface planarization structure by reverse pitch doubling is further performed in step S1: forming a third mask layer between the semiconductor substrate and the reverse interval mask layer; the S8 further includes: etching the third mask layer through the second groove until the semiconductor substrate is exposed, so as to form a final groove on the semiconductor substrate; and etching the semiconductor substrate through the final groove to form a third groove in the semiconductor substrate.
5. The method of forming a surface planarization structure using reverse pitch doubling process as claimed in claim 3 or 4, wherein when the second protrusion structure includes an active region, the forming method further comprises S9: and filling an insulating material in the third groove to form a shallow trench isolation structure.
6. The method of claim 3, wherein the step of forming a surface planarization structure by reverse pitch doubling is further performed in step S1: sequentially forming an insulating layer and an etching stop layer from bottom to top between the semiconductor substrate and the reverse spacer mask layer, wherein S8 further includes: and etching and removing the insulating layer and the etching stop layer.
7. The method of claim 1, wherein the thickness of the undercut spacer sacrificial layer is not more than 50% of the thickness of the first mask layer, such that the aspect ratio of the second etched pattern is not less than 3.
8. The method of claim 7, wherein the second etched pattern has an aspect ratio of 5 or more.
9. The method of claim 1, wherein the second etching pattern is formed by a dry etching process in S2.
10. The method of claim 9, wherein the etching gas of the dry etching process comprises carbon tetrafluoride and oxygen, wherein a gas flow rate of the carbon tetrafluoride is between 100sccm and 200sccm, and a gas flow rate of the oxygen is between 5sccm and 15 sccm; the pressure of the reaction chamber of the dry etching process is between 30mT and 50mT, the source power is between 200W and 300W, and the bias voltage is between 100V and 200V.
11. The method as claimed in claim 10, wherein the first mask layer is made of a material selected from the group consisting of photoresist, organic anti-reflective layer material, inorganic anti-reflective layer material and amorphous carbon, and the undercut spacer sacrificial layer is made of a material selected from the group consisting of organic anti-reflective layer material, inorganic anti-reflective layer material and amorphous carbon.
12. The method of claim 11, wherein the first mask layer comprises photoresist and the undercut spacer sacrificial layer comprises an organic anti-reflective layer.
13. The method as claimed in claim 1, wherein a dry etching process is used in S3 to remove the portion of the second mask layer higher than the spacer layer, and the etching gas of the dry etching process includes tetrafluoromethane and oxygen, wherein the flow rate of tetrafluoromethane is 100 sccm-200 sccm, the flow rate of oxygen is 5 sccm-15 sccm, the pressure of the reaction chamber of the dry etching process is 30 mT-50 mT, the source power is 200W-300W, and the bias voltage is 100V-200V.
14. The method of claim 1, wherein a chemical mechanical polishing process is used to remove the portion of the second mask layer higher than the spacer layer in S3.
15. The method as claimed in claim 1, wherein a dry etching process is employed in S4 to remove the spacer layer and the undercut spacer sacrificial layer on the first mask layer, and an etching gas of the dry etching process includes carbon tetrafluoride, trifluoromethane, and oxygen, wherein a gas flow rate of the carbon tetrafluoride is 100 seem to 200 seem, a gas flow rate of the trifluoromethane is 100 seem to 300 seem, a gas flow rate of the oxygen is 5 seem to 15 seem, a reaction chamber pressure of the dry etching process is 5mT to 15mT, a source power is 300W to 400W, and a bias voltage is 200V to 250V.
16. The method as claimed in claim 1, wherein a dry etching process is used in S5 to form the first recess, and an etching gas of the dry etching process includes tetrafluoromethane, trifluoromethane, oxygen, and argon, wherein a gas flow rate of tetrafluoromethane is 100 seem to 200 seem, a gas flow rate of trifluoromethane is 100 seem to 200 seem, a gas flow rate of oxygen is 10 seem to 20 seem, a gas flow rate of argon is 50 seem to 100 seem, a reaction chamber pressure of the dry etching process is 10mT to 15mT, a source power is 300W to 500W, and a bias voltage is 200V to 300V.
17. The method of claim 16, wherein an etch selectivity of said spacer layer to said spacer mask layer is greater than an etch selectivity of said second mask layer to said spacer mask layer and greater than an etch selectivity of said first mask layer to said spacer mask layer.
18. The method as claimed in claim 17, wherein the spacer layer is made of one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and silicon oxycarbonitride, the first mask layer is made of one selected from the group consisting of photoresist, organic anti-reflective layer material, inorganic anti-reflective layer material and amorphous carbon, and the second mask layer is made of one selected from the group consisting of photoresist, organic anti-reflective layer material, inorganic anti-reflective layer material and amorphous carbon.
19. The method of claim 18, wherein the spacer layer comprises silicon nitride, the first mask layer comprises photoresist, and the second mask layer comprises photoresist.
20. The method as claimed in claim 1, wherein a dry etching process is used in S6 to form the second recess, and the etching gas of the dry etching process includes chlorine and oxygen, wherein the flow rate of chlorine is 30sccm to 50sccm, the flow rate of oxygen is 50sccm to 70sccm, the pressure of the reaction chamber of the dry etching process is 5mT to 15mT, the source power is 300W to 500W, and the bias voltage is 100V to 200V.
21. The method of claim 1, wherein the depth of the second recess is between 30nm and 50 nm.
22. The method of claim 1, wherein the step of forming the first etching pattern in S1 comprises: forming a photoresist layer on the upper surface of the side etching interval sacrificial layer, and photoetching the photoresist layer to form a pre-etched pattern on the side etching interval sacrificial layer; and performing width trimming on the pre-etched pattern by adopting an etching process so as to form a first etched pattern on the side etching interval sacrificial layer.
23. The method of claim 22, wherein the width of the first etched pattern is smaller than the minimum feature size of the photolithography process, and the width of the first etched pattern is the same as the width of the second groove and the width of the first protrusion structure.
24. The method of claim 23, wherein the first etch pattern has a width equal to half of a minimum feature size of a photolithography process.
25. A surface planarization structure, comprising: the semiconductor device comprises a semiconductor substrate, a reverse interval mask layer formed on the semiconductor substrate, a groove formed in the reverse interval mask layer and protruding structures formed on two sides of the groove; wherein the raised structure has a flat surface.
26. The surface planarization structure of claim 25, wherein the grooves have a depth of 30nm to 50 nm.
27. The surface planarization structure of claim 25, further comprising: and the insulating layer, the etching stop layer and the third mask layer are sequentially formed between the semiconductor substrate and the reverse interval mask layer from bottom to top.
28. The surface planarization structure of claim 25 or 27, wherein the recess and the raised structure each extend into the semiconductor substrate, wherein the raised structures in the semiconductor substrate on both sides of the recess have a planar surface.
29. The surface planarization structure of claim 28, wherein the groove has a width that is the same as the width of the raised structure and is smaller than the minimum feature size of the photolithography process.
30. The surface planarization structure of claim 29, wherein the recess has a width that is the same as the width of the raised structure and is equal to half of the minimum feature size of a photolithography process.
31. The surface planarization structure of claim 28, wherein the raised structure in the semiconductor substrate comprises an active region.
32. The surface planarization structure of claim 31, further comprising: and the insulating layer is filled in the groove in the semiconductor substrate.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110426761A (en) * | 2018-10-29 | 2019-11-08 | 中国科学院长春光学精密机械与物理研究所 | Cyclic olefine copolymer microlens array with metal diaphragm and preparation method thereof |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6403492B1 (en) * | 2001-02-02 | 2002-06-11 | Advanced Micro Devices, Inc. | Method of manufacturing semiconductor devices with trench isolation |
| KR20040036798A (en) * | 2002-10-24 | 2004-05-03 | 주식회사 하이닉스반도체 | Method of forming a isolation layer in a semiconductor device |
| CN101009225A (en) * | 2005-08-05 | 2007-08-01 | 海力士半导体有限公司 | Planarization method and method for forming interlayer dielectric layers, isolation layer and plug |
| US20090280618A1 (en) * | 2008-05-12 | 2009-11-12 | Texas Instruments Incorporated | Method of Planarizing a Semiconductor Device |
| CN102082117A (en) * | 2009-11-30 | 2011-06-01 | 海力士半导体有限公司 | Method for forming side contact in semiconductor device through self-aligned damascene process |
| CN102157428A (en) * | 2010-02-12 | 2011-08-17 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow trench isolation (STI) structure |
| CN102456739A (en) * | 2010-10-28 | 2012-05-16 | 中国科学院微电子研究所 | Semiconductor structure and forming method thereof |
| CN103715080A (en) * | 2012-09-29 | 2014-04-09 | 中芯国际集成电路制造(上海)有限公司 | Forming method of self-aligned double pattern |
| CN104167357A (en) * | 2013-05-17 | 2014-11-26 | 中国科学院微电子研究所 | Semiconductor device and manufacture method thereof |
| JP2015026657A (en) * | 2013-07-25 | 2015-02-05 | マイクロン テクノロジー， インク． | Semiconductor device manufacturing method |
| US20180012761A1 (en) * | 2013-12-04 | 2018-01-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lithography Using High Selectivity Spacers for Pitch Reduction |
| CN208336151U (en) * | 2018-07-05 | 2019-01-04 | 长鑫存储技术有限公司 | Surface planarisation structure is formed using reversed pitch doubling processes |
-
2018
- 2018-07-05 CN CN201810729139.8A patent/CN110690112A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6403492B1 (en) * | 2001-02-02 | 2002-06-11 | Advanced Micro Devices, Inc. | Method of manufacturing semiconductor devices with trench isolation |
| KR20040036798A (en) * | 2002-10-24 | 2004-05-03 | 주식회사 하이닉스반도체 | Method of forming a isolation layer in a semiconductor device |
| CN101009225A (en) * | 2005-08-05 | 2007-08-01 | 海力士半导体有限公司 | Planarization method and method for forming interlayer dielectric layers, isolation layer and plug |
| US20090280618A1 (en) * | 2008-05-12 | 2009-11-12 | Texas Instruments Incorporated | Method of Planarizing a Semiconductor Device |
| CN102082117A (en) * | 2009-11-30 | 2011-06-01 | 海力士半导体有限公司 | Method for forming side contact in semiconductor device through self-aligned damascene process |
| CN102157428A (en) * | 2010-02-12 | 2011-08-17 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow trench isolation (STI) structure |
| CN102456739A (en) * | 2010-10-28 | 2012-05-16 | 中国科学院微电子研究所 | Semiconductor structure and forming method thereof |
| CN103715080A (en) * | 2012-09-29 | 2014-04-09 | 中芯国际集成电路制造(上海)有限公司 | Forming method of self-aligned double pattern |
| CN104167357A (en) * | 2013-05-17 | 2014-11-26 | 中国科学院微电子研究所 | Semiconductor device and manufacture method thereof |
| JP2015026657A (en) * | 2013-07-25 | 2015-02-05 | マイクロン テクノロジー， インク． | Semiconductor device manufacturing method |
| US20180012761A1 (en) * | 2013-12-04 | 2018-01-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lithography Using High Selectivity Spacers for Pitch Reduction |
| CN208336151U (en) * | 2018-07-05 | 2019-01-04 | 长鑫存储技术有限公司 | Surface planarisation structure is formed using reversed pitch doubling processes |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110426761A (en) * | 2018-10-29 | 2019-11-08 | 中国科学院长春光学精密机械与物理研究所 | Cyclic olefine copolymer microlens array with metal diaphragm and preparation method thereof |
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