CN101009225A

CN101009225A - Planarization method and method for forming interlayer dielectric layers, isolation layer and plug

Info

Publication number: CN101009225A
Application number: CN 200610138973
Authority: CN
Inventors: 崔容寿
Original assignee: Hynix Semiconductor Inc
Current assignee: SK Hynix Inc
Priority date: 2005-08-05
Filing date: 2006-08-07
Publication date: 2007-08-01

Abstract

A method for planarizing a layer of a semiconductor device includes heating the layer to exhibit flowability, and applying pressure through an optically flat surface layer onto the layer to planarize the layer. And the planarizing method further comprises etch-back or chemical-mechanical polishing on the planarized layer.

Description

The method of flattening method, formation interlevel dielectric layer, separator and connector

Technical field

The present invention relates to semiconductor device, more specifically relate to flattening method and use this flattening method to form the method for interlevel dielectric layer (ILD), separator and contact plunger.

Background technology

In the manufacturing of semiconductor device, mainly use the flattening method of applied chemistry mechanical polishing (CMP).In the flattening method of above-mentioned use CMP, carry out mechanism and chemical action simultaneously, thereby they are interact with each other.

More specifically, with pad (pad) and slurry polished wafer.Only rotation has the platform (table) of pad.Rotate head (head) simultaneously and at the pressure that applies specified intensity vibrating head part under the situation of head.By surface tension or vacuum wafer is placed on the head.Wafer surface contacts this pad by the head load with the pressure that is applied to head, in the minim gap between the contact-making surface of slurry inflow wafer and pad.As a result, the protrusion of surface that is included in particle in the slurry and pad is wafer mechanical polishing, is included in chemicals in the slurry and chemically removes from wafer and specify composition.

Fig. 1 is the schematic diagram of explanation by the sample of chemico-mechanical polishing (hereinafter referred to as " CMP ") planarization.

With reference to Fig. 1, the

pattern

111 and 112 with difformity and density is positioned on lower floor 100 or the

Semiconductor substrate.Pattern

111 and 112 comprises the close pattern 111 that has smaller width and closely be provided with and has bigger width and the independent isolation pattern 112 that is provided with.

Interlevel dielectric layer (after this, being called " ILD ") 120 is provided with close pattern 111 thereon and isolates in the lower floor 100 of pattern 112 and forms.ILD 120 is made by various dielectric substances.Particularly, making under the situation of ILD 120 by low-k spin-coating glass (after this, being called " SOG ") by spin coating, because the pattern (topology) of lower floor 100, the uneven surface that ILD 120 has, and have because the different deposition characteristics that

pattern

111 and 112 variation density cause.In the part of the ILD 120 with dense pattern 111 and have between another part of the ILD 120 that isolates pattern 112 and form stepped part (d).Under this situation, with the flattening surface of ILD 120 to carry out technology subsequently.Here, use the cmp planarization method.

Fig. 2 is that explanation uses CMP traditional planar method to form the schematic diagram of the caused problem of ILD.Here, even in different figure, describe, represent with identical reference number with the element among the same or analogous Fig. 2 of Fig. 1.

With reference to Fig. 2, after carrying out the planarization of SOG ILD 120 with CMP, because weak wear resistence, corrosion resistance and the mechanical strength of SOG, the pressure that is applied to SOG ILD 120 produces slight crack 150 in SOG ILD 120, cause various defectives.In addition, during clean subsequently, chemicals can destroy SOG ILD 120.Therefore, comprising SOG ILD 120 and after two ILD structures of the oxide layer 130 that forms on the SOG ILD 120 are made, carrying out the planarization of SOG ILD 120 with CMP.

Yet, in this case, because the thickness of SOG ILD 120 also may produce slight crack 150 in SOG ILD 120.In addition, owing to have big deposit thickness at Waffer edge SOG ILD 120, even therefore SOG ILD 120 is planarized to the object height that with dashed lines 140 is represented, outside the part (A) of the SOG of Waffer edge ILD 120 also can be exposed to.Therefore, chemicals still can destroy SOG ILD 120 during clean subsequently.

Cmp planarizationization is used for forming the separator of isolating device, as shallow trench isolation from (hereinafter referred to as " STI ") layer.When deposition during as the silicon oxide layer of the dielectric layer of separator, the pattern of the silicon oxide layer of the pattern influence deposition of lower floor, the pattern of the oxide layer that deposits during grid exposure-processed subsequently reduces depth of focus (DOF) allowance.In order to address this problem, use cmp planarizationization.

Fig. 3 is explanation forms the method for separator with CMP traditional planar method a schematic diagram

With reference to Fig. 3, in order to form the STI layer, in Semiconductor substrate 160,

form groove

161 and 163, this Semiconductor substrate comprises the bed course 170 for silicon nitride layer, and is dielectric layers 180 filling grooves 161 and 163.After this,, and be separated into the isolation pattern with cmp planarization separator 180, in each pattern fills

groove

161 and 163 corresponding that.

When layer deposited isolating 180, because the difference of density between the pattern, the stepped part of formation between the external zones of the cellular zone of first groove 161 that provides relative high density and relatively little width and second groove 163 that provides relative low-density and big relatively width.In addition, when using bed course 170 to polish separator 180 as the polishing terminating point with CMP, it is poor polishing velocity to occur between cellular zone and external zones.Therefore, after polishing finished, remaining separator 180 had different thickness.

Carrying out under the situation of polishing as the polishing target with cellular zone, variety of issue can appear, part such as separator to be removed 180 remains in external zones, the attenuation of the change circle (181) at the angle of the edge's bed course 170 between cellular zone and external zones and depression (183) and residue bed course 170.Therefore, may cause the erosion that the Semiconductor substrate of being made by silicon 160 is not expected.Under the situation that the part of removed separator 180 is residual,, therefore can not carry out the technology subsequently of removing bed course 170 effectively because bed course 170 does not expose.

In order to solve above-mentioned polishing problem, a method is proposed.In the method; pseudo-pattern by adding bed course 170 forms pseudo-active area to the zone of second groove 163 with quite big width; perhaps earlier has the stepped part that a part that the reverse mask etch-back with the reciprocal transformation of the mask that forms groove is positioned at the separator on the pseudo-active area reduces separator, then with the cmp planarization separator by use.Yet said method needs extra step, and the result makes the complex process that forms separator and increases the cost of carrying out technology.

In addition, another kind of method is proposed.In the method, the silicon dioxide based sizing that replaces normally used smoke-like in CMP with ceria based sizing with high selectivity, be the bed course 170 of silicon nitride layer and be high selectivity between the separator 180 of silicon oxide layer to be implemented in, thereby stop the polishing problem.Yet said method needs expensive ceria based sizing and is used for the new supply arrangement of ceria based sizing.In addition, the ceria based sizing produces cut on separator 180.

Therefore, need develop the flatening process of the improvement of the formation that can be applied to the STI layer.

Summary of the invention

The invention provides a kind of flattening method that is used for producing the semiconductor devices, this method prevents because the defective in the planarization of layer that is arranged in the stepped part of the polished layer that the layer pattern under one deck produce and causes thus.

According to an aspect of the present invention, provide a kind of method of layer of planarization semiconductor device, having comprised: heated described layer to present flowability; Pressurize to carry out planarization to described layer.

Described layer is by a kind of the making that is selected from the group of being made up of photo-curing material, thermosets and thermoplastic.

Described layer should be no more than 300 ℃ to fixed temperature by making at the material that is higher than to presenting flowability under the fixed temperature.

The heating of described layer realizes by stove heating or light radiation.

Described method also be included in described planarization the layer on carry out etch-back or chemico-mechanical polishing.

According to another aspect of the present invention, also provide a kind of method of layer of planarization semiconductor device, having comprised: optics flat surfaces layer has been arranged on the described layer; Heat described layer to present flowability; Pressurize to carry out planarization on described layer by described optics flat surfaces layer; With the described optics flat surfaces layer of removal.

Described optics flat surfaces layer is made by transparent material, and this transparent material allows by the described layer of light irradiation method heating.

The pressure that is applied to described layer is not more than 5psi.

Described method further comprises after removing described optics flat surfaces layer cleans described layer.

According to another aspect of the present invention, provide a kind of method that forms interlevel dielectric layer, having comprised: on semiconductor layer, form metal layer pattern; Deposit described interlevel dielectric layer to cover described metal layer pattern; Heat described interlevel dielectric layer to present flowability; With to the pressurization of described interlevel dielectric layer to carry out planarization.

Described interlevel dielectric layer is made by spin-coating glass (SOG), and this spin-coating glass presents flowability being no more than under 300 ℃ the temperature.

According to another aspect of the present invention, provide a kind of method that forms interlevel dielectric layer, having comprised: on Semiconductor substrate, form metal layer pattern; Deposit described interlevel dielectric layer to cover described metal layer pattern; Optics flat surfaces layer is set on described interlevel dielectric layer; Heat described interlevel dielectric layer to present flowability; By pressurizeing on the described interlevel dielectric layer of described optics flat surfaces course to carry out planarization; With the described optics flat surfaces layer of removal.

Described heating and pressurization are carried out simultaneously.

According to another aspect of the present invention, provide a kind of method that forms separator, having comprised: in Semiconductor substrate, form groove; Form the dielectric layer of filling described groove; On described dielectric layer, form sacrifice layer; Heat described sacrifice layer to present flowability; Pressurize to carry out planarization to described sacrifice layer; And remove the described sacrifice layer of planarization and described dielectric layer successively to form the pattern of separating from described dielectric layer.

Described sacrifice layer is by be selected from a kind of formation the in the group of being made up of photo-curing material, thermosets and thermoplastic to described dielectric layer coating.

Described sacrifice layer is formed by dielectric substance, and described dielectric substance has the removal speed identical with described dielectric layer.

Described sacrifice layer is formed by spin-coating glass (SOG).

The described sacrifice layer of planarization and the removal of described dielectric layer are included in etch-back or chemico-mechanical polishing on described sacrifice layer and the described dielectric layer.

According to a further aspect in the invention, provide a kind of method that forms separator, having comprised: in Semiconductor substrate, form groove; Form the dielectric layer of filling described groove; On described dielectric layer, form sacrifice layer; Heat described sacrifice layer to present flowability; Optics flat surfaces layer is set on described sacrifice layer; Pressurize to carry out planarization by the described sacrifice layer of described optics flat surfaces course; Remove described optics flat surfaces layer; And described sacrifice layer and the described dielectric layer of removing planarization.

According to a further aspect in the invention, provide a kind of method that forms separator, having comprised: in Semiconductor substrate, form groove; Form the dielectric layer of filling described groove; Heat described dielectric layer to present flowability; Pressurize to carry out planarization to described dielectric layer; With the dielectric layer of removing planarization.

Comprise to described dielectric layer pressurization: optics flat surfaces layer is set on described dielectric layer; By pressurizeing on the described dielectric layer of described optics flat surfaces course; With the described optics flat surfaces layer of removal.

According to a further aspect in the invention, provide a kind of method that forms contact plunger, having comprised: on Semiconductor substrate, form interlevel dielectric layer; Formation is passed described dielectric layer and the contact hole that forms; Form the conductive layer of filling described contact hole; On described conductive layer, form sacrifice layer; Heat described sacrifice layer to present flowability; Pressurize to carry out planarization to described sacrifice layer; With sacrifice layer and the conductive layer of removing planarization.

In accordance with a further aspect of the present invention, provide a kind of method that forms contact plunger, having comprised: on Semiconductor substrate, form interlevel dielectric layer; Formation is passed described dielectric layer and the contact hole that forms; Form the conductive layer of filling described contact hole; On described conductive layer, form sacrifice layer; Optics flat surfaces layer is set; Heat described sacrifice layer to present flowability; By pressurizeing on the described sacrifice layer of described optics flat surfaces course to carry out planarization; Remove described optics flat surfaces layer; With sacrifice layer and the conductive layer of removing planarization.

The invention provides a kind of flattening method that is used for producing the semiconductor devices, this method prevents because the defective in the planarization of destination layer that is arranged in the stepped part of the destination layer that layer pattern destination layer under cause and causes thus.

Description of drawings

Following detailed description in conjunction with the drawings can more be expressly understood above-mentioned and other purpose, characteristic and other the advantage of the present invention, wherein:

Fig. 1 is the schematic diagram that a sample of chemico-mechanical polishing (CMP) planarization is adopted in explanation;

Fig. 2 is the schematic diagram that the problem of using CMP traditional planar method to form interlevel dielectric layer and causing is described;

Fig. 3 is that explanation uses CMP traditional planar method to form the schematic diagram of the method for separator;

Fig. 4 to 7 is sectional views that the flattening method of making semiconductor device according to one embodiment of present invention is described;

Fig. 8 to 10 is sectional views that the flattening method of making semiconductor device according to another embodiment of the invention is described;

Figure 11 to 14 is sectional views that the interlayer dielectric layer method that forms semiconductor device according to one embodiment of present invention is described;

Figure 15 to 17 is sectional views that the interlayer dielectric layer method that forms semiconductor device according to another embodiment of the invention is described;

Figure 18 to 24 is sectional views that the separator method that forms semiconductor device according to one embodiment of present invention is described;

Figure 25 to 28 is curve charts that the problem of the separator method that forms semiconductor device according to one embodiment of present invention is described; With

Figure 29 and 30 is sectional views that the contact plunger method that forms semiconductor device according to one embodiment of present invention is described.

Embodiment

Now, describe the preferred embodiments of the present invention in detail with reference to accompanying drawing.

Fig. 4 to 7 has illustrated the sectional view of making the flattening method of semiconductor device according to one embodiment of present invention.

With reference to Fig. 4, pattern 210 is arranged in the lower floor (lower layer) 200, and destination layer 220 is arranged in the lower floor that comprises pattern 210.Here, lower floor 200 can be ILD or Semiconductor substrate.Destination layer 220 is with the layer of planarization, is preferably the ILD layer.

The destination layer 220 for the treatment of planarization is by having mobile material and make being higher than under the assigned temperature, this temperature is no more than 300 ℃.For example, destination layer 220 is by photo-curing material, thermosets, and perhaps thermoplastic is made.Just, destination layer is by showing mobile material or make by applying heat thereon or applying the material that light solidifies from flowable state by heating thereon or adding light.

Demonstrate flowability before the curing and can comprise photoresist and epoxy resin by on it, applying the photo-curing material that the light that is higher than prescribed energy solidifies.Have flowability and can comprise benzocyclobutene (BCB), SOG and anti-reflecting layer (ARC) by on it, applying the thermosets that the heat that is higher than assigned temperature is solidified.Show mobile thermoplastic by on it, applying heat, comprise polymethyl methacrylate (PMMA).

When destination layer 220 is coated in the lower floor 200 that comprises pattern 210, when making hole between destination layer 220 filling patterns 210, destination layer 220 demonstrates because the pattern that pattern 210 causes.Therefore, need to reduce the planarization of exposure process allowance or DOF allowance.

With reference to Fig. 4, the destination layer 220 of planarization is treated in heating.Here, destination layer 220 is heated to above the temperature that this destination layer presents flowability.As mentioned above, destination layer 220 is by presenting mobile material and make being higher than under a certain temperature, and this temperature is no more than 300 ℃.Therefore, when destination layer 220 was heated to above said temperature, destination layer 220 presented flowability.Because environment needs, the heating-up temperature of destination layer 220 may be above 300 ℃.In this case, other device that is not subjected to surpass 300 ℃ of temperature effects must be arranged on 200 li of lower floors.

Destination layer 220 can heat by light irradiation method, and wherein heat is transferred to destination layer 220 by radiant light or stove heating means, and wherein transfer of heat arrives destination layer 220 in stove.

With reference to Fig. 6, to have 220 pressurizations of mobile destination layer by heating.Because destination layer 220 presents flowability, the result flows by the pressure that adds specified intensity.Thereby the upper surface of destination layer 220 flattens.When being pressurized to destination layer 220 and continuing the fixed time, can be with the upper surface planarization of destination layer 220, as shown in Figure 7.

Destination layer 220 can be ILD or other dielectric layer.In addition, destination layer 220 can be such layer: prevent to be positioned at during with cmp planarization destination layer 220 other layer under the destination layer 220 depression, become the layer of circle, attenuation or corrosion.Just, destination layer 220 is the resilient coatings that are used for relaxing the stepped part of lower floor, has improved the polishing uniformity of lower floor like this during with cmp planarization lower floor.

Fig. 8 to 10 is sectional views that the flattening method of making semiconductor device according to another embodiment of the invention is described.Here, even in different figure, describe, represent with identical reference number with the parts among the same or analogous Fig. 8 to 10 of the parts among Fig. 4 to 7.

With reference to Fig. 8, optics flat surfaces layer (optically flat surface layer) 230 is arranged on the destination layer 220.Below, as shown in Figure 9, optics flat surfaces layer 230 heating destination layers 220 and stress on destination layer 220, thereby with the upper surface planarization of destination layer 220.Present flowability by top heating destination layer 220, and the planarization by above-mentioned pressurization.

Therefore, optics flat surfaces layer 230 is used for the surface of planarization destination layer 220.Optics flat surfaces layer 230 can be flat pressing surfaces, and it provides pressure, and it can be to have a kind of mould that adds pressure surface.Although do not show among the figure, provide pressure depression bar (press shaft), all be connected to optics flat surfaces layer 230 as the CD-ROM drive motor and the hydraulic pressure device of the unit that produces pressure.In addition, although do not show among the figure, optics flat surfaces layer 230 is equipped with heating unit, such as heater or heated light sources.

After this, as shown in figure 10, when from destination layer 220 removal optics flat surfaces layers 230, the destination layer 220 that obtains having planarized upper surface.

In the present embodiment, destination layer 220 also by photo-curing material, thermosets, perhaps make by thermoplastic, and particularly by being higher than the material that the assigned temperature that is no more than 300 ℃ presents flowability, for example SOG makes.With light irradiation method heating destination layer 220.In this case, in order to allow optics flat surfaces layer 220 shift heat effectively to destination layer 220, optics flat surfaces layer 220 is made by light transmissive material.Optics flat surfaces layer 230 applies about 5psi or pressure still less to destination layer 220.After this, although do not show among the figure, carry out cleaning, the result removes by contacting the dirt that obtains with optics flat surfaces layer 230 from destination layer 220.

Figure 11 to 14 is sectional views that the interlayer dielectric layer method that forms semiconductor device according to one embodiment of present invention is described.

At first, with reference to Figure 11, in dielectric lower floor 300, form metallic circuit layer pattern 310.After this, use with the same method of above-mentioned destination layer 220 and form ILD320 comprising in the dielectric lower floor 300 of metallic circuit layer pattern 310.For example, ILD320 is by presenting mobile SOG and make being higher than the assigned temperature that is no more than 300 ℃.Because environment needs, can replace the metallic circuit layer pattern to be arranged in the dielectric lower floor 300 with other pattern.

After this, with reference to Figure 12, ILD320 is heated to above assigned temperature.Heating-up temperature is that ILD320 presents mobile temperature.Carry out the heating of ILD320 by light irradiation method or stove heating means.

After this, with reference to Figure 13, be pressurized to by heating and have on the mobile ILD320.Because ILD320 presents flowability, the upper surface of the pressure ILD320 by imposing specified intensity flattens.Therefore the pressure by applying certain hour is to ILD320, as shown in figure 14, and with the upper surface planarization of ILD320.

Figure 15 to 17 is sectional views that the interlayer dielectric layer method that forms semiconductor device according to another embodiment of the invention is described.Here, even in different figure, describe, represent with identical reference number with the element among the same or analogous Figure 15 to 17 of the parts among Figure 11 to 14.

At first, as shown in figure 15, optics flat surfaces layer 330 is arranged on the ILD 320.In the present embodiment, ILD 320 also is by presenting mobile SOG under the assigned temperature that is no more than 300 ℃ and make being higher than.

After this, as shown in figure 16, optics flat surfaces layer 330 heating ILD 320 and be pressurized to ILD320, thereby with the upper surface planarization of ILD 320.Present flowability by top heating ILD 320, and by top pressurization with its planarization.

After this, as shown in figure 17, when from ILD 320 removal optics flat surfaces layers 330, the ILD 320 that obtains having flat upper surfaces.After this, can carry out the processing of the pattern of the ILD 320 that forms planarization according to purpose.

Figure 18 to 24 is sectional views that the separator method that forms semiconductor device according to one embodiment of present invention is described.

Material is being heated under the condition of assigned temperature, under the optics flat surfaces course situation that for example pressurize in the surface that is being higher than the deposition materials that presents flowability under the assigned temperature of SOG, material (globally) planarization all sidedly.Said method proposes a kind of technology, and it is used to use the above-mentioned fact, by the cmp planarization separator and after being separated into pattern corresponding to groove, improves the uniformity of residue dielectric layer thickness.

Just, at first reduce the stepped part of dielectric layer surface, then by dry ecthing, such as etch-back (etching back) or CMP, with the flattening surface of dielectric layer.Thereby, can prevent after finishing the dielectric layer planarization, during removing the pad silicon nitride striped since some regional residual electricity thickness of dielectric layers inhomogeneous according to dielectric layer below the shape of groove or the defective that density causes.In addition, may stop since the erosion of dielectric layer or attenuation to the erosion of Semiconductor substrate.

With reference to Figure 18, on Semiconductor substrate 410, form bed course 420 according to STI technology.Bed course 420 can comprise silicon nitride layer.Can under silicon nitride layer, form silicon oxide layer extraly as resilient coating.

With reference to Figure 19, with bed course 420 patternings, thereby formation exposes the pattern of the part of part semiconductor substrate 410, is used to form groove, just, exposes the part of the Semiconductor substrate 410 at separator place.

With reference to Figure 20,, thereby form groove 411 with the expose portion etching of Semiconductor substrate 410.

With reference to Figure 21, on Semiconductor substrate 410, form the dielectric layer 430 of filling groove 411.Dielectric layer 430 can comprise silicon oxide layer.Shape and density dielectric layer 430 according to the groove under the dielectric layer 430 can have stepped part 431.

With reference to Figure 22, destination layer 440 or the sacrifice layer that is flattened formed on dielectric layer 430 for the stepped part 431 that reduces dielectric layer 430.The destination layer 440 that is flattened is the same with ILD 320 (among Figure 11) with destination layer 220 (among Fig. 4).

Obtain destination layer 440 by applying photo-curing material, thermosets or thermoplastic to dielectric layer 430.Preferably, in order to separate the separator on the dielectric layer 430, SOG for example obtains destination layer 440 by being coated in the dielectric substance of removing during the technology (that is, etch-back or CMP) with dielectric layer 430 has identical removal speed.

With reference to Figure 23, heating destination layer 440 is to making destination layer 440 present mobile temperature, and is pressurized to the destination layer 440 with flowability.Thereby, first with destination layer 440 planarizations.This technology with reference to Fig. 5 and 6, Fig. 8 and 9 identical with the technology described of Figure 16.

For example, optics flat surfaces layer 450 is arranged on the destination layer 440, the pressure of maximum 5psi is applied to the optics flat surfaces layer 450 of contact target layer 440.Thereby planarization has mobile destination layer 440.Then, from destination layer 440 surface removal optics flat surfaces layers 450.

By light irradiation method, perhaps the stove heating means are carried out the heating of destination layer 440.

After first with destination layer 440 planarizations, with the destination layer 440 of planarization and dielectric layer 430 successively from Semiconductor substrate 410 surface removals.Thereby, as shown in figure 24, form the separator 435 that has corresponding to the pattern of groove 411.Bed course 420 is as the polishing terminating point of CMP.

As mentioned above, after reducing the initial stepped part 431 of dielectric 430, use CMP polishing destination layer 440 and dielectric layer 430 up to the bed course 420 that exposes under the dielectric layer 430 by destination layer 440.Here, because dielectric layer 430 has identical polishing velocity with destination layer 440, therefore during the flatening process they are considered as same one deck in the second time.Thereby, may improve the uniformity of rest layers thickness.

Therefore, use the silicon dioxide based sizing of smog (fume) shape although CMP does not use the ceria based sizing with high selectivity, it can further improve the uniformity of rest layers thickness and the uniformity of polishing layer is possible.Thereby, may reduce the cost of carrying out STI CMP and effectively reduce the cut that causes by the ceria based sizing.

Figure 25 to 28 is curve charts that the separator method of making semiconductor device according to one embodiment of present invention is described.Figure 25 and 26 is a curve chart, illustrates respectively that dielectric layer at the groove of filling isolating device is deposited on the semiconductor device zone and with after the cmp planarizationization, along the stepped part of residue of X section and Y section dielectric layer.Shown in Figure 25 and 26, in conventional method, has the depth difference of about 2510  and in the depth difference of about 1640  of Y section in the stepped part of X section.

On the other hand, Figure 27 and 28 is a curve chart, illustrates that respectively the dielectric layer at the groove of filling isolating device is deposited on the semiconductor device zone, at first uses destination layer to come planarization, and after adopting CMP planarization for the second time, along the stepped part of residue of X section and Y section dielectric layer.

Shown in Figure 27 and 28, in one embodiment of the present of invention method, stepped part has in the depth difference of about 286  of X section with in the depth difference of about 307  of Y section.Therefore, with the conventional method comparison shown in Figure 25 and 26, one embodiment of the present of invention method has realized the minimizing of the stepped part of dielectric layer.

Figure 18 to 24 illustrates the separator method that forms semiconductor device according to one embodiment of present invention, and wherein the dielectric layer 430 of filling groove 411 forms on Semiconductor substrate 410, and destination layer 440 forms on dielectric layer 430.Yet, can revise said method.

For example, use by having the dielectric layer filling groove 411 that mobile dielectric substance is made such as SOG under the assigned temperature being higher than.The SOG dielectric layer is heated to said temperature, and is pressurized to dielectric layer with flowability.Thereby, first with the dielectric layer planarization.Then, use the dielectric layer for the second time planarization of CMP with planarization first, the result forms the separator that has corresponding to the separation pattern of groove.Here, dielectric layer can be made by photo-curing material, thermosets or thermoplastic.

The above embodiment of the present invention can be applied to the process for fabrication of semiconductor device of other use such as the flattening method of CMP.For example, embodiments of the invention are applied to the technology that forms contact plunger, wherein depositing conducting layer and separate (nodeseparation) with the node of realizing conductive layer with cmp planarizationization.

With reference to Figure 29, on Semiconductor substrate 510, form the ILD530 that comprises such as gate stack 520 structures.Can form ILD 530 according to the method identical with reference to Figure 10 to 17 with ILD 320 (Figure 17).Each gate stack 520 comprises grid oxic horizon 521, grid conducting layer 523, hard mask 525 and clearance wall 527.

After this, for other capacitor or the bit line that is electrically connected Semiconductor substrate 510 and forms thereon, pass ILD 530 and form contact hole 531.Here, between gate stack 520, can form a plurality of contact holes respectively, perhaps can form linear or the band shape contact hole so that contact hole can be separated into a plurality of sub-contact holes by gate stack 520.

After this, the conductive layer 540 of deposition filling contact hole 531, for example conductive polycrystalline silicon floor on Semiconductor substrate 510.The pattern that conductive layer 540 has has the stepped part based on the pattern of the pattern of contact hole 531 or other pattern.

On conductive layer 540, form the destination layer 550 for the treatment of planarization.Destination layer 550 is used to reduce the stepped part of conductive layer 540.The same method of describing by reference Figure 22 forms destination layer 550.After this, destination layer 550 is heated to destination layer 550 and presents mobile temperature, and to having 550 pressurizations of mobile destination layer.Thereby, with destination layer 550 planarizations.This process is identical with the technology of describing with reference to Figure 23.

After this, as shown in figure 31, the destination layer 550 of planarization and conductive layer 540 successively from Semiconductor substrate 510 surface removals, are preferably used CMP.Use preferably includes the hard mask 525 of silicon nitride layer and carries out CMP as the polishing terminating point.Thereby, forming contact plunger 541, this contact plunger is separated mutually corresponding to the contact hole between gate stack 520 531.

Treat that the use of the destination layer 550 of planarization has reduced the stepped part of conductive layer 540, thereby improved the polishing uniformity among the CMP, separate with the node of realizing contact plunger 541.Thereby, can prevent owing to excessive polishing causes the bridge joint of contact plunger 541 or damages hard mask 521.

In addition, in usefulness other process for fabrication of semiconductor device, can use destination layer of the present invention, to improve polishing uniformity as the flattening method of CMP.

Obviously, from above-mentioned explanation, the invention provides the flattening method of making semiconductor device and use it to form the method for interlevel dielectric layer.Compare with the traditional planar method of using CMP, the amount of the amount of the chemicals that method minimizing of the present invention consumes and the byproduct of generation, thus reduce because the defective that byproduct produces.Method of the present invention does not need pseudo-pattern, needs this puppet pattern in the traditional planar method of using CMP, thereby prevents because the device performance characteristics that the parasitic capacitance of pseudo-pattern generating causes becomes bad.

In addition, the invention provides the method that forms separator, this method has reduced the thickness difference of the dielectric layer residue that the initial stepped part by dielectric layer causes effectively.Therefore, method of the present invention is not used the ceria based sizing with high selectivity.Thereby, can stop owing to use the cut of ceria based sizing on the surface of separator.In addition, method of the present invention is not used reverse mask (reversemask) and in order to prevent because of not exposing the etch process of the incomplete removal bed course that causes.As a result, can simplify technology that forms separator and the manufacturing cost that reduces separator.

Although disclose the preferred embodiments of the present invention for illustrative purposes, it will be apparent to those skilled in the art various modifications, increase and the replacement that to carry out, and do not leave as disclosed scope and spirit of the present invention in the claim.

Claims

A planarization semiconductor device the layer method, comprising:

Heat described layer to present flowability;

Pressurize to carry out planarization to described layer.
2. method according to claim 1, wherein said layer is by a kind of the making that is selected from the group of being made up of photo-curing material, thermosets and thermoplastic.
3. method according to claim 1, wherein said layer should be no more than 300 ℃ to fixed temperature by making at the material that is higher than to presenting flowability under the fixed temperature.
4. method according to claim 1, the heating of wherein said layer realizes by stove heating or light radiation.
5. method according to claim 1 also comprises:

On the layer of described planarization, carry out etch-back or chemico-mechanical polishing.
A planarization semiconductor device the layer method, comprising:

Optics flat surfaces layer is arranged on the described layer;

Heat described layer to present flowability;

Pressurize to carry out planarization on described layer by described optics flat surfaces layer; With

Remove described optics flat surfaces layer.
7. method according to claim 6, wherein said optics flat surfaces layer is made by transparent material, and this transparent material allows by the described layer of light irradiation method heating.
8. method according to claim 6, wherein said layer is by a kind of the making that is selected from the group of being made up of photo-curing material, thermosets and thermoplastic.
9. method according to claim 6, wherein said layer should be no more than 300 ℃ to fixed temperature by making at the material that is higher than to presenting flowability under the fixed temperature.
10. method according to claim 6, the pressure that wherein is applied to described layer is not more than 5psi.
11. method according to claim 6 further comprises after removing described optics flat surfaces layer and cleans described layer.
12. method according to claim 6 also comprises:

On the layer of described planarization, carry out etch-back or chemico-mechanical polishing.
13. a method that forms interlevel dielectric layer comprises:

On semiconductor layer, form metal layer pattern;

Deposit described interlevel dielectric layer to cover described metal layer pattern;

Heat described interlevel dielectric layer to present flowability; With

Pressurize to carry out planarization to described interlevel dielectric layer.
14. method according to claim 13, wherein said interlevel dielectric layer is made by spin-coating glass (SOG), and this spin-coating glass presents flowability being no more than under 300 ℃ the temperature.
15. method according to claim 13 also comprises:

On the interlevel dielectric layer of described planarization, carry out etch-back or chemico-mechanical polishing.
16. a method that forms interlevel dielectric layer comprises:

On Semiconductor substrate, form metal layer pattern;

Deposit described interlevel dielectric layer to cover described metal layer pattern;

Optics flat surfaces layer is set on described interlevel dielectric layer;

Heat described interlevel dielectric layer to present flowability;

By pressurizeing on the described interlevel dielectric layer of described optics flat surfaces course to carry out planarization; With

Remove described optics flat surfaces layer.
17. method according to claim 16, wherein said heating and pressurization are carried out simultaneously.
18. method according to claim 16, wherein said interlevel dielectric layer is made by spin-coating glass (SOG), and this spin-coating glass presents flowability being no more than under 300 ℃ the temperature.
19. method according to claim 16 also comprises:

On the interlevel dielectric layer of described planarization, carry out etch-back or chemico-mechanical polishing.
20. a method that forms separator comprises:

In Semiconductor substrate, form groove;

Form the dielectric layer of filling described groove;

On described dielectric layer, form sacrifice layer;

Heat described sacrifice layer to present flowability;

Pressurize to carry out planarization to described sacrifice layer; And

Remove the described sacrifice layer and the described dielectric layer of planarization.
21. method according to claim 20, wherein said sacrifice layer are by be selected from a kind of formation the in the group of being made up of photo-curing material, thermosets and thermoplastic to described dielectric layer coating.
22. method according to claim 20, wherein said sacrifice layer is formed by dielectric substance, and described dielectric substance has the removal speed identical with described dielectric layer.
23. method according to claim 22, the described dielectric substance that wherein is used for described sacrifice layer are spin-coating glass (SOG).
24. method according to claim 20, wherein the removal of the described sacrifice layer of planarization and described dielectric layer is included in etch-back or chemico-mechanical polishing on described sacrifice layer and the described dielectric layer.
25. a method that forms separator comprises:

In Semiconductor substrate, form groove;

Form the dielectric layer of filling described groove;

On described dielectric layer, form sacrifice layer;

Heat described sacrifice layer to present flowability;

Optics flat surfaces layer is set on described sacrifice layer;

Pressurize to carry out planarization by the described sacrifice layer of described optics flat surfaces course;

Remove described optics flat surfaces layer; And

Remove the described sacrifice layer and the described dielectric layer of planarization.
26. method according to claim 25, wherein the removal of the described sacrifice layer of planarization and described dielectric layer is included in etch-back or chemico-mechanical polishing on described sacrifice layer and the described dielectric layer.
27. a method that forms separator comprises:

In Semiconductor substrate, form groove;

Form the dielectric layer of filling described groove;

Heat described dielectric layer to present flowability;

Pressurize to carry out planarization to described dielectric layer; With

Remove the dielectric layer of planarization.
28. method according to claim 26 wherein comprises to described dielectric layer pressurization:

Optics flat surfaces layer is set on described dielectric layer;

By pressurizeing on the described dielectric layer of described optics flat surfaces course; With

Remove described optics flat surfaces layer.
29. a method that forms contact plunger comprises:

On Semiconductor substrate, form interlevel dielectric layer;

Formation is passed described dielectric layer and the contact hole that forms;

Form the conductive layer of filling described contact hole;

On described conductive layer, form sacrifice layer;

Heat described sacrifice layer to present flowability;

Pressurize to carry out planarization to described sacrifice layer; With

Remove the sacrifice layer and the conductive layer of planarization.
30. a method that forms contact plunger comprises:

On Semiconductor substrate, form interlevel dielectric layer;

Formation is passed described dielectric layer and the contact hole that forms;

Form the conductive layer of filling described contact hole;

On described conductive layer, form sacrifice layer;

Optics flat surfaces layer is set;

Heat described sacrifice layer to present flowability;

By pressurizeing on the described sacrifice layer of described optics flat surfaces course to carry out planarization;

Remove described optics flat surfaces layer; With

Remove the sacrifice layer and the conductive layer of planarization.