CN102270583A - Trench MOS (Metal Oxide Semiconductor) and forming method thereof - Google Patents
Trench MOS (Metal Oxide Semiconductor) and forming method thereof Download PDFInfo
- Publication number
- CN102270583A CN102270583A CN2011102476894A CN201110247689A CN102270583A CN 102270583 A CN102270583 A CN 102270583A CN 2011102476894 A CN2011102476894 A CN 2011102476894A CN 201110247689 A CN201110247689 A CN 201110247689A CN 102270583 A CN102270583 A CN 102270583A
- Authority
- CN
- China
- Prior art keywords
- groove
- layer
- barrier layer
- semiconductor substrate
- polysilicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention relates to a trench MOS (Metal Oxide Semiconductor) and a forming method thereof. The trench MOS comprises a semiconductor substrate, a pad oxide layer formed on the surface of the semiconductor substrate, a trench which is formed in the semiconductor substrate and penetrates through the pad oxide layer, gate oxide layers formed on the bottom and side walls of the trench and a polysilicon layer which is filled in the trench and in flush with the pad oxide layer. The quality of the trench MOS provided by embodiment of the invention is high. According to the processing steps of the forming method of the trench MOS provided by embodiment of the invention, the yield rate of the trench MOS is high.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of groove MOS and forming method thereof.
Background technology
Power metal-oxide-semiconductor field (Power MOSFET) structure has a wide range of applications in boundless field owing to the particularity on the function, for example, and disk drive, automotive electronics and power device or the like aspect.With the power device is example, is applied to the very lagre scale integrated circuit (VLSIC) device of power device, and its output rectifier requires to export about 3.3V voltage and input 10V voltage at input 20V voltage and exports about 1.5V voltage; And require described power device can have the depleted voltage of 10V to 50V scope.Can't satisfy described demand for more existing devices, for example the depleted voltage range of Schottky diode (Schottky diodes) is greatly about 0.5V.
A kind of novel device architecture, trench metal-oxide-semiconductor field (trench-metal-oxide-silicon transistors) are suggested above-mentioned this problem that solves.Be to find more relevant informations of making about groove MOS among the CN102110687A for example at the Chinese patent publication number.But the existing groove MOS formation of employing technology yield is low, the performance of the groove MOS of formation is low.
Summary of the invention
The problem that the present invention solves provides high groove MOS formation method of a kind of yield and the high groove MOS of performance.
For addressing the above problem, the invention provides a kind of groove MOS formation method, comprising: Semiconductor substrate is provided, and described semiconductor substrate surface is formed with cushion oxide layer, and described liner oxidation laminar surface is formed with the barrier layer; Remove the described barrier layer of part, described cushion oxide layer and described Semiconductor substrate successively, form groove; Bottom and sidewall at described groove form grid oxic horizon; Form polysilicon layer at described barrier layer surface, and described polysilicon layer is filled full described groove; The described polysilicon layer of planarization is until exposing described barrier layer; With described barrier layer is mask, the using plasma etching technics, and the described polysilicon layer of etching flushes with described cushion oxide layer until described polysilicon layer; Remove described barrier layer.
Optionally, described barrier material is a silicon nitride.
Optionally, described barrier layer thickness is 400 to 1000 dusts.
Optionally, described barrier layer thickness is 500 dusts.
Optionally, to form technology be depositing operation for described polysilicon layer.
Optionally, the formation technology of described grid oxic horizon is thermal oxidation.
The present invention also provides a kind of groove MOS, comprising: Semiconductor substrate; Be formed on the cushion oxide layer of semiconductor substrate surface; Be formed in the Semiconductor substrate and run through the groove of described cushion oxide layer; Be formed on the gate oxide of channel bottom and sidewall; The polysilicon layer of filling full described groove and flushing with cushion oxide layer.
Compared with prior art, the present invention has the following advantages:
The formation method of the groove MOS of present embodiment, employing forms the barrier layer at semiconductor substrate surface, adopt flatening process plain polycrystalline silicon layer to exposing the barrier layer then earlier, adopting the barrier layer then is mask, and the using plasma etching technics is removed polysilicon layer, flushed with described cushion oxide layer until described polysilicon layer; The groove MOS quality height that forms.Further, the barrier layer as planarization is done on described barrier layer when the planarization polysilicon layer, as the etch mask layer, saves processing step at the etch polysilicon layer.
The polysilicon layer of the groove MOS that present embodiment forms flushes with cushion oxide layer, and surface topography quality height; Thereby make the quality height of groove MOS.
Description of drawings
Fig. 1 is the formation method flow schematic diagram of the groove MOS of one embodiment of the invention;
Fig. 2 is the formation method flow schematic diagram of the groove MOS of another embodiment of the present invention;
Fig. 3 to Fig. 9 is the process generalized section of formation method of the groove MOS of another embodiment of the present invention.
Embodiment
Existing groove MOS formation technology yield is low, the performance of the groove MOS of formation is low, and for this reason, the present inventor forms technology to existing groove MOS and studies, and a kind of formation method of groove MOS at first is provided, and please refer to Fig. 1, comprises the steps:
Step S10 provides Semiconductor substrate;
Step S11, forms groove at the using plasma etching technics in described Semiconductor substrate;
Step S12 form grid oxic horizon at described semiconductor substrate surface, and described grid oxic horizon is positioned at the bottom and the sidewall of groove;
Step S13 forms polysilicon layer at described gate oxidation laminar surface, and described polysilicon layer is filled full described groove;
Step S14 adopts the described polysilicon layer of chemico-mechanical polishing planarization, until exposing described grid oxic horizon.
But, the inventor observes, the groove MOS performance that the formation method of above-mentioned groove MOS forms is good not enough, for this reason, the inventor further discovers: be CMP (Chemical Mechanical Polishing) process at the flatening process in step S14 specifically, and flatening process is controlled stopping of chemico-mechanical polishing by terminal point control (End-Pointing) method, and end-point control method is difficult to the accurate thickness planarization of control, throws thereby make polysilicon layer to be crossed; On the other hand, the homogeneity of chemico-mechanical polishing is also good inadequately, when described polysilicon layer is polished, is easy to form rugged surface topography, makes that the groove MOS performance of follow-up formation is good not enough; In addition, when the chemico-mechanical polishing planarization exposes described grid oxic horizon, be easy to be damaged to described grid oxic horizon, make the further degrade performance of groove MOS.
For this reason, the inventor provides a kind of formation method of groove MOS, please refer to Fig. 2, comprises the steps:
Step S101 provides Semiconductor substrate, and described semiconductor substrate surface is formed with cushion oxide layer, and described liner oxidation laminar surface is formed with the barrier layer;
Step S102 removes the described barrier layer of part, described cushion oxide layer and described Semiconductor substrate successively, forms groove;
Step S103 is at the bottom and the sidewall formation grid oxic horizon of described groove;
Step S104 forms polysilicon layer at described barrier layer surface, and described polysilicon layer is filled full described groove;
Step S105, the described polysilicon layer of planarization is until exposing described barrier layer;
Step S106 is a mask with described barrier layer, the using plasma etching technics, and the described polysilicon layer of etching flushes with described cushion oxide layer until described polysilicon layer;
Step S107 removes described barrier layer.
The specific embodiment of the formation method of below detailed in conjunction with the drawings description groove MOS, above-mentioned purpose and advantage of the present invention will be clearer:
Please refer to Fig. 3, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 surfaces are formed with cushion oxide layer 110, and described cushion oxide layer 110 surfaces are formed with barrier layer 120.
Described Semiconductor substrate 100 can or be silicon-on-insulator (SOI) substrate for silicon-based semiconductor, is example exemplary illustration in addition with the silicon substrate in the present embodiment.
The material of described cushion oxide layer 110 is a silica, the formation technology of described cushion oxide layer 110 is chemical vapour deposition (CVD) or thermal oxidation, described cushion oxide layer 110 is used to avoid the described Semiconductor substrate 100 and the barrier layer 120 of follow-up formation not to match, thereby make that stress is bigger in the whole formation technology, influence forms the quality of technology.
The material on described barrier layer 120 is a silicon nitride, and described barrier layer 120 is used on the barrier layer of subsequent planarization technology as planarization, and described barrier layer 120 can also be as the mask layer of subsequent etching polysilicon; Described barrier layer 120 thickness are 400 to 1000 dusts, and as an embodiment, described barrier layer 120 thickness are 500 dusts.
Please refer to Fig. 4, remove the described barrier layer 120 of part, described cushion oxide layer 110 and described Semiconductor substrate 100 successively, form groove 101.
Described groove 101 is filled polysilicon layer in subsequent technique, form the grid of groove MOS.
The formation step of described groove 101 is: form photoresist figure (not shown) on 120 surfaces, described barrier layer, described photoresist graphical definition goes out follow-up groove to be formed 101; With described photoresist figure is mask, the using plasma etching technics, and the described barrier layer 120 of etching, described cushion oxide layer 110 and described Semiconductor substrate 100 form groove 101 successively.
Please refer to Fig. 5, at the bottom and the sidewall formation grid oxic horizon 130 of described groove 101.
The formation technology of described grid oxic horizon 130 is thermal oxidation, and thermal oxidation technology is carried out in the bottom of described groove 101 and the silicon substrate of sidewall, forms grid oxic horizon 130.
Please refer to Fig. 6, form polysilicon layer 140 on 120 surfaces, described barrier layer and grid oxic horizon 130, and described polysilicon layer 140 is filled full described groove 101.
It is depositing operation that described polysilicon layer 140 forms technology, for example is chemical vapour deposition (CVD).
Described polysilicon layer 140 forms grid behind subsequent chemical-mechanical polishing and plasma etching.
Please refer to Fig. 7, the described polysilicon layer 140 of planarization is until exposing described barrier layer 120.
Described flatening process is a CMP (Chemical Mechanical Polishing) process, described CMP (Chemical Mechanical Polishing) process is planarized to described barrier layer 120 and stops, need to prove, owing to the limitation of flatening process, polysilicon layer 140 patterns bad and described barrier layer 120 damages after described CMP (Chemical Mechanical Polishing) process still can exist polysilicon layer 140 to be thrown, to polish by crossing.
But, because described barrier layer 120 has the thickness of 400 to 1000 dusts, cross the polysilicon layer of throwing 140 and at most only can cross throwing in the thickness of 300-500 dust, and the polysilicon layer 140 of follow-up 400 to 1000 dust thickness can be removed, thereby can not influence the quality of the groove MOS of formation; In addition, polysilicon layer 140 patterns after the polishing rise and fall and also have only the difference in height of 300-500 dust at most, and in before analysis as can be known, the polysilicon layer 140 of follow-up 400 to 1000 dust thickness can be removed, and can not influence the quality of the groove MOS of formation; Also can be removed at subsequent technique as for impaired barrier layer 120, can not influence the quality of the groove MOS of formation equally.
Please refer to Fig. 8, is mask with described barrier layer 120, the using plasma etching technics, and the described polysilicon layer 140 of etching flushes with described cushion oxide layer 110 until described polysilicon layer 140.
Plasma etch process in the employing is a mask with described barrier layer 120, and the described polysilicon layer 140 of etching flushes with described cushion oxide layer 110 until described polysilicon layer 140.
Need to prove, in this step, need to remove the polysilicon layer 140 of 400 to 1000 dust thickness, because in subrange (in the width range of opening), adopt corresponding etching technics parameter, plasma etch process can obtain better planarization effect than CMP (Chemical Mechanical Polishing) process, even the 140 surface topography big rise and falls of described polysilicon layer still can make described polysilicon layer 140 flush with described cushion oxide layer 110.
Further, the present inventor is through a large amount of experiment contrasts, if find directly to adopt the described polysilicon layer 140 of chemico-mechanical polishing planarization, described polysilicon layer 140 is 300 to 500 dusts with described cushion oxide layer 110 differences in height after the planarization; And the described polysilicon layer 140 of using plasma etching technics etching, the polysilicon layer 140 after the etching and the difference in height of described cushion oxide layer 110 are less than 300 dusts, meet the requirement of groove MOS, can think that the described polysilicon layer 140 after the plasma etch process etching flushes with described cushion oxide layer 110.
Please refer to Fig. 9, remove described barrier layer 120.
In the present embodiment, described barrier layer 120 materials are silicon nitride, and removing technology is hot phosphoric acid process, and those skilled in the art can select the corresponding technology of removing according to concrete barrier layer 120 materials, for example: when described barrier layer 120 materials are silica, select the KOH solution removal.
In subsequent technique, can also in described Semiconductor substrate 100, form the source electrode and the drain electrode of groove MOS according to existing processes, here just repeat no more.
The formation method of the groove MOS of present embodiment, employing forms barrier layer 120 on Semiconductor substrate 100 surfaces, adopt flatening process plain polycrystalline silicon layer 140 to exposing barrier layer 120 then earlier, adopt barrier layer 120 to be mask then, the using plasma etching technics is removed polysilicon layer 140, is flushed with described cushion oxide layer 110 until described polysilicon layer 140; The groove MOS quality height that forms.Further, the barrier layer as planarization is done on described barrier layer 120 when planarization polysilicon layer 140, as the etch mask layer, saves processing step at etch polysilicon layer 140.
The groove MOS that adopts above-mentioned formation method to form please refer to Fig. 9, comprising:
The polysilicon layer 140 of the groove MOS that present embodiment forms flushes with cushion oxide layer 110, and surface topography quality height, thereby makes the quality height of groove MOS.
Described groove MOS also comprises: be formed on source electrode and drain electrode in the Semiconductor substrate 100.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (7)
1. the formation method of a groove MOS is characterized in that, comprising:
Semiconductor substrate is provided, and described semiconductor substrate surface is formed with cushion oxide layer, and described liner oxidation laminar surface is formed with the barrier layer;
Remove the described barrier layer of part, described cushion oxide layer and described Semiconductor substrate successively, form groove;
Bottom and sidewall at described groove form grid oxic horizon;
Form polysilicon layer at described barrier layer surface, and described polysilicon layer is filled full described groove;
The described polysilicon layer of planarization is until exposing described barrier layer;
With described barrier layer is mask, the using plasma etching technics, and the described polysilicon layer of etching flushes with described cushion oxide layer until described polysilicon layer;
Remove described barrier layer.
2. the formation method of groove MOS as claimed in claim 1 is characterized in that, described barrier material is a silicon nitride.
3. the formation method of groove MOS as claimed in claim 1 is characterized in that, described barrier layer thickness is 400 to 1000 dusts.
4. the formation method of groove MOS as claimed in claim 3 is characterized in that, described barrier layer thickness is 500 dusts.
5. the formation method of groove MOS as claimed in claim 1 is characterized in that, it is depositing operation that described polysilicon layer forms technology.
6. the formation method of groove MOS as claimed in claim 1 is characterized in that, the formation technology of described grid oxic horizon is thermal oxidation.
7. groove MOS comprises:
Semiconductor substrate;
Be formed on the cushion oxide layer of semiconductor substrate surface;
Be formed in the Semiconductor substrate and run through the groove of described cushion oxide layer;
Be formed on the gate oxide of channel bottom and sidewall;
It is characterized in that, also comprise:
The polysilicon layer of filling full described groove and flushing with cushion oxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102476894A CN102270583A (en) | 2011-08-26 | 2011-08-26 | Trench MOS (Metal Oxide Semiconductor) and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102476894A CN102270583A (en) | 2011-08-26 | 2011-08-26 | Trench MOS (Metal Oxide Semiconductor) and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102270583A true CN102270583A (en) | 2011-12-07 |
Family
ID=45052827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011102476894A Pending CN102270583A (en) | 2011-08-26 | 2011-08-26 | Trench MOS (Metal Oxide Semiconductor) and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102270583A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103000534A (en) * | 2012-12-26 | 2013-03-27 | 上海宏力半导体制造有限公司 | Manufacture method of groove-type P-type metal oxide semiconductor power transistor |
| CN103208426A (en) * | 2013-03-22 | 2013-07-17 | 上海宏力半导体制造有限公司 | Trench type power transistor and production method thereof |
| CN111276389A (en) * | 2020-02-14 | 2020-06-12 | 上海华虹宏力半导体制造有限公司 | Method for forming liner oxide layer in BCD (Bipolar CMOS DMOS) process |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6316329B1 (en) * | 1998-12-30 | 2001-11-13 | Nec Corporation | Forming a trench mask comprising a DLC and ASH protecting layer |
| US20010046750A1 (en) * | 2000-05-24 | 2001-11-29 | Shuji Miyazaki | Method for manufacturing semiconductor device having a STI structure |
| TW200529357A (en) * | 2004-01-20 | 2005-09-01 | Advanced Micro Devices Inc | Method of forming planarized shallow trench isolation |
-
2011
- 2011-08-26 CN CN2011102476894A patent/CN102270583A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6316329B1 (en) * | 1998-12-30 | 2001-11-13 | Nec Corporation | Forming a trench mask comprising a DLC and ASH protecting layer |
| US20010046750A1 (en) * | 2000-05-24 | 2001-11-29 | Shuji Miyazaki | Method for manufacturing semiconductor device having a STI structure |
| TW200529357A (en) * | 2004-01-20 | 2005-09-01 | Advanced Micro Devices Inc | Method of forming planarized shallow trench isolation |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103000534A (en) * | 2012-12-26 | 2013-03-27 | 上海宏力半导体制造有限公司 | Manufacture method of groove-type P-type metal oxide semiconductor power transistor |
| CN103208426A (en) * | 2013-03-22 | 2013-07-17 | 上海宏力半导体制造有限公司 | Trench type power transistor and production method thereof |
| CN111276389A (en) * | 2020-02-14 | 2020-06-12 | 上海华虹宏力半导体制造有限公司 | Method for forming liner oxide layer in BCD (Bipolar CMOS DMOS) process |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103098200B (en) | There is transistor and the manufacture method thereof of metal replacement gate | |
| CN102044426B (en) | Semiconductor device and manufacturing method thereof | |
| TW200737349A (en) | Methods for forming thin oxide layers on semiconductor wafers | |
| CN103227111B (en) | The manufacture method of semiconductor device | |
| CN103137452A (en) | Method for controlling substitute gate structure height | |
| CN102270583A (en) | Trench MOS (Metal Oxide Semiconductor) and forming method thereof | |
| JP2008072032A (en) | Manufacturing method of semiconductor device | |
| US20120064720A1 (en) | Planarization control for semiconductor devices | |
| CN102148183A (en) | Method for forming SOI (Silicon On Insulator) with stepped buried oxide layer | |
| KR100374301B1 (en) | Method for fabricating shallow trench isolation | |
| CN102148181B (en) | Method for forming shallow trench isolation structure | |
| CN102800576A (en) | Method for graphing membrane layer and methods for forming gate and metal oxide semiconductor (MOS) transistor | |
| US20170018432A1 (en) | Manufacturing method of semiconductor structure | |
| US7638394B2 (en) | Method for fabricating trench MOSFET | |
| CN102263030B (en) | Method for manufacturing groove-type power device | |
| TW201533905A (en) | Semiconductor device and method for manufacturing the same | |
| US20120264302A1 (en) | Chemical mechanical polishing process | |
| CN103943487A (en) | Chemical mechanical polish in the growth of semiconductor regions | |
| CN105321884A (en) | Formation method for metal gate device | |
| CN102479742A (en) | Substrate for integrated circuit and formation method thereof | |
| TW202004920A (en) | Semiconductor structure having metal gate and forming method thereof | |
| US20140374885A1 (en) | Narrow gap device with parallel releasing structure | |
| CN102468212B (en) | Method for forming shallow-ditch isolating structure | |
| CN103839796A (en) | Method for forming source electrode polycrystalline silicon | |
| US9704738B2 (en) | Bulk layer transfer wafer with multiple etch stop layers |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140408 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20140408 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: Zuchongzhi road in Pudong Zhangjiang hi tech park Shanghai city Pudong New Area No. 1399 201203 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
|
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20111207 |