CN208507680U - Semiconductor devices - Google Patents

Abstract

The utility model provides a kind of semiconductor devices, which includes: substrate, has channel region；MOS transistor, including the grid being located above the channel region；It is located at the first isolation structure and the second isolation structure of the channel region two sides on the length direction of the grid, first isolation structure has positioned at top and to the channel region the first protrusion outstanding, and second isolation structure has positioned at top and to the channel region the second protrusion outstanding.Compared with prior art, the utility model trench edges form groove, and insulating layer accordingly forms protrusion in groove, so that the thickness of the insulating materials between trench edges and grid increases.Such structure increases the threshold voltage of trench edges position, and the effect for causing threshold voltage to reduce with fringe field offsets, and then improves the reversed narrow-path effect of MOS device.

Description

Semiconductor devices

Technical field

The utility model relates generally to the anti-narrow channel effect of technical field of semiconductors more particularly to a kind of improvement MOS transistor The semiconductor devices answered.

Background technique

Shallow trench isolation (STI, Shallow Trench Isolation) metal-oxide semiconductor (MOS) (MOS, Metal-Oxide Semiconductor) in structure, in the width direction of MOS device, the grid of channel two sides covers portion Divide dielectric isolation layer.In the case where adding gate voltage, since the electric field at grid edge terminates at channel side, lean on trench edges The electric field in the region of nearly STI increases, this electric field keeps the depletion layer of marginal position deeper, and makes the surface potential of trench edges position Increase, enables marginal position transoid earlier.Therefore, threshold voltage (Threshold Voltage, the threshold value of trench edges position Voltage) it is lower than the threshold voltage in channel middle position.This is known as reversed narrow-path effect.

When MOS device width is very big, marginal portion accounting very little, reversed narrow-path effect can be ignored.But with MOS The reduction of device widths, marginal portion accounting is increasing, and the threshold voltage of entire MOS device will be made to reduce.

With the development of integrated circuit processing technique, device size more contract it is smaller, it is anti-narrow in the MOS device of shallow trench isolation Channelling effect bring influences more and more significant.

Currently, the method for improving reversed narrow-path effect needs to increase additional photomask or processing step, higher cost And effect is limited.

Utility model content

The technical problem to be solved by the present invention is to provide a kind of semiconductor devices, can not increase process complexity On the basis of cost, improve MOS transistor reversed narrow-path effect.

In order to solve the above technical problems, the utility model provides a kind of semiconductor devices, comprising: substrate has channel Area；MOS transistor, including the grid being located above the channel region；It is located at the channel on the length direction of the grid The first isolation structure and the second isolation structure of area two sides, first isolation structure have positioned at top and to the channel region First protrusion outstanding, second isolation structure have positioned at top and to the channel region the second protrusion outstanding.

In an embodiment of the utility model, the both ends of the grid in the length direction are located at described On one protrusion and the second protrusion.

In an embodiment of the utility model, the boundary, and/or described second of first protrusion and the channel region Protrusion and the boundary of the channel region are in smooth shape.

In an embodiment of the utility model, first protrusion and/or the second protrusion are in the length side of the grid Upward section is sector.

In an embodiment of the utility model, first protrusion and/or the second protrusion perpendicular to the substrate Direction on size be the grid width 1/5 to 1/3.

It is between first protrusion and the channel region, and/or described second convex in an embodiment of the utility model Liner oxidation layer is formed between portion and the channel region.

In an embodiment of the utility model, the density of the liner oxidation layer is convex greater than first protrusion or second The density in portion.

The utility model also provides a kind of semiconductor devices, comprising: substrate has channel region；MOS transistor, including position Grid on the channel region；It is located at the first isolation structure of the channel region two sides on the length direction of the grid With the second isolation structure；The channel region the first side wall top adjacent with first isolation structure has the first groove, institute Stating the first isolation structure has the first protrusion for projecting to first groove, the channel region and the second isolation structure phase Adjacent second sidewall top has the second groove, and second isolation structure is convex with project to second groove second Portion.

In an embodiment of the utility model, the both ends of the grid in the length direction are located at described On one protrusion and the second protrusion.

Compared with prior art, the utility model has the advantage that the utility model provides a kind of improvement MOS crystal The semiconductor devices of pipe reversed narrow-path effect, trench edges form groove, and insulating layer accordingly forms convex in groove It rises, so that the thickness of the insulating materials between trench edges and grid increases.Such structure makes the threshold value of trench edges position Voltage increases, and the effect for causing threshold voltage to reduce with fringe field offsets, and then improves the anti-narrow channel effect of MOS device It answers.

Detailed description of the invention

Fig. 1 is a kind of top view of semiconductor devices with MOS transistor；

Fig. 2 is the sectional view along A-A of the semiconductor devices with MOS transistor in Fig. 1；

Fig. 3 is the B-B direction cross-sectional view of the semiconductor devices with MOS transistor in Fig. 1；

Fig. 4 is the diagrammatic cross-section according to the semiconductor devices with MOS transistor of an embodiment of the present invention；

Fig. 5 is the diagrammatic cross-section according to the semiconductor devices with MOS transistor of another embodiment of the utility model；

Fig. 6 is the forming method flow chart according to the semiconductor devices of an embodiment of the present invention；

Fig. 7 A-7H is the section signal according to the example process of the formation semiconductor devices of an embodiment of the present invention Figure；

Fig. 8 is the schematic diagram of the result of the semiconductor technology device simulation of an embodiment according to the present utility model.

Specific embodiment

It is practical to this below in conjunction with attached drawing for the above objects, features, and advantages of the utility model can be clearer and more comprehensible Novel specific embodiment elaborates.

Many details are explained in the following description in order to fully understand the utility model, but this is practical new Type can also be implemented using other different from other way described herein, therefore the utility model is not by following public tool The limitation of body embodiment.

As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising" Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus The step of may also including other or element.

When the utility model embodiment is described in detail, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general ratio Example makees partial enlargement, and the schematic diagram is example, should not limit the range of the utility model protection herein.In addition, The three-dimensional space of length, width and depth should be included in actual fabrication.

For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper" Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing Other directions.For example, being described as be in other elements or feature " below " or " under " if overturning the device in attached drawing Or the direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " under Side " and " following " can include upper and lower both direction.Device may also have other directions (to be rotated by 90 ° or in its other party To), therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer at two layers " between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.

In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first Be formed as the embodiment directly contacted with second feature, also may include that other feature is formed between the first and second features Embodiment, such first and second feature may not be direct contact.

Fig. 1 is a kind of top view of semiconductor devices 10 with MOS transistor.As shown in Figure 1, having one or more The semiconductor devices 10 of MOS transistor (example one in figure) includes fleet plough groove isolation structure STI 101, active area 102 and grid Pole 103.Semiconductor devices 10 divide for A-A to and B-B direction, wherein B-B direction refers to the length side along MOS transistor grid To, A-A to the width direction referred to along MOS transistor grid, A-A is to vertical with B-B direction.Fleet plough groove isolation structure STI 101 are located at the outside of active area 102, and active area 102 is surrounded.Semiconductor devices 10 with MOS transistor can be applied to The various fields such as power device, circuit control.

Fig. 2 is the sectional view along A-A of the semiconductor devices 10 with MOS transistor in Fig. 1.As shown in Fig. 2, substrate 104 have active area and passive region, form isolation structure of shallow trench STI 101 in passive region, STI 101 defines active area. MOS transistor is formed in active area.MOS transistor includes grid 103, source area 105, drain region 106, channel region 107 and trap Area 108.Between source area 105 and drain region 106, grid 103 is located on channel 107 channel region 107.MOS transistor Structure be it is known in the art, the utility model is no longer discussed in detail.

Fig. 3 is the B-B direction cross-sectional view of the semiconductor devices 10 with MOS transistor in Fig. 1.As shown in figure 3, in shallow ridges In the mos transistor structure of slot isolation STI 101, in the width direction of MOS device, the grid 103 of 107 two sides of channel is covered SI semi-insulation separation layer.In the case where adding gate voltage, since the electric field at grid edge terminates at 107 side of channel, make ditch Electric field of 107 edge of road close to the region of STI 101 increases, this electric field keeps the depletion layer of marginal position deeper, and makes channel The surface potential of marginal position increases, and enables marginal position transoid earlier.Therefore, the threshold voltage of 107 marginal position of channel compares ditch The threshold voltage in road middle position is low, referred to as reversed narrow-path effect.

When MOS device width is very big, marginal portion accounting very little, reversed narrow-path effect can be ignored.But with MOS The reduction of device widths, marginal portion accounting is increasing, and the threshold voltage of entire MOS device will be made to reduce.With integrated The development of circuitry process technology, device size more contract smaller, reversed narrow-path effect bring shadow in the MOS device of shallow trench isolation Sound is more and more significant.Therefore need to provide a kind of improved semiconductor devices, to improve reversed narrow-path effect.

Fig. 4 is the diagrammatic cross-section according to the semiconductor devices 20 with MOS transistor of an embodiment of the present invention. This diagrammatic cross-section is the diagrammatic cross-section of the length direction of the grid of MOS transistor.Semiconductor devices 20 includes MOS crystal The first isolation structure 205, the second isolation structure 206 of pipe 21 and isolation MOS transistor.Although 1 MOS crystal of example in Fig. 4 Pipe, it is to be understood that, semiconductor devices 20 may include multiple MOS transistors.By the first isolation structure between these MOS transistors 205, the second isolation structure 206 is isolated.

Refering to what is shown in Fig. 4, MOS transistor 21 is located in active area.It is appreciated that MOS transistor 21 can be as shown in Figure 2 It like that include the typical structures such as source area, drain region and grid.Fig. 4 is the cross-sectional view of the length direction of the grid of MOS transistor, Therefore source area and drain region are not embodied in Fig. 4.

Semiconductor devices 20 includes substrate 201.Substrate 201 has channel region 202.Source area and drain region are formed in substrate In 201.Channel region 202 is formed between source area and drain region.Channel region 202 can be doped, to be used to adjust MOS transistor The size of threshold voltage.N-type impurity can be mixed, with the threshold voltage for increasing n-MOSFET.It is miscellaneous N-shaped can also to be mixed Matter, to obtain depletion type MOS FET.

MOS transistor 21 includes the grid 203 on channel region 202.The both ends of grid 203 in the longitudinal direction point On the first protrusion 209 and the second protrusion 210 that Wei Yu be not described below.It include grid oxygen between grid 203 and channel region 202 Change layer 204, to prevent 203 being destroyed property of grid from puncturing.The material of grid oxic horizon 204 can be silica (SiO₂) etc..

Semiconductor devices 20 further includes that 202 two sides of channel region are located on the length direction of the grid of each metal-oxide-semiconductor The first isolation structure 205 and the second isolation structure 206.First isolation structure 205 and the second isolation structure 206 form shallow trench Isolation structure.Fleet plough groove isolation structure defines active area.Region on substrate 201 other than fleet plough groove isolation structure is active Area.First isolation structure 205 and the second isolation structure 206 are insulating materials.Insulating materials is, for example, silica, silicon nitride, nitrogen Silica etc..In one embodiment, the first isolation structure 205 and the second isolation structure 206 can be and grid oxic horizon 204 Identical material, such as silicon oxide sio₂。

The first side wall top adjacent with the first isolation structure 205 of channel region 202 has the first groove 207, channel region 202 The second sidewall top adjacent with the second isolation structure 206 has the second groove 208.First groove 207 and/or the second groove 208 can be in smooth shape, can also be in non-smooth shape.Here, smooth groove helps to improve electricity compared to rough groove The uniformity of field.For example, the section of the first groove 207 and/or the second groove 208 on the length direction of grid can be arc Shape, such as arc-shaped or ellipse arc.It is appreciated that shape recited herein be it is rough, can be for various purposes The shape of groove 207 and/or 208 is changed.For example, the groove of arc and the side wall of channel region 202 and/or the friendship of top surface There can also be smooth profile at boundary, to further increase the uniformity of electric field.At this point, groove 207 and/or 208 is approximately Arc.

Size on the direction perpendicular to substrate 201 of first groove 207 and/or the second groove 208 can be with MOS crystal The width of the grid of pipe is related.For example, on the direction perpendicular to substrate 201 of the first groove 207 and/or the second groove 208 Size can be 1/5 to the 1/3 of the width of the grid of corresponding MOS transistor.

First isolation structure 205 has positioned at top and to first protrusion 209 outstanding of channel region 202, the second isolation junction Structure 206 has positioned at top and to second protrusion 210 outstanding of channel region 202.First protrusion 209 is by the first isolation structure 205 project to the formation of the first groove 207, and the second protrusion 210 is to project to 208 shape of the second groove by the second isolation structure 206 At.Since the first protrusion 209 is that the first isolation structure 205 projects to the formation of the first groove 207, the first protrusion 209 Structure with the first groove 207 is complementary.Since the second protrusion 210 is that the second isolation structure 206 projects to the second groove 208 It is formed, therefore the second protrusion 210 is also complementary with the structure of the second groove 208.First protrusion 209 and channel region 202 Boundary, and/or the second protrusion 210 and the boundary of channel region 202 are in smooth shape.First protrusion 209 and/or the second protrusion 210 exist Section on the length direction of grid can be fan-shaped or its variation.First protrusion 209 and/or the second protrusion 210 are vertical It can be related to the width of the grid of MOS transistor in the size on the direction of substrate 201.For example, the first protrusion 209 and/or Size of second protrusion 220 on the direction perpendicular to substrate 201 can be with 1/5 to the 1/ of the width of the grid of MOS transistor 3。

Since the side wall top adjacent with the first isolation structure 205 and the second isolation structure 206 of channel region 202 is provided with the One groove 207 and the second groove 208, the first isolation structure 205 and the second isolation structure 206 have correspondingly formed the first protrusion 209 and second protrusion 210, so that the thickness of grid oxide layer of trench edges increases, the threshold voltage of trench edges position increases, The effect for causing threshold voltage to reduce with fringe field offsets, and then improves the reversed narrow-path effect of MOS device.

In another embodiment of the utility model, referring to Fig. 5, between the first protrusion 209 and channel region 202, and/or Liner oxidation layer (linear oxide) 211 is formed between two protrusions 209 and channel region 202.Liner oxidation layer (linear Oxide) 211 with a thickness of 1-5nm.

Liner oxidation layer 211 can be and aoxidizing the material on the first groove 207 and/or the second groove 208 It obtains, to change the profile of the first groove 207 and/or the second groove 208.

In an example, liner oxidation layer 211 is formed by thermally grown.The density of liner oxidation layer 211 be greater than pair The density of the first protrusion 209 or the second protrusion 210 in the groove answered.

Since the forming process of liner oxidation layer 211 changes the profile of the first groove 207 and/or the second groove 208, So that the profile of the first groove 207 and/or the second groove 208 is more smooth, electric field is improved in the uniformity of part.

Fig. 6 is the forming method flow chart according to the semiconductor devices of an embodiment of the present invention.Fig. 7 A-7H is basis The diagrammatic cross-section of the example process of the formation semiconductor devices of an embodiment of the present invention.It is described below with reference to Fig. 6-7H The forming method of the semiconductor devices of the present embodiment.The forming method packet of the semiconductor devices of the embodiment of the utility model It includes:

Step 302, substrate is provided.

Substrate is provided, substrate is that subsequent step provides a supporting role and good electric property.The material of substrate can be with It is silicon carbide (SiC), silicon (Si) etc..Substrate generally requires pretreatment, for improving the adhesive ability of substrate surface.Improve substrate The method of surface-clinging ability includes evaporating the moisture of substrate surface and smearing compound in substrate surface.The compound of smearing It can be hexamethyl-disilazane (hexa-methyl-disilazane, HMDS), trimethyl silyl diethylamine (tri- Methyl-silyl-diethyl-amime, TMSDEA) etc..

Step 304, channel region is formed in the substrate.

The step of forming channel region in the substrate includes: to perform etching to substrate, with the first isolation junction corresponding in substrate Structure, the second isolation structure position be respectively formed first groove, second groove, substrate between first groove and second groove is made For the channel region.

Forming channel region in the substrate may refer to the example process of Fig. 7 A-7E.

In the sectional view of the semiconductor structure exemplified by Fig. 7 A, etching barrier layer 402 is formed on substrate 401.Only make For example, etching barrier layer 402 may include cushion oxide layer (Pad Oxide) and silicon nitride (SiN) layer.Wherein cushion oxide layer On substrate 401, silicon nitride layer is located on cushion oxide layer.Cushion oxide layer is used to provide for etching barrier layer 402 Buffering, prevents substrate 401 from being generated mechanical damage by larger stress.It will be appreciated by persons skilled in the art that etching resistance Barrier 402 can be other structures or material.For example, etching barrier layer 402 includes photoresist layer and silicon oxide layer.

Fig. 7 B shows the etching barrier layer after patterned process.As shown in Figure 7 B, etching barrier layer 402 passes through After patterned process, section substrate 401 is exposed, and the substrate 401 being exposed forms passive region, and be etched barrier layer The substrate 401 of 402 coverings constitutes active area.The method for patterning etching barrier layer 402 carries out photoetching including the use of photomask.Benefit Carrying out photoetching with photomask is known technology, this is repeated no more.

Below with reference to Fig. 7 C-7D.Fig. 7 C-7D shows the example process to form first groove and second groove.

After being performed etching to etching barrier layer, exposed substrate is performed etching using isotropic etching technique. Isotropic etching refers to that the etch rate of all directions is consistent, and in the present embodiment, all directions refer to transverse direction And vertical direction.Specifically, with reference to Fig. 7 C, the substrate 401 to the first of passive region is longitudinally etched using isotropic etching technique Depth, since the etch rate of all directions in isotropic etching is consistent, substrate 401 is also etched on lateral. Isotropic etching can be wet chemical etching technique.Only as an example of isotropic etching, hydrofluoric acid HF can be used With nitric acid HNO₃Isotropic etching is carried out to substrate 401 as etching agent.

Then as illustrated in fig. 7d, the substrate of the passive region is etched to the second depth with shape using anisotropic etch process At first groove and second groove.

Anisotropic etching refers to that the etch rate of all directions is different, and can carry out the etching of larger depth, Perfect anisotropic etching refers to only etching in one direction.In the present embodiment, etching speed in vertical direction Rate is greater than etch rate in a lateral direction.Referring to Fig. 7 D, the substrate 401 of passive region is longitudinally etched using anisotropic etching To the second depth, the second depth is greater than the first depth, since etch rate in vertical direction is greater than in a lateral direction Etch rate, substrate 401 is almost seldom on lateral or is not etched.The numerical value of second depth can be by each to different Property etching parameter control, such as etch period, etching agent temperature etc..Anisotropic etching can be dry plasma quarter Erosion.After isotropic etching and anisotropic etching, first groove 403 and second groove are formd on substrate 401 404.Substrate between first groove 403 and second groove 404 forms channel region.

First groove 403, second groove 404 side wall top be respectively formed the first groove 405 of oriented channel region recess, Second groove 406, so that the top of first groove 403, second groove 404 is prominent to channel region.First groove 405 and second is recessed Shape of the slot 406 on the length direction of grid can be arc, be also possible to other shapes.First groove 405 and second is recessed The shape of slot 406 can control by adjusting the parameter of isotropic etching, such as etching agent concentration, etch period, etching Agent temperature etc..When the isotropism of etching is good, the shape of the first groove 405 and the second groove 406 can be arc-shaped.

After channel region is formed in substrate 401, need to remove etching barrier layer 402, removal etching barrier layer 402 it Substrat structure afterwards is referring to Fig. 7 E.Cleaning agent can be used to remove etching barrier layer 402 by the method for cleaning.Cleaning agent can To be other all kinds of cleaning agents such as phosphoric acid.The first groove 405 and/or the can also be included in after removal etching barrier layer 402 Thermally grown liner oxidation layer on two grooves 406.The thermally grown tip portion that can erode groove.The thickness of liner oxidation layer can be with For 1-5nm.

Step 306, the first isolation structure and the second isolation structure for being located at channel region two sides on direction initialization are formed in.

Be located on direction initialization channel region two sides formed the first isolation structure and the second isolation structure method can be it is heavy Product.Direction initialization refers to the length direction of the grid of MOS transistor.It is filled into first groove 403, second groove 404 exhausted Edge layer, to be respectively formed the first isolation structure and the second isolation structure.The insulating layer being filled in the first groove 405 constitutes first Protrusion 407.The insulating layer being filled in the second groove 406 constitutes the second protrusion 408.The boundary of first protrusion 407 and channel region, And/or second the boundary of protrusion 408 and channel region can be in smooth shape.First protrusion 407 and/or the second protrusion 408 are in grid Length direction on section be sector.First protrusion 407 and/or the second protrusion 408 on the direction perpendicular to substrate 1/5 to 1/3 of width having a size of grid.The formation of first isolation structure and the second isolation structure is referring to Fig. 7 F-7G.Fig. 7 F In, insulating layer 409 is covered in substrate 401, due to the presence of first groove 403 and second groove 404, the surface of insulating layer 409 It is not flat.Planarization process then is carried out to 401 surface of substrate, retains the insulating layer 409 in the groove in passive region.It is flat 401 surface of substrate after smoothization processing referring to Fig. 7 G, wherein the substrate 401 of insulating layer 409 and active area be in it is same Plane.Insulating layer 409 in first groove 403 forms the first isolation structure 410, exhausted in second groove 404 Edge layer 409 forms the second isolation structure 411.

Step 308, MOS transistor is formed.

By step 302-306, the first isolation structure 410 and the second isolation structure 411 have been formed, and are subsequently formed MOS transistor.Forming MOS transistor includes channel doping.Channel doping refers to passing through ion implantation technique in channel region A small amount of alms giver or acceptor impurity ion implanting are entered, to be used to adjust the size of MOS transistor threshold voltage.It can mix N-type impurity, with the threshold voltage for increasing n-MOSFET.P-type impurity can also be mixed, to obtain depletion type MOS FET.This Field technical staff, can also be with it is understood that channel doping might not carry out after isolation structure of shallow trench molding It is carried out on other suitable opportunitys.Such as channel doping can do trap on substrate 401 before isolation structure of shallow trench molding It carries out in the process.

Fig. 7 H shows the semiconductor structure after grid is formed.Referring to Fig. 7 H, grid 412 is formed on channel region. The both ends of grid 412 in the longitudinal direction are located on the first protrusion 407 and the second protrusion 408.Channel region and grid 412 Between can also include that grid oxic horizon is used to prevent the destructive break-down of grid 412.Grid oxic horizon is formed on channel Can be and carried out after forming fleet plough groove isolation structure.The material of grid oxic horizon can be with the first isolation structure and second Isolation structure is identical material, such as silicon oxide sio₂Deng.

MOS transistor includes grid, source area and drain region.After grid is formed, followed by formation MOS transistor Source area and drain region.Source area and drain region are located at channel along the two sides of 412 width direction of grid.Those skilled in the art can What it is with understanding is, it is not limited to be initially formed grid, re-form source area and drain region, can also be initially formed source area and drain electrode Area re-forms grid.

Since the channel region side wall top adjacent with the first isolation structure 410 and the second isolation structure 411 is provided with first Groove 405 and the second groove 406, the first isolation structure 410 and the second isolation structure 411 have correspondingly formed the first protrusion 407 With the second protrusion 408, so that the thickness of grid oxide layer of trench edges increases, the threshold voltage of trench edges position increases, with The effect that fringe field causes threshold voltage to reduce offsets, and then improves the reversed narrow-path effect of MOS device.

Fig. 8 is the schematic diagram of the result of semiconductor technology device simulation.Abscissa is the characteristic size of semiconductor devices, single Position is micron.Ordinate is threshold voltage, and unit is volt.In three isotropic etching depth, isotropic etching depth 1 2 < isotropic etching depth 3 of < isotropic etching depth.Wherein isotropic etching depth 1 can be 0.It can be with from Fig. 8 Find out, within the scope of low characteristic size W, with the increase of isotropic etching depth, the decline of threshold voltage becomes slowly, can See that the reversed narrow-path effect of MOS device is improved.

The application has used particular words to describe embodiments herein.As " one embodiment ", " embodiment ", And/or " some embodiments " means a certain feature relevant at least one embodiment of the application, structure or feature.Therefore, it answers Emphasize and it is noted that " embodiment " or " one embodiment " that is referred to twice or repeatedly in this specification in different location or " alternate embodiment " is not necessarily meant to refer to the same embodiment.In addition, certain in one or more embodiments of the application Feature, structure or feature can carry out combination appropriate.

Although the utility model is described with reference to current specific embodiment, ordinary skill in the art Personnel it should be appreciated that more than embodiment be intended merely to illustrate the utility model, be detached from the spirit of the present invention no In the case of can also make various equivalent change or replacement, therefore, as long as to upper in the spirit of the utility model State the variation of embodiment, modification will all be fallen in the range of following claims.

Claims (9)

1. a kind of semiconductor devices, comprising:

Substrate has channel region；

MOS transistor, including the grid being located above the channel region；

It is located at the first isolation structure and the second isolation structure of the channel region two sides on the length direction of the grid, it is described First isolation structure has positioned at top and to the channel region the first protrusion outstanding, and second isolation structure, which has, to be located at Top and to the channel region the second protrusion outstanding.

2. semiconductor devices according to claim 1, which is characterized in that the both ends of the grid in the length direction It is located on first protrusion and the second protrusion.

3. semiconductor devices according to claim 1, which is characterized in that the side of first protrusion and the channel region Boundary, and/or second protrusion and the boundary of the channel region are in smooth shape.

4. semiconductor devices according to claim 3, which is characterized in that first protrusion and/or the second protrusion are in institute The section on the length direction of grid is stated as sector.

5. semiconductor devices according to claim 1 or 4, which is characterized in that first protrusion and/or the second protrusion Size on the direction perpendicular to the substrate is 1/5 to the 1/3 of the width of the grid.

6. semiconductor devices according to claim 1 or 4, which is characterized in that first protrusion and the channel region it Between, and/or second protrusion and the channel region between be formed with liner oxidation layer.

7. semiconductor devices according to claim 6, which is characterized in that the density of the liner oxidation layer is greater than described the The density of one protrusion or the second protrusion.

8. a kind of semiconductor devices, comprising:

Substrate has channel region；

MOS transistor, including the grid being located above the channel region；

It is located at the first isolation structure and the second isolation structure of the channel region two sides on the length direction of the grid；

The channel region the first side wall top adjacent with first isolation structure has the first groove, first isolation junction Structure has the first protrusion for projecting to first groove, the channel region second sidewall adjacent with second isolation structure Top has the second groove, and second isolation structure has the second protrusion for projecting to second groove.

9. semiconductor devices according to claim 8, which is characterized in that the both ends of the grid in the length direction It is located on first protrusion and the second protrusion.