TWI517402B - Semiconductor device and methods for forming the same - Google Patents

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a trench gate and a method of fabricating the same.

The high-voltage component technology is applied to a high-voltage and high-power integrated circuit. In order to achieve high withstand voltage and high current, the flow of the drive current develops from a planar direction to a vertical direction. At present, a metal oxide semiconductor field effect transistor (MOSFET) having a trench gate is developed, which can effectively reduce the on-resistance and has a large current handling capability.

Figure 1 is a schematic plan view showing a metal oxide semiconductor field effect transistor having a trench gate. The metal oxide semiconductor field effect transistor includes a substrate 500, a gate doping region 510 located in the substrate 500, a trench gate structure 520, and a source doping region 530. The source doping regions 530 are located on both sides of the trench gate structure 520, and the source doping regions 530 are located on both sides of the trench gate structure 520. The source doped region 530 and the trench gate structure 520 have the same length, and the trench gate structure 520 has a depth greater than the depth of the source doped region 530. The direction in which the lengths of the source doping region 530 and the trench gate structure 520 extend is parallel to the extending direction of the length of the drain doping region 510. The metal oxygen The driving current of the semiconductor field effect transistor flows from the drain doping region 510 toward the source doping region 530 and the trench gate structure 520, and flows upward along the sidewall of the trench gate structure 520 to the source. The pole doped region 530 is such that the gate channel width w of the MOSFET is the length of the trench gate structure 520 as viewed from above.

At a fixed gate channel length, the magnitude of the drive current is proportional to the width of the gate channel described above. However, if the gate channel width is increased, the length of the trench gate structure 520 is increased, thereby increasing the size of the semiconductor device.

Therefore, it is necessary to find a novel semiconductor device having a trench gate and a method of fabricating the same that can solve or ameliorate the above problems.

Embodiments of the present invention provide a semiconductor device including a substrate having an active region and a field region located in the active region. At least one trench gate structure is located within the substrate, wherein the field plate region is on a first side of the trench gate structure. At least one source doping region is located in a substrate on a second side of the trench gate structure, wherein the second side is opposite to the first side, and the source doping region is adjacent to a sidewall of the trench gate structure . A drain doped region is located in the substrate of the active region, wherein the field plate region is between the drain doped region and the at least one trench gate structure, and the trench gate structure is viewed from a top view direction The length of the extension direction is perpendicular to the direction in which the length of the drain doped region extends.

Embodiments of the present invention provide a method of fabricating a semiconductor device, including providing a substrate having an active region and a field region located within the active region. At least one trench gate structure is formed in the substrate, wherein the field plate region is located on a first side of the trench gate structure. On a second side of the trench gate structure At least one source doped region is formed in the substrate, wherein the second side is opposite to the first side, and the source doped region is adjacent to a sidewall of the trench gate structure. Forming a drain doped region in the substrate of the active region, wherein the field plate region is between the drain doped region and the trench gate structure, and the trench gate structure is viewed from a top view direction The direction in which the length extends is perpendicular to the direction in which the length of the drain doped region extends.

10‧‧‧active area

20‧‧‧Field area

50‧‧‧Arrow

100, 500‧‧‧ substrate

200, 520‧‧‧ trench gate structure

210‧‧‧ trench

220‧‧‧ dielectric layer

230‧‧‧ gate electrode layer

240‧‧ ‧ field oxide layer

250‧‧ ‧ field plate electrode

300, 530‧‧‧ source doped area

310‧‧‧Doped area

350‧‧‧ Well Area

400, 510‧‧‧汲polar doped area

W, w‧‧‧ gate channel width

Figure 1 is a schematic plan view showing a metal oxide semiconductor field effect transistor having a trench gate.

2A, 3A, and 4A are schematic plan views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

Fig. 2B is a schematic cross-sectional view taken along line 2B-2B' in Fig. 2A.

Fig. 3B is a schematic cross-sectional view taken along line 3B-3B' in Fig. 3A.

Fig. 4B is a schematic cross-sectional view taken along line 4B-4B' in Fig. 4A.

Fig. 5A is a plan view showing a semiconductor device in accordance with another embodiment of the present invention.

Fig. 5B is a schematic cross-sectional view taken along line 5B-5B' in Fig. 5A.

Hereinafter, the fabrication and use of the semiconductor device and the method of manufacturing the same according to embodiments of the present invention will be described. However, it can be easily understood that the embodiments of the present invention provide many combinations. Appropriate inventive concepts can be implemented in a wide variety of specific contexts. The specific embodiments disclosed are merely illustrative of the invention, and are not intended to limit the scope of the invention. In the drawings and the description of the embodiments of the present invention, the same reference numerals are used to refer to the same or similar parts.

Hereinafter, a semiconductor device having a trench gate according to an embodiment of the present invention will be described with reference to FIGS. 4A and 4B, wherein FIG. 4A is a plan view showing a semiconductor device having a trench gate according to an embodiment of the present invention. And Fig. 4B is a schematic cross-sectional view taken along line 4B-4B' in Fig. 4A.

In this embodiment, a semiconductor device having a trench gate includes: a substrate 100, at least one trench gate structure 200, at least one source doped region 300, a drain doped region 400, and a well District 350. The substrate 100 has an active region 10 and a field plate region 20 located within the active region 10. In the present embodiment, the substrate 100 is a single crystal germanium substrate. In other embodiments, the substrate 100 can be a silicon on insulator (SOI) substrate, an epitaxial germanium substrate, a germanium substrate, a compound semiconductor substrate, or other suitable semiconductor substrate. In the present embodiment, the conductivity type of the substrate 100 is n-type, but is not limited thereto. In other embodiments, the conductivity type of the substrate 100 may also be p-type, and its conductivity type may be selected according to design requirements.

The trench gate structure 200 is located within the substrate 100 of the active region 10. Field plate region 20 and well region 350 are respectively located on opposite first and second sides of trench gate structure 200, and a portion of trench gate structure 200 is located within well region 350. In the present embodiment, the conductivity type of the well region 350 is p-type, but is not limited thereto. In other embodiments, the conductivity type of well region 350 can also be n-type, and its conductivity type can be selected according to design needs.

The trench gate structure 200 includes a dielectric layer 220 and a gate electrode layer 230. The dielectric layer 220 is compliantly disposed within a trench 210 in the substrate 100, and the gate electrode layer 230 is disposed on the dielectric layer 220 and fills the trench 210 as shown in FIG. 4B. Dielectric layer 220 acts as a gate dielectric layer and may include oxides, nitrides, oxynitrides, combinations thereof, or other suitable gate dielectric materials. The gate electrode layer 230 may comprise germanium, polysilicon or other conductive material. In the present embodiment, the trench gate structure 200 is an elongated column, and the bottom surface of the elongated column has a rectangular shape, as shown in FIG. 4A. In other embodiments, the bottom surface of the elongated column of the trench gate structure 200 may have an elliptical shape, a rounded rectangular shape, or a polygonal outer shape (not shown).

The source doping region 300 is located in the substrate 100 on the second side of the trench gate structure 200 and is adjacent to a sidewall of the trench gate structure 200. In the present embodiment, the conductivity type of the source doping region 300 is n-type, but is not limited thereto. In other embodiments, the conductivity type of the source doping region 300 may also be p-type, and its conductivity type may be selected according to design requirements. For example, the source doping region 300 may include a p-type dopant (for example, , boron or boron fluoride) or n-type dopants (eg, phosphorus or arsenic).

In the present embodiment, the depth of the source doping region 300 is greater than the depth of the trench gate structure 200, as shown in FIG. 4B. In other embodiments, the depth of the source doped region 300 can be equal to the depth of the trench gate structure 200. In the present embodiment, the length of the source doped region 300 adjacent to the side of the trench gate structure 200 is the same as the width of the trench gate structure 200, as viewed from the top view, as shown in FIG. 4A. Show. In other embodiments, the length of the source doped region 300 adjacent to the side of the trench gate structure 200 may be greater than the width of the trench gate structure 200 (not depicted) Show).

In this embodiment, the semiconductor device having the trench gate may include a plurality of trench gate structures 200 and a plurality of source doped regions 300 correspondingly adjacent to the trench gate structures 200, and the trenches The gate structures 200 are spaced apart from each other, and the source doping regions 300 are also spaced apart from each other. For example, a semiconductor device having a trench gate includes two trench gate structures 200 spaced apart from each other and two source doped regions 300 spaced apart from each other and corresponding to the trench gate structure 200 As shown in Figure 4A. The trench gate structures 200 may have the same shape as each other, and the source doping regions 300 may have the same shape as each other. In another embodiment, the two trench gate structures 200 may have different shapes from each other, and the two source doping regions 300 may have the same or different shapes (not shown) from each other. In other embodiments, two or more trench gate structures 200 may have the same or different outer shape of the trench gate structure 200, and adjacent trench gate structures 200 may have Same or different spacing. The source doping regions 300 may have the same or different outer shape in the two or more source doping regions 300, and the adjacent source doping regions 300 may have the same or different spacing therebetween. It can be understood that the number and shape of the trench gate structure 200 and the corresponding source doping region 300 in FIGS. 4A and 4B are merely illustrative and not limited thereto, and the trench gate structure 200 and The actual number and shape of the corresponding source doped regions 300 depends on the design requirements.

The gate doped region 400 is located within the substrate 100 of the active region 10, and each trench gate structure 200 has the same spacing from the gate doped region 400. The drain doped region 400 is on the first side of the trench gate structure 200, and the field plate region 20 is between the drain doped region 400 and the trench gate structure 200, as shown in Figures 4A and 4B. Shown. In the present embodiment, the conductivity type of the drain doping region 400 is p-type, but is not limited thereto. In other embodiments, the conductivity type of the drain doping region 400 may also be n-type, and the conductivity type may be selected according to design requirements. For example, the gate doping region 400 may include a p-type dopant (eg, boron). Or boron fluoride) or an n-type dopant (for example, phosphorus or arsenic).

In the present embodiment, the extending direction of the length of the trench gate structure 200 (i.e., the X direction) is substantially perpendicular to the extending direction of the length of the gate doping region 400 (i.e., Y) as viewed from the top direction. Direction) as shown in Figure 4A.

In the present embodiment, the semiconductor device having the trench gate further includes a field oxide layer 240 (eg, a local oxidation of silicon (LOCOS) structure) and a field plate electrode 250. The field oxide layer 240 is located in the substrate 100 in the field plate region 20 and protrudes from the substrate 100. The field plate electrode 250 is disposed on the field oxide layer 240 and extends onto the substrate 100 as shown in FIGS. 4A and 4B.

The drive current of the semiconductor device having the trench gate passes from the drain doping region 400 through the field oxide layer 240 and along the extending direction of the trench gate structure 200 perpendicular to the length of the gate doped region 400 ( That is, the two opposite side walls of the Y direction flow horizontally to the corresponding source doping region 300 as indicated by arrow 50 of FIG. 4A. In accordance with an embodiment of the invention, the gate channel width W of a semiconductor device having a trench gate is equal to the depth of the gate electrode layer 230 in the single trench gate structure 200. Since the driving current flows to the source doping region 300 along the opposite sidewalls of the trench gate structure 200, the total gate channel width is twice the depth of the gate electrode layer 230 or the plurality of trench gate structures The sum of the two times the depth of the gate electrode layer 230 in 200.

The metal oxide semiconductor field effect transistor having a trench gate in FIG. 1 has only one trench gate structure 500, and the length of the trench gate structure 500 extends parallel to the gate doping. The direction in which the length of the region 510 extends. The gate width w of the MOSFET having a trench gate is the length of the trench gate structure 500. If the gate width w is increased in order to increase the driving current, the ratio is equal. The area of the semiconductor device is increased.

The semiconductor device of the embodiment of the present invention has a single trench gate structure 200 or a plurality of trench gates spaced apart from each other, compared to the metal oxide semiconductor field effect transistor having a trench gate in FIG. The structure 200, the length of the trench gate structure 200 extends in a direction substantially perpendicular to the length of the drain doping region 400, such that the gate channel width W is the gate in the trench gate structure 200. The depth of the electrode layer 230 can thus control the required gate channel width W by adjusting the depth of the trench gate structure 200 and the source doping region 300.

It can be seen that the trench gate structure is arranged such that its length extends substantially perpendicular to the trench gate structure of the gate doped region compared to the extension direction of the length. When the length of the drain doping region is extended so that the total gate channel width is twice the depth of the gate electrode layer in the trench gate structure, the trench gate structure and source doping are increased. The depth of the region can increase the total gate channel width of the semiconductor device. In addition, since a plurality of trench gate structures spaced apart from each other can be formed in the semiconductor device, the total gate channel width is increased to be twice the depth of the gate electrode layer in the plurality of trench gate structures, Can further improve the drive current and improve Turn on the resistance and effectively increase the efficiency of the device area.

According to an embodiment of the present invention, when the extending direction of the length of the trench gate structure is substantially perpendicular to the extending direction of the length of the drain doping region, the gate channel width of the semiconductor device is in the trench gate structure. When the depth of the gate electrode layer is increased, the total gate area of the trench gate structure can be greatly increased by increasing the device area of a small portion, thereby increasing the driving current and improving the on-resistance. In other words, the trench gate structure according to the embodiment of the present invention can reduce the size of the gate structure and increase the use efficiency of the device area under the same required driving current, thereby reducing the size of the semiconductor device.

5A is a plan view showing a semiconductor device having a trench gate according to another embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along line 5B-5B' of FIG. 5A. schematic diagram. The driving current path and the total gate channel width of the semiconductor device in FIGS. 5A and 5B are the same as those in the semiconductor devices in FIGS. 4A and 4B, and the semiconductor devices in FIGS. 5A and 5B are similar in structure to FIGS. 4A and 4B. Semiconductor device. The difference is that the structure of the semiconductor device in FIGS. 5A and 5B further includes a doped region 310 located in the substrate 100 on the first side of the trench gate structure 200. The doped region 310 has the same conductivity type as the source doped region 300, and is adjacent to the opposite sidewalls of the trench gate structure 200, respectively.

In this embodiment, the depths of the source doping region 300 and the doping region 310 on opposite sides of the trench gate structure 200 are greater than the depth of the trench gate structure 200, as shown in FIG. 5B. . In other embodiments, the depth of the source doped region 300 and the doped region 310 may be equal to the depth of the trench gate structure 200.

In this embodiment, the semiconductor device having the trench gate can be A plurality of trench gate structures 200 and a plurality of source doped regions 300 and a plurality of doped regions 310 correspondingly adjacent to opposite sidewalls of the trench gate structure 200, and the trench gate structures 200 are spaced apart from each other Arranged, the source doped regions 300 and the doped regions 310 on opposite sides of the trench gate structure 200 are also spaced apart from each other. For example, a semiconductor device having a trench gate includes two trench gate structures 200 spaced apart from each other and two spaced apart from each other and corresponding to opposite sidewalls of the two trench gate structures 200 The source doping region 300 and the two doping regions 310 are as shown in FIG. 5A.

According to an embodiment of the present invention, since the opposite sides of the trench gate structure respectively have a source doping region 300 and a doping region 310 having the same conductivity type as the source doping region 300, the current first passes through the doping region. 310 flows along the sidewalls of the gate structure 200 to the source doping region 300, thereby further reducing the resistance in the current path, thereby increasing the driving current of the semiconductor device.

Hereinafter, a method of manufacturing a semiconductor device having a trench gate according to an embodiment of the present invention will be described with reference to FIGS. 2A, 3A and 4A and FIGS. 2B, 3B and 4B, wherein FIGS. 2A, 3A and 4A are diagrams according to the present invention. A schematic plan view of a method of fabricating a semiconductor device having a trench gate according to an embodiment of the invention, and wherein FIG. 2B is a cross-sectional view taken along line 2B-2B' of FIG. 2A, and FIG. 3B is a A schematic cross-sectional view along section line 3B-3B' in Fig. 3A is depicted, and Fig. 4B is a cross-sectional view taken along line 4B-4B' in Fig. 4A.

Referring to FIGS. 2A and 2B, a substrate 100 is provided having an active region 10 and a field plate region 20 located in the active region 10. In the present embodiment, the substrate 100 is a single crystal germanium substrate. In other embodiments, the substrate 100 may be a silicon on insulator (SOI) substrate, an epitaxial germanium substrate, a germanium substrate, A compound semiconductor substrate or other suitable semiconductor substrate. In the present embodiment, the conductivity type of the substrate 100 is n-type, but is not limited thereto. In other embodiments, the conductivity type of the substrate 100 may also be p-type, and its conductivity type may be selected according to design requirements.

The well region 350 can be formed in the substrate 100 through a doping process (eg, an ion implantation process). In the present embodiment, the conductivity type of the well region 350 is p-type, but is not limited thereto. In other embodiments, the conductivity type of well region 350 can also be n-type, and its conductivity type can be selected according to design needs.

Then, a patterned hard mask layer (not shown), such as a tantalum nitride layer, is formed on the substrate 100 through the deposition process and the lithography process to expose the substrate 100 of the field plate region 20. Next, an oxidative growth process is performed to form a field oxide layer 240 (eg, a tantalum partial oxidation structure) in the substrate 100 of the field plate region 20, and protrudes from the substrate 100.

Then, after the hard mask layer is removed, another patterned hard mask layer (not shown) is formed on the substrate 100 through the deposition process and the lithography process to expose a portion of the substrate 100. Then, an etching process (for example, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, or other suitable etching process) is performed to form at least one trench 210 in the substrate 100 so that a part of the trench 210 is located within well zone 350, and field plate zone 20 and well zone 350 are located on opposite first and second sides of trench 210, respectively. For example, two trenches 210 are formed in the substrate 100 as shown in FIG. 2A.

Next, referring to FIGS. 3A and 3B, after removing the hard mask layer (not shown) for forming the trench 210, the doping process (for example, ion implantation process) can be performed, and the trench 210 is Corresponding trenches 210 are formed in the substrate 100 on the two sides. And a plurality of source doped regions 300 spaced apart from each other. In the present embodiment, the conductivity type of the source doping region 300 is n-type, but is not limited thereto. In other embodiments, the conductivity type of the source doping region 300 may also be p-type, and the conductivity type may be selected according to design requirements, for example, through a p-type dopant (eg, boron or boron fluoride). The doping process is performed with an n-type dopant (eg, phosphorus or arsenic) and/or a combination thereof.

In the present embodiment, the two source doping regions 300 may have the same shape as each other, as shown in FIG. 3A. In another embodiment, the two source doping regions 300 may have different shapes (not shown) from each other. In other embodiments, the source doping regions 300 may have the same or different external shapes in the two or more source doping regions 300, and the adjacent source doping regions 300 may have the same or different Pitch. It can be understood that the number and shape of the source doping regions 300 in FIG. 3A are merely illustrative and not limited thereto, and the actual number and shape of the source doping regions 300 depend on design requirements.

In another embodiment, the source doped region 300 and the source doped region respectively adjacent to opposite sidewalls of the trench 210 may be formed in the substrate 100 on opposite sides of the trench 210 through a doping process. 300 doped regions 310 of the same conductivity type, as shown in Figures 5A and 5B.

Please refer to the 4A and 4B drawings, which can be subjected to a deposition process (for example, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD). A process, a thermal oxidation process, or other suitable process), a dielectric material is conformally deposited in each of the trenches 210 to form a dielectric layer 220 as a gate dielectric layer. Dielectric layer 220 can include an oxide, a nitride, an oxynitride, combinations thereof, or other suitable gate dielectric materials.

Then, a conductive material is deposited on each dielectric layer 220 through a deposition process (eg, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, a sputtering process, or a coating process), and is filled The corresponding trenches 210 are formed to form the gate electrode layer 230, thereby forming two trench gate structures 200 spaced apart from each other in the substrate 100, as shown in FIG. 4A. The field plate region 20 and the well region 350 are respectively located on opposite first sides and second sides of the trench gate structure 200, and the source doping region 300 is located in the substrate 100 on the second side of the trench gate structure 200. And a source doped region 300 correspondingly adjacent to a sidewall of a trench gate structure 200.

Gate electrode layer 230 can include germanium, polysilicon or other conductive materials. Alternatively, a field plate electrode 250 may be formed on the field oxide layer 240 through the deposition process and extended onto the substrate 100.

In the present embodiment, the two trench gate structures 200 are all elongated pillars, and the bottom surface of the elongated pillars has a rectangular shape, as shown in FIG. 4A. In another embodiment, the two trench gate structures 200 can have different shapes (not shown) from each other. In other embodiments, the bottom surface of the elongated column of the trench gate structure 200 may have an elliptical shape, a rounded rectangular shape, or a polygonal outer shape (not shown). The two or more trench gate structures 200 may have the same or different outer shape of the trench gate structure 200, and the adjacent trench gate structures 200 may have the same or different spacing between them. It can be understood that the number and shape of the trench gate structure 200 in FIG. 4A are merely illustrative and not limited thereto, and the actual number and shape of the trench gate structure 200 depend on design requirements.

In the present embodiment, the depth of the source doping region 300 is greater than the depth of the trench gate structure 200, as shown in FIG. 4B. In other embodiments, the source The depth of the doped region 300 can be equal to the depth of the trench gate structure 200. In the present embodiment, the length of the source doped region 300 adjacent to the side of the trench gate structure 200 is the same as the width of the trench gate structure 200, as viewed from the top view, as shown in FIG. 4A. Show. In other embodiments, the length of the source doped region 300 adjacent to the side of the trench gate structure 200 may be greater than the width of the trench gate structure 200 (not shown).

Next, a gate doped region 400 is formed in the substrate 100 of the active region 10 through a doping process (eg, an ion implantation process). The field plate region 20 is between the drain doped region 400 and the trench gate structure 200, and each trench gate structure 200 has the same spacing from the gate doped region 400. In the present embodiment, the conductivity type of the drain doping region 400 is p-type, but is not limited thereto. In other embodiments, the conductivity type of the drain doping region 400 may also be n-type, and the conductivity type may be selected according to design requirements, for example, through a p-type dopant (eg, boron or boron fluoride), n A dopant (eg, phosphorus or arsenic) and/or combinations thereof are subjected to a doping process.

In the present embodiment, the extending direction of the length of the trench gate structure 200 (i.e., the X direction) is substantially perpendicular to the extending direction of the length of the gate doping region 400 (i.e., Y) as viewed from the top direction. Direction) as shown in Figure 4A.

The drive current of the semiconductor device having the trench gate passes from the drain doping region 400 through the field oxide layer 240 and along the extending direction of the trench gate structure 200 perpendicular to the length of the gate doped region 400 ( That is, the two opposite side walls of the Y direction flow horizontally to the corresponding source doping region 300 as indicated by arrow 50 of FIG. 4A. In accordance with an embodiment of the invention, the gate channel width W of a semiconductor device having a trench gate is equal to the depth of the gate electrode layer 230 in the single trench gate structure 200. And because the driving current is along the two opposite sides of the trench gate structure 200 The sidewalls flow toward the source doped region 300, such that the total gate channel width is twice the depth of the gate electrode layer 230 or twice the depth of the gate electrode layer 230 in the plurality of trench gate structures 200.

The length of the trench gate structure extends substantially perpendicular to the drain doped region, in accordance with an embodiment of the invention, as compared to the trench gate structure of the drain doped region. When the length is extended so that the total gate channel width is twice the depth of the gate electrode layer in the trench gate structure, the size of the gate structure can be reduced and the device can be increased under the same required driving current. The use efficiency of the area further reduces the size of the semiconductor device.

The semiconductor device and the method for fabricating the same according to the embodiments of the present invention are applicable to a laterally diffused metal oxide semiconductor (LDMOS), an N-channel insulated gate bipolar transistor (N-channel insulated gate bipolar transistor). , NIGBT) and other low voltage, high voltage and very high voltage components.

While the invention has been described above in terms of the preferred embodiments thereof, which are not intended to limit the invention, the invention may be modified and combined with the various embodiments described above without departing from the spirit and scope of the invention. example.

10‧‧‧active area

20‧‧‧Field area

50‧‧‧ drive current

100‧‧‧Substrate

200‧‧‧ Trench gate structure

210‧‧‧ trench

220‧‧‧ dielectric layer

230‧‧‧ gate electrode layer

240‧‧ ‧ field oxide layer

250‧‧ ‧ field plate electrode

300‧‧‧ source doped area

350‧‧‧ Well Area

400‧‧‧汲polar doped area

Claims (23)

A semiconductor device comprising: a substrate having an active region and a field region located in the active region; at least one trench gate structure located in the substrate, wherein the field plate region is located in the at least one trench a first side of the gate structure; at least one source doped region in the substrate on a second side of the at least one trench gate structure, wherein the second side is opposite the first side, and The at least one source doped region is adjacent to a sidewall of the at least one trench gate structure; and a drain doped region is located in the substrate of the active region, wherein the field plate region is located at the drain Between the stray region and the at least one trench gate structure, and extending from a top view direction, an extension direction of the length of the at least one trench gate structure is perpendicular to an extension of a length of the drain doped region direction. The semiconductor device of claim 1, wherein the at least one source doping region has a depth equal to or greater than a depth of the at least one trench gate structure. The semiconductor device of claim 1, wherein the gate channel width of the semiconductor device is a depth of a gate electrode layer in the at least one trench gate structure. The semiconductor device according to claim 1, wherein the at least one trench gate structure is an elongated column, and a bottom surface of the pillar has an elliptical shape, a rounded rectangle, a rectangle or a polygon. Appearance. The semiconductor device of claim 1, wherein the semiconductor device comprises a plurality of trench gate structures and corresponding complex source doped regions, and The trench gate structures are spaced apart from each other, and the source doped regions are spaced apart from each other. The semiconductor device of claim 5, wherein the trench gate structures have the same pitch between each other, and each trench gate structure and the drain doped region have the same The pitch, and wherein the source doped regions have the same spacing between them. The semiconductor device of claim 5, wherein the trench gate structures have different pitches between each, and each trench gate structure has the same relationship with the drain doped region. Spacing, and wherein there is a different spacing between the source doped regions. The semiconductor device of claim 5, wherein the trench gate structures have the same shape. The semiconductor device of claim 5, wherein the trench gate structures have different shapes. The semiconductor device of claim 1, wherein the at least one trench gate structure comprises: a dielectric layer compliantly located in a trench in the substrate; and a gate electrode layer, Located on the dielectric layer and filling the trench. The semiconductor device of claim 1, further comprising: a field oxide layer on the substrate of the field plate region; and a field plate electrode on the field oxide layer. The semiconductor device of claim 1, wherein the semiconductor device further comprises at least one doped region in the substrate on the first side of the at least one trench gate structure, and wherein the at least one Doped region and at least one The source doped regions have the same conductivity type. A method of fabricating a semiconductor device, comprising: providing a substrate having an active region and a field region located in the active region; forming at least one trench gate structure in the substrate, wherein the field plate region is located a first side of the at least one trench gate structure; at least one source doped region is formed in the substrate on a second side of the at least one trench gate structure, wherein the second side is opposite to the second side The first side, and the at least one source doped region is adjacent to a sidewall of the at least one trench gate structure; and a drain doped region is formed in the substrate of the active region, wherein the field plate The region is located between the drain doped region and the at least one trench gate structure, and the length direction of the at least one trench gate structure extends perpendicular to the drain electrode when viewed from a top view direction The extension of the length of the miscellaneous zone. The method of fabricating a semiconductor device according to claim 13, wherein the at least one source doping region has a depth equal to or greater than a depth of the at least one trench gate structure. The method of fabricating a semiconductor device according to claim 13, wherein the gate channel width of the semiconductor device is a depth of a gate electrode layer in the at least one trench gate structure. The method of manufacturing a semiconductor device according to claim 13, wherein the at least one trench gate structure is an elongated column, and a bottom surface of the pillar has an elliptical shape, a rounded rectangle, and a rectangular shape. Or a polygon type. A method of manufacturing a semiconductor device according to claim 13, wherein The semiconductor device includes a plurality of trench gate structures and corresponding complex source doped regions, and wherein the trench gate structures are spaced apart from each other, and the source doped regions are spaced apart from each other. The method of fabricating a semiconductor device according to claim 17, wherein the trench gate structures have the same pitch between each trench gate structure and the drain doping region. Having the same pitch, and wherein the source doped regions have the same spacing between them. The method of fabricating a semiconductor device according to claim 17, wherein the trench gate structures have different pitches between each trench gate structure and the drain doped region. Having the same pitch, and wherein there is a different spacing between the source doped regions. The method of fabricating a semiconductor device according to claim 17, wherein the trench gate structures have the same shape. The method of fabricating a semiconductor device according to claim 17, wherein the trench gate structures have different shapes. The method of fabricating a semiconductor device according to claim 13, further comprising: forming a field oxide layer on the substrate of the field plate region; and forming a field plate electrode on the field oxide layer. The method of fabricating the semiconductor device of claim 13, further comprising forming at least one doped region in the substrate on the first side of the at least one trench gate structure, wherein the at least one doping The region has the same conductivity type as the at least one source doped region.