TWI611505B - Trench isolation structure and methods for forming the same - Google Patents

Abstract

The present invention provides a trench isolation structure including a substrate, a polygonal trench disposed in the substrate, an insulating material disposed in the polygonal trench, and a polygonal top contact structure disposed in the polygonal trench and surrounded by the insulating material, wherein the viewing angle is from above The polygonal top contact structure has the same shape as the polygonal groove. The present invention also provides a method of fabricating a trench isolation structure.

Description

Trench isolation structure and method of manufacturing same

The present invention relates to semiconductor technology, and more particularly to trench isolation structures having a top side contact structure and methods of fabricating the same.

In the semiconductor device, the deep trench isolation structure and the insulating layer in the substrate can be used to form a closed isolation region, and the internal components are electrically isolated from the external components to avoid mutual interference. When it is necessary to apply a bias or ground to the above-mentioned isolation region, a bottom side contact structure or a top side contact structure is usually formed in the substrate.

However, in the prior art, whether it is a bottom contact structure or a top contact structure, an additional photomask is required to define the position of the contact hole to fill the contact structure.

Some embodiments of the present invention provide a trench isolation structure including: a substrate; a polygonal trench disposed in the substrate; an insulating material disposed in the polygonal trench; and a polygonal top contact structure disposed in the polygonal trench and insulated The material surrounds, wherein the polygonal top contact structure from the top view has the same shape as the polygonal groove.

Some embodiments of the present invention provide a manufacturer of trench isolation structures The method includes: providing a substrate; forming a polygonal groove in the substrate; forming an insulating material in the polygonal groove; and forming a polygonal top contact structure in the polygonal groove and surrounded by the insulating material, wherein the top of the polygon is viewed from a top view The contact structure has the same shape as the polygonal groove.

100‧‧‧ trench isolation structure

101‧‧‧ polygonal groove

101a‧‧‧ first side

101b‧‧‧ second side

101c‧‧‧ third side

101d‧‧‧ fourth side

101a', 101b', 101c', 101d'‧‧‧ grooved projections

102, 103, 104, 105‧‧ ‧ vertices

110‧‧‧Polygonal top contact structure

110’‧‧‧Electrical materials

110a', 110b', 110c', 110d'‧‧‧ top contact protrusion

201‧‧‧Base

202‧‧‧First semiconductor layer

203‧‧‧Insulation

204‧‧‧Second semiconductor layer

205‧‧‧Shallow trench isolation structure

206‧‧‧First dielectric layer

207‧‧‧ patterned mask

207a, 209’ ‧ ‧ openings

208‧‧‧Insulation materials

209‧‧‧Contact hole

210‧‧‧Doped area

211‧‧‧Second dielectric layer

212‧‧‧through hole

213‧‧‧metal layer

A, B, C, D, E‧‧‧ semiconductor component area

R‧‧‧ area

T, W ₃ ‧ ‧ thickness

W ₁ ‧‧‧flat width

W ₂ ‧‧‧ diagonal width

W ₄ , W ₅ ‧ ‧ width

Θ1, θ2, θ3, θ4‧‧‧ angle

Figure 1 shows a plan view of a trench isolation structure in accordance with some embodiments of the present invention.

Fig. 2 is an enlarged schematic view of a region R in Fig. 1.

3A-3H are cross-sectional views showing various stages of a method of fabricating a trench isolation structure in accordance with some embodiments of the present invention, wherein FIG. 3H is a trench isolation structure along line AA' of FIG. Schematic diagram of the section.

Figure 4 is a cross-sectional view showing the trench isolation structure along line B-B' of Figure 2, in accordance with some embodiments of the present invention.

The trench isolation structure and the method of fabricating the same according to embodiments of the present invention are described below. However, it will be readily understood that the embodiments of the present invention are susceptible to many specific embodiments of the invention and can The specific embodiments disclosed are merely illustrative of the invention, and are not intended to limit the scope of the invention. In the drawings and the description of the embodiments of the present invention, the same reference numerals are used to refer to the same or similar parts.

Referring to Figure 1, there is shown a schematic plan view of a trench isolation structure 100 in accordance with some embodiments of the present invention. In FIG. 1, the trench isolation structure 100 includes a polygonal trench 101 having a high aspect ratio (aspect) A ratio (for example, an aspect ratio greater than 10), and an insulating material 208 may be filled into the polygonal trench 101 to form a deep trench isolation (DTI) structure.

The polygonal groove 101 has a plurality of sides and a plurality of angles enclosed by adjacent sides. In the present embodiment, the polygonal groove 101 is a closed rectangular groove formed by the first side 101a, the second side 101b, the third side 101c, and the fourth side 101d. The first side 101a and the adjacent second side 101b are connected to the apex 102, and the first side 101a and the adjacent second side 101b enclose an angle θ ₁ ; the second side 101b and the adjacent third side 101c are connected to The vertex 103, and the second side 101b and the adjacent third side 101c enclose an angle θ ₂ ; the third side 101c and the adjacent fourth side 101d are connected to the vertex 104, and the third side 101c and the adjacent fourth The side 101d encloses an included angle θ ₃ ; the fourth side 101d and the adjacent first side 101a are connected to the apex 105, and the fourth side 101d and the adjacent first side 101a enclose an angle θ ₄ . In some embodiments, the first side 101a, the second side 101b, the third side 101c, and the fourth side 101d have the same length, and the included angles θ ₁ , θ ₂ , θ _{3 ,} and θ ₄ are all 90 degrees. In some other embodiments, the first side 101a, the second side 101b, the third side 101c, and the fourth side 101d may have different lengths, and the included angles θ ₁ , θ ₂ , θ _{3 ,} and θ ₄ are 60 degrees - 120 degrees. .

The trench isolation structure 100 also includes a polygonal top contact structure 110. The polygonal top contact structure 110 is filled in the polygonal trench 101 and surrounded by the insulating material 208. The polygonal top contact structure 110 has the same shape as the polygonal trench 101 from a top view. That is, the polygonal top contact structure 110 fills the first side 101a, the second side 101b, the third side 101c, and the fourth side 101d of the polygonal groove 101 with the vertices 102, 103, 104, and 105 to form the same A closed rectangle of the shape of the polygonal groove 101. In some embodiments, the material of the polygonal top contact structure 110 may comprise tungsten (W), germanium (Po), or other suitable electrically conductive material.

As shown in FIG. 1, the trench isolation structure 100 further includes a via 212 disposed in the dielectric layer on the polygonal top contact structure 110, and the via 212 is located at the apex 102 (or vertex) of the polygonal top contact structure 110. 103, 104, 105). In some embodiments, the material of the via 212 includes tungsten (W), germanium (Po), or other suitable conductive material. In some embodiments, the material of the via 212 may comprise silver (Ag), copper (Cu), or other suitable conductive material. In some embodiments, the material of the via hole 212 may be the same as the material of the polygonal top contact structure 110.

As shown in FIG. 1, from the top view, the trench isolation structure 100 further includes an extension of the trench protrusion portion 101a' from the apex 102, 105 of the polygonal trench 101 along the first side 101a of the polygonal trench 101. The direction extends outward, and the groove protruding portion 101b' extends outward from the apex 102, 103 of the polygonal groove 101 along the extending direction of the second side 101b of the polygonal groove 101, and the groove protruding portion 101c' is from the apex of the polygonal groove 101 103, 104 extend outward along the extending direction of the third side 101c of the polygonal groove 101, and the groove protruding portion 101d' extends from the apex 104, 105 of the polygonal groove 101 along the fourth side 101d of the polygonal groove 101. Extend outward. In some embodiments, the trench isolation structure 100 also includes top contact protrusions 110a', 110b', 110c', 110d' that fill the trench protrusions 101a', 101b', 101c', and 101d'.

1 shows that a region surrounded by a closed rectangular groove composed of a first side 101a, a second side 101b, a third side 101c, and a fourth side 101d of the polygonal groove 101 may include the semiconductor element region A. The trench isolation structure 100 can fill the semiconductor device region A and the semiconductor device regions B, C by filling the insulating material 208 of the closed polygonal trench 101 and the trench protruding portions 101a', 101b', 101c', 101d'. D and E are electrically isolated. In some embodiments, semiconductor component regions A, B, The elements in C, D, and E can each have different applied bias voltages. In some embodiments, the elements of the semiconductor elements A, B, C, D, and E may comprise a metal oxide semiconductor field effect transistor (MOSFET), a high electron mobility transistor (high electron) A variety of low voltage, high voltage, and very high voltage components such as a mobility transistor (HEMT) and an insulated gate bipolar transistor (IGBT).

In a conventional trench isolation structure, the bias voltage of the semiconductor element in one region and the bias voltage of other semiconductor components in another region separated by the trench may affect each other, resulting in bias coupling. The phenomenon, which in turn affects the operation of the semiconductor components in each region.

Compared with the conventional trench isolation structure, in the embodiment of the present invention, the trench isolation structure 100 further includes a polygonal top contact structure 110, and a voltage of 0 volt is applied through the polygonal top contact structure 110 (ie, the top contact structure 110 is grounded). The phenomenon of bias coupling of the components of the semiconductor device regions A, B, C, D, and E can be avoided, that is, the bias coupling immune effect is achieved, and the semiconductor device is further made higher. Quality of merit (FOM).

It should be understood that the rectangular trenches shown in FIG. 1 are only some embodiments of the present invention and are not intended to limit the present invention. For example, in some other embodiments, the polygonal trench 101 can be triangular, pentagonal, hexagonal, or other suitable polygon, and the polygonal top contact structure 110 also has the same triangle, pentagon, and hexagonal Shape or other suitable polygon.

Please refer to Fig. 2, which shows an enlarged schematic view of a region R in Fig. 1. In some embodiments, the first side 101a and the second side 101b of the polygonal groove 101 have a flat side width W1 with a diagonal width W2 passing through the center of the apex 102 of the first side 101a and the second side 101b. Since the angle θ ₁ surrounded by the first side 101a and the second side 101b in the present embodiment is 90 degrees, the diagonal width W2 should be 1.414 times the width W1 of the flat side as a result of the trigonometric function calculation. Moreover, the groove at the position where the apex 102 of the first side 101a and the second side 101b is located is widened because of the corner rounding effect caused by etching in the process. Therefore, the diagonal width W _{2 is} greater than 1.414 times the width W ₁ of the flat side. In other embodiments, the first side 101a and the second side 101b may have different flat side widths, and different diagonal widths may be obtained according to different flat side widths.

Moreover, in some embodiments, the polygonal top contact structure 110 that fills the polygonal trench 101 has a width W ₄ at the apex 102 (or other vertices 103, 104, 105) and a polygonal top contact structure 110 at the first side 101a (or The widths W _{5 of the} other sides 101b, 101c, and 101d) are different.

Referring to Figures 3A-3H, there are shown cross-sectional schematic views of various stages of fabrication of trench isolation structures 100 in accordance with some embodiments of the present invention. The 3A-3H diagram is drawn along the line A-A' of Fig. 2.

In FIG. 3A, a substrate 201 is provided. The substrate 201 includes a first semiconductor layer 202, an insulating layer 203 formed on the first semiconductor layer 202, and a second semiconductor layer 204 formed on the insulating layer 203. In some embodiments, the first semiconductor layer 202 and the second semiconductor layer 204 may comprise germanium, germanium, antimony, III-V materials (eg, gallium arsenide, indium arsenide), II-VI materials (eg, Zinc selenide, zinc sulfide, or other suitable semiconductor materials, and may be formed by epitaxially grown or other methods. In some embodiments, the insulating layer 203 can be packaged Contains buried oxide (BOX) and can be formed by ion implantation and annealing processes.

In some embodiments, through a lithography process, an etch process (eg, a dry etch process, a wet etch process, a plasma etch process, a reactive ion etch process, or other suitable process), a deposition process (eg, physical vapor deposition) A process, a chemical vapor deposition process or other suitable process) and a planarization process (eg, a chemical mechanical polishing process or other suitable process) form a shallow trench isolation structure 205 in the second semiconductor layer 204, followed by a deposition process ( For example, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process) forms a first dielectric layer 206 on the second semiconductor layer 204 and the shallow trench isolation structure 205, the shallow trench isolation structure 205 abutting the first Dielectric layer 206. Then, through the lithography process, it includes photoresist coating (for example, spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (for example, hard baking), and other suitable A process or combination thereof forms a patterned mask 207 having an opening 207a over the first dielectric layer 206. In the present embodiment, the shallow trench isolation structure 205 directly contacts the first dielectric layer 206. In some embodiments, the shallow trench isolation structure 205 and the first dielectric layer 206 can comprise an oxide, a nitride, a carbide, other suitable dielectric materials, or a combination of the foregoing.

Referring to FIG. 3A-3B, the first dielectric layer 206, the shallow trench isolation structure 205, and the second semiconductor layer 204 are subjected to an etching process by using the patterned mask 207 (for example, a dry etching process, a wet etching process, and a plasma process). An etching process, a reactive ion etching process, or other suitable process) to form a polygonal trench 101 at a position corresponding to the opening 207a in the second semiconductor layer 204, the polygonal trench 101 having a diagonal at the apex of the polygonal trench 101 Width W ₂ . After the polygonal trench 101 is formed, the patterned mask 207 is removed. In some embodiments, the polygonal trench 101 penetrates the first dielectric layer 206, the shallow trench isolation structure 205, and the second semiconductor layer 204, but does not penetrate the underlying first semiconductor layer 202 and the insulating layer 203. In some embodiments, since the etching process may be reactive ion etch (RIE), a polygonal trench 101 having a higher aspect ratio may be formed to facilitate subsequent formation of the deep trench isolation structure.

Referring to FIG. 3C, after forming the polygonal groove 101, the upper surface of the first dielectric layer 206 and the insulating material is conformally deposited on sidewalls 208 and bottom 101 of the polygonal grooves, an insulating material 208 having a thickness W _3. In some embodiments, the material of the insulating material 208 may include an inorganic material (for example, tantalum oxide, tantalum nitride, niobium oxynitride or a combination thereof), an organic material (for example, an epoxy resin, a polyimide resin (polyimide). ), butylcyclobutene (BCB), parylene, polynaphthalenes, fluorocarbons, acrylates, or other suitable insulating materials.

In the present embodiment, the polygonal groove 101 is not completely filled with the insulating material 208, and thus the opening 209' is formed at the center of the polygonal groove 101. The opening 209' will correspond to the location where the top contact structure is formed in a subsequent process.

By controlling the deposition thickness W _{3 of the} insulating material 208, the polygonal trench 101 is not completely filled with the insulating material 208, so that the opening 209' and the subsequent opening are formed in the opening without additional use of the mask. A contact hole at a position of 209' is self-aligned formed at the center of the polygonal groove 101. In order to make the polygonal trench 101 not completely filled with the insulating material 208, to smoothly fill the polygonal trench 101 with the polygonal top contact structure 110 in the subsequent process, the thickness W _{3 of the} insulating material 208 and the width of the polygonal trench 101 the ratio of W ₁ W _3: W ₁ must be maintained within a certain range. In some embodiments, the ratio W ₃ :W ₁ of the thickness W _{3 of the} insulating material 208 to the width W ₁ of the polygonal trench 101 is 2:5. In some embodiments, the insulating material 208 is greater than a thickness of 1 m W _3, and has a compressive strength of greater than 400V.

Referring to FIG. 3D, after depositing the insulating material 208, the first dielectric layer 206 is etched back as an etch stop layer to remove the insulating material 208 located at the bottom of the polygonal trench 101 (ie, the bottom of the opening 209'). And an insulating layer 203 under the bottom of the polygonal trench 101 (see FIG. 3C) to form a contact hole 209 exposing the upper surface of the first semiconductor layer 202 (as shown in FIG. 3D). This etch back process can simultaneously remove the insulating material 208 over the first dielectric layer 206. This etch back process causes the contact hole 209 to extend downward through the insulating layer 203 and expose the upper surface of the first semiconductor layer 202. Next, a doping process (eg, an ion implantation process) is performed to form a doped region 210 under the exposed surface of the first semiconductor layer 202. Next, an annealing process is performed to activate the dopant of the doped region 210. After the annealing process, the resistance value of the doping region 210 is lowered, so that it can be electrically connected to the subsequently formed top contact structure. In the present embodiment, the doping region 210 has the same conductivity type as the first semiconductor layer 202.

Referring to FIG. 3E, a conductive material 110' is formed on the first dielectric layer 206 and the insulating material 208 through a deposition process (eg, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process), and is filled in. The inside of the polygonal groove 101 and the contact hole 209. In some embodiments, the electrically conductive material 110' can comprise tungsten (W), germanium (Po), or other suitable electrically conductive material.

Referring to FIG. 3F, the excess conductive material 110 ′ located outside the polygonal trench 101 is removed by a planarization process (eg, a chemical mechanical polishing process) to form a polygonal top contact structure 110 having a polygonal top contact structure 110 in a polygonal shape. The vertices have a width W ₄ . In some embodiments, referring to Figures 1 and 3F, the polygonal top contact structure 110 has a width W ₄ at the vertices 102, 103, 104, 105 of the polygon and a polygonal groove 101 at the vertices 102, 103, 104, 105. The ratio of the diagonal width W ₂ to W ₂ : W ₂ is 3:7. The polygonal top contact structure 110 penetrates the first dielectric layer 206, the shallow trench isolation structure 205, the second semiconductor layer 204, and the insulating layer 203 and directly contacts the first semiconductor layer 202 (or its doped region 210), and is electrically The doping region 210 is disposed in the first semiconductor layer 202 to facilitate subsequent application of a ground voltage to the first semiconductor layer 202. Since the contact hole 209 is formed in the center of the polygonal groove 101 in a self-aligned manner, the polygonal top contact structure 110 filled in the contact hole 209 can be self-alignedly formed at the center of all sides and vertices of the polygonal groove 101, that is, The polygonal top contact structure 110 is said to be surrounded by an insulating material 208.

Referring to FIG. 3G, a second process is formed on the first dielectric layer 206, the insulating material 208, and the polygonal top contact structure 110 through a deposition process (eg, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process). Dielectric layer 211 (not shown in Figures 1-2). In some embodiments, the second dielectric layer 211 can comprise an oxide, a nitride, an oxynitride, a carbide, other suitable dielectric materials, or a combination of the foregoing.

Referring to FIG. 3H, an etching process (eg, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, or other suitable process) corresponds to a polygonal top contact structure in the second dielectric layer 211. The location of 110 (eg, at the apex of the polygon) forms a hole that penetrates the second dielectric layer 211. Then, a conductive material is filled in the hole through the deposition process, the lithography process, and the etching process to form the via hole 212, and the metal layer 213 is formed on the second dielectric layer 211. The via hole 212 directly contacts and electrically connects the top contact of the polygon. Structure 110, gold The dying layer 213 is electrically connected to the via hole 212, and the via hole 212 and the metal layer 213 are both located at the apex of the polygonal top contact structure 110. As such, the first semiconductor layer 202 can be electrically connected to the external circuit through the polygonal top contact structure 110, the via hole 212, and the metal layer 213. In some embodiments, the material of the via 212 and the metal layer 213 may comprise silver (Ag), copper (Cu), or other suitable conductive material.

Referring to Figure 4, there is shown a cross-sectional view of trench isolation structure 100 taken along line BB' of Figure 2, in accordance with some embodiments of the present invention. Referring to FIGS. 2 and 4, in some embodiments, the polygonal top contact structure 110 has a width W in the first side 101a, the second side 101b, the third side 101c, and the fourth side 101d of the polygonal groove 101. ₅ , the second dielectric layer 211 (not shown in the first 1-2) completely covers all sides of the polygonal top contact structure 110, and has no structure of the via hole 212 and the metal layer 213 above the side of the polygonal top contact structure 110 . As can be seen from FIG. 2, FIG. 3H and FIG. 4, in some embodiments, the via hole 212 and the metal layer 213 are formed only at the apex of the polygonal trench 101. In some embodiments, the width W _{5 of the} polygonal top contact structure 110 at the sides of the polygon and the flat side width W _{1 of the} polygonal groove 101 at the first side 101a, the second side 101b, the third side 101c, and the fourth side 101d. The ratio W ₅ :W ₁ is 1:5.

In the present embodiment, the ratio (T/W ₁ ) of the thickness T of the second semiconductor layer 204 to the flat side width W ₁ of the polygonal trench 101 is also one of the important parameters affecting the formation of the trench isolation structure 100 by the polygonal trench 101. . The higher the ratio (T/W ₁ ) of the thickness T of the second semiconductor layer 204 to the flat side width W ₁ of the polygonal trench 101, the more difficult it is to control the hole filling ability of the insulating material 208. That is, the thickness W ₃ of the insulating material 208 filled in the sidewalls of the polygonal trench 101 may be uneven. If the insulating material 208 of the side wall of the polygonal trench 101 is too thick, the insulating materials 208 located on the opposite side walls may be connected to each other, thereby causing the contact hole 209 to be formed in the polygonal trench 101. If the insulating material 209 on the side wall of the polygonal trench 101 is too thin, the insulating effect is not good, which may cause problems such as leakage current. Further, the higher the ratio (T/W ₁ ) of the thickness T of the second semiconductor layer 204 to the flat side width W ₁ of the polygonal trench 101, the more difficult it is to etch the insulating material 208 and the polygonal groove located at the bottom of the polygonal trench 101. An insulating layer 203 below the bottom of the trench 101. As a result, the first semiconductor layer 202 may not be exposed, and the first semiconductor layer 202 may not be electrically connected to the polygonal top contact structure 110. In some embodiments, the thickness T of the second semiconductor layer 204 is 1 to 8 times the width W ₁ of the flat side of the polygonal trench 101 (ie, T/W ₁ = 1-8). In some embodiments, the thickness T of the second semiconductor layer 204 is three to six times the width W ₁ of the flat side of the polygonal trench 101 (ie, T/W ₁ = 3-6).

A conventional bottom side contact structure is formed by forming a contact hole on the back side of the substrate (i.e., with respect to the front side on which the element is formed on the substrate), and filling the conductive material. In order to make the bottom contact structure, an additional protective or dielectric layer must be formed on the back side of the substrate, and the protective layer or dielectric layer must be patterned using an additional mask to form an electrical contact point at the desired location. . Therefore, the process complexity and manufacturing cost of the bottom contact structure are high.

Furthermore, the conventional top side contact structure is formed by forming a contact hole on the front side of the substrate (i.e., the side on which the element is formed on the substrate) and filling it with a conductive material. In the prior art, in order to form the top contact structure, an additional mask is still required to define the location of the contact holes. In addition, the top contact structure formed in the element region will occupy an effective area available for use of the element, which is disadvantageous for miniaturization of the semiconductor element.

The invention provides a trench isolation structure with a top contact structure The manufacturing method integrates the process of the top contact structure with the process of the deep trench isolation structure. Compared with the conventional bottom contact structure or the top contact structure process, the use of the photomask can be reduced, thereby greatly reducing the process complexity and manufacturing cost. Furthermore, the top contact structure provided by the present invention is formed in the deep trench isolation structure without occupying an effective area available for use of the device, thereby contributing to the miniaturization of the semiconductor device.

According to some embodiments of the present invention, since the trench isolation structure includes a polygonal top contact structure, by grounding the polygonal top contact structure, the bias coupling of adjacent semiconductor elements can be avoided, that is, the bias coupling immunity is achieved, and further The semiconductor element has a high quality factor.

In addition, by controlling the deposition thickness of the insulating material (ie, the ratio of the thickness of the insulating material to the width of the polygonal trench must be maintained within a certain range), the polygonal trench of the trench isolation structure is not completely filled with the insulating material. In this way, the contact hole can be self-aligned in the center of the polygonal groove without using the mask, so that the polygonal top contact structure filled in the contact hole can be self-aligned in the polygonal groove. The center of all sides and vertices of the slot.

Furthermore, by maintaining the ratio of the thickness of the second semiconductor layer in the substrate to the width of the flat side of the polygonal trench within a certain range, thickness unevenness of the insulating material filled in the polygonal trench can be avoided, and the thickness can be effectively reduced. The subsequent difficulty in forming the polygonal top contact structure.

The trench isolation structure and the manufacturing method thereof of the embodiment of the invention can be applied to a metal oxide semiconductor field effect transistor (MOSFET), a high electron mobility transistor (HEMT), Insulated gate bipolar transistor (insulated gate bipolar transistor, IGBT) and other low voltage, high voltage and very high voltage components.

While the invention has been described above in terms of the preferred embodiments thereof, which are not intended to limit the invention, the invention may be modified and combined with the various embodiments described above without departing from the spirit and scope of the invention. example.

100‧‧‧ trench isolation structure

101‧‧‧ polygonal groove

101a‧‧‧ first side

101b‧‧‧ second side

101c‧‧‧ third side

101d‧‧‧ fourth side

101a', 101b', 101c', 101d'‧‧‧ grooved projections

102, 103, 104, 105‧‧ ‧ vertices

110‧‧‧Polygonal top contact structure

110a', 110b', 110c', 110d'‧‧‧ top contact protrusion

208‧‧‧Insulation materials

212‧‧‧through hole

A, B, C, D, E‧‧‧ semiconductor component area

R‧‧‧ area

Θ1, θ2, θ3, θ4‧‧‧ angle

Claims (20)

A trench isolation structure comprising: a substrate; a polygonal trench disposed in the substrate; an insulating material disposed in the polygonal trench; and a polygonal top contact structure disposed in the polygonal trench The insulating material surrounds the polygonal top contact structure having a shape identical to the polygonal groove from a top view, and the polygonal top contact structure surrounds a portion of the substrate. The trench isolation structure of claim 1, wherein the substrate comprises: a first semiconductor layer; an insulating layer disposed on the first semiconductor layer; and a second semiconductor layer disposed on the insulating layer On the floor. The trench isolation structure of claim 2, wherein the polygonal trench penetrates the second semiconductor layer but does not penetrate the first semiconductor layer and the insulating layer. The trench isolation structure of claim 2, wherein the second semiconductor layer has a thickness of three to six times the width of the polygonal trench. The trench isolation structure of claim 2, wherein the polygonal top contact structure penetrates the second semiconductor layer and the insulating layer and directly contacts a doped region of the first semiconductor layer. The trench isolation structure of claim 2, further comprising: a shallow trench isolation structure disposed in the second semiconductor layer; a first dielectric layer disposed on the second semiconductor layer, wherein the polygonal trench penetrates the first dielectric layer and the shallow trench isolation structure, and the shallow trench isolation structure abuts the first dielectric a layer; and a second dielectric layer disposed on the first dielectric layer. The trench isolation structure of claim 6, wherein the two dielectric layers completely cover each side of the polygon of the polygonal top contact structure. The trench isolation structure of claim 6, further comprising: a via hole formed in the second dielectric layer and electrically connected to the polygonal top contact structure; and a metal layer disposed on the The second dielectric layer is electrically connected to the via hole. The trench isolation structure of claim 8, wherein the via is located at an apex of a polygon of the top contact structure of the polygon. The trench isolation structure of claim 1, wherein the material of the polygonal top contact structure comprises tungsten (W) or germanium (Po). The trench isolation structure of claim 1, wherein the polygonal top contact structure has a width at a vertex of the polygon that is greater than a width of a side of the polygon. The trench isolation structure of claim 1, wherein the insulating material has a thickness greater than 1 μm and a compressive strength greater than 400V. The trench isolation structure of claim 1, wherein the upper viewing angle further comprises a groove protruding portion extending from a polygonal vertex of the polygonal groove along a polygonal side of the polygonal groove. Extend outward. A method of manufacturing a trench isolation structure, comprising: providing a substrate; Forming a polygonal trench in the substrate; forming an insulating material in the polygonal trench; and forming a polygonal top contact structure in the polygonal trench and surrounded by the insulating material, wherein the upper viewing angle The polygonal top contact structure has the same shape as the polygonal groove, and the polygonal top contact structure surrounds a portion of the substrate. The method of fabricating a trench isolation structure according to claim 14, wherein the substrate comprises: a first semiconductor layer; an insulating layer formed on the first semiconductor layer; and a second semiconductor layer formed On the insulating layer. The method for fabricating a trench isolation structure according to claim 15, wherein the forming the polygonal trench comprises: forming a patterned mask having an opening over the second semiconductor layer; and utilizing the pattern The masking layer performs an etching process on the second semiconductor layer to form the polygonal trench at a position corresponding to the opening of the second semiconductor layer, wherein the polygonal trench penetrates the second semiconductor layer. The method of fabricating a trench isolation structure according to claim 15, wherein the insulating material is conformally formed on a bottom portion and a sidewall of the polygonal trench. The method for fabricating a trench isolation structure according to claim 17, wherein the step of forming the polygonal top contact structure comprises: performing an etch back process to remove the bottom portion of the polygonal trench; The insulating material and the insulating layer under the bottom portion form a contact hole to expose the first semiconductor layer; and a conductive material is filled in the polygonal trench and the contact hole to form the polygonal top contact structure. The method for fabricating a trench isolation structure according to claim 15, further comprising: forming a shallow trench isolation structure in the second semiconductor layer; forming a first dielectric layer on the second semiconductor layer The polygonal trench penetrates the first dielectric layer and the shallow trench isolation structure, and the shallow trench isolation structure abuts the first dielectric layer; and a second is formed on the first dielectric layer Dielectric layer. The method for fabricating a trench isolation structure according to claim 19, further comprising: forming a via hole electrically connected to the polygonal top contact structure in the second dielectric layer; and the second dielectric layer A metal layer is formed on the layer to be electrically connected to the via hole.