WO2024131650A1 - Semiconductor device and manufacturing method therefor, memory, and electronic device - Google Patents

Abstract

The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a semiconductor device and a manufacturing method therefor, a memory, and an electronic device, for use in at least effectively solving the problem of electric leakage between a gate structure and a source structure of a VGAA transistor. The method comprises: providing a target substrate (100'), wherein a plurality of active pillars (20) arranged at intervals by initial first isolation structures (10') in a first direction are formed in the target substrate (100'), an initial second isolation structure (30') is formed on the two opposite sides of every two adjacent active pillars (20) in a second direction, and each initial second isolation structure (30') comprises an insulating pillar (32) and an initial liner layer (31) covering the outer side surface and the bottom surface of the insulating pillar (32); forming a protective layer (40) on the exposed side walls of the active pillars (20); removing the initial liner layers (31) and the tops of the initial first isolation structures (10') to obtain target gaps exposing the tops of the insulating pillars (32); and forming gate structures (50) in the target gaps.

Description

Semiconductor device and manufacturing method thereof, memory and electronic device

CROSS-REFERENCE TO RELATED APPLICATIONS

This disclosure claims the priority of a Chinese patent application filed with the China Patent Office on December 23, 2022, with application number 202211665514.X and invention name “Semiconductor device and method for manufacturing the same, memory and electronic device”. The entire contents of the patent application are incorporated by reference in this disclosure.

Technical Field

The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a semiconductor device and a manufacturing method thereof, a memory and an electronic device.

Background technique

With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products.

Summary of the invention

According to various embodiments of the present disclosure, a semiconductor device and a method for manufacturing the same, a memory, and an electronic device are provided.

According to some embodiments, one aspect of the present disclosure provides a method for preparing a semiconductor device, including: providing a target substrate having a bottom surface, forming a plurality of active pillars arranged in an array on the bottom surface of the target substrate, the plurality of active pillars are arranged along a first direction to form an active pillar row, the plurality of active pillars are arranged along a second direction to form an active pillar column, an initial first isolation structure is provided between adjacent active pillars in the active pillar row, and an initial second isolation structure is provided between adjacent active pillars in the active pillar column; the top surface of the initial first isolation structure and the top surface of the initial second isolation structure are both lower than the top surface of the active pillar, so as to obtain an exposed side wall of the active pillar; the first direction intersects with the second direction and is both parallel to the bottom surface of the target substrate; forming a protective layer on the exposed side wall of the active pillar; removing a portion of the top of the initial second isolation structure and the top of the initial first isolation structure to obtain a target gap between the active pillar and the top of the initial second isolation structure; and forming a gate structure in the target gap.

According to some embodiments, the initial second isolation structure includes an insulating column and an initial liner layer covering the outer side and bottom surface of the insulating column; removing a portion of the top of the initial second isolation structure includes: removing the top of the initial liner layer to expose the top of the insulating column.

According to some embodiments, providing a target substrate having a bottom surface includes: providing an initial substrate, on the bottom surface of which a plurality of active walls arranged along a first direction are formed, a first trench isolation structure is provided between adjacent active walls, and the active walls extend along a second direction; forming a plurality of second trenches extending along the first direction and spaced apart along the second direction on the bottom surface of the initial substrate, the bottom surface of the second trenches being higher than the bottom surface of the first trench isolation structure; forming a liner material layer on the bottom surface of the second trenches and on the side walls opposite to each other along the second direction; forming an insulating material layer in the second trench whose top surface is flush with the top surface of the active column, the liner material layer and the insulating material layer constituting a second trench isolation structure; and etching back the first trench isolation structure and the second trench isolation structure to obtain an initial first isolation structure and an initial second isolation structure whose top surfaces are both lower than the top surface of the active column, so as to provide a target substrate.

According to some embodiments, etching back the first trench isolation structure and the second trench isolation structure includes: obtaining an initial first isolation structure and an initial second isolation structure whose top surfaces are lower than the top surface of the active pillar by controlling the etching rate and time of the first trench isolation structure and the second trench isolation structure.

According to some embodiments, a protective layer is formed on the exposed sidewalls of the active pillar, including: using an atomic layer deposition process to form a protective material layer on the exposed surface of the active pillar, the top surface of an initial first isolation structure, and the top surface of an initial second isolation structure; removing the protective material layer located on the top surface of the active pillar, the top surface of the initial first isolation structure, and the top surface of the initial second isolation structure, and retaining the protective material layer located on the sidewalls of the active pillar to form a protective layer.

According to some embodiments, removing the initial liner layer and the top of the initial first isolation structure includes: removing the initial liner layer and the top of the initial first isolation structure by a wet etching process, the remaining initial liner layer constituting a target liner layer, and the remaining The remaining initial first isolation structure constitutes a target first isolation structure, and the target liner layer and the insulating column constitute a target second isolation structure.

According to some embodiments, a gate structure is formed in a target gap, including: forming a gate dielectric layer on the exposed sidewalls of the active pillar in the target gap, the thickness of the gate dielectric layer being less than the thickness of the target liner layer; forming a work function material layer, the work function material layer filling the gap between the target second isolation structure and the adjacent active pillar, covering the exposed surface of the gate dielectric layer and the top surface of the target first isolation structure; forming a conductive material layer, the top surface of the conductive material layer located on the side of the target second isolation structure along a third direction is higher than the top surface of the active pillar; the third direction is a direction perpendicular to the bottom surface of the target substrate; etching back the work function material layer and the conductive material layer, the remaining work function material layer having a top surface flush with the top surface of the gate dielectric layer constitutes a work function layer, the remaining conductive material layer having a top surface flush with the top surface of the gate dielectric layer constitutes a gate conductive layer, and the gate dielectric layer, the work function layer and the gate conductive layer constitute a gate structure.

According to some embodiments, the protection layer is removed during the process of etching back the work function material layer and the conductive material layer, or the protection layer is removed after the gate structure is obtained.

According to some embodiments, after obtaining the gate structure and removing the protection layer, the method further includes: forming a capping layer whose top surface is flush with the top surface of the active pillar; and the capping layer fills the gaps between the active pillars adjacent to each other along the first direction and the second direction.

According to some embodiments, forming a capping layer whose top surface is flush with the top surface of the active pillar includes: forming a spacer material layer whose top surface is higher than the top surface of the active pillar; filling the gaps between the active pillars adjacent to each other along the first direction and the second direction with the spacer material layer; and planarizing the spacer material layer to obtain the capping layer.

According to some embodiments, planarizing the spacer material layer includes: processing the spacer material layer using at least one of a chemical mechanical polishing process, a dry etching process, and a push-flat process.

According to some embodiments, after forming a liner material layer on the bottom surface of the second trench and the sidewalls opposite to it along the second direction, and before forming an insulating material layer, it also includes: injecting ions into the initial substrate on one side of the second trench along the third direction through the bottom of the second trench, and performing an annealing process, so that the conductive regions formed in the initial substrate on one side of the adjacent second trenches along the third direction are electrically connected, and a bit line structure extending along the second direction is formed; the bottom surface of the initial first isolation structure is lower than the bottom surface of any conductive region; the third direction is a direction perpendicular to the bottom surface of the target substrate.

According to some embodiments, the second aspect of the present disclosure provides a semiconductor device, which includes a target substrate and a gate structure, wherein a plurality of active pillars arranged in an array are provided on the bottom surface of the target substrate, wherein the plurality of active pillars are arranged along a first direction to form an active pillar row, and the plurality of active pillars are arranged along a second direction to form an active pillar column, wherein a target first isolation structure is provided between adjacent active pillars in the active pillar row, and a target second isolation structure is provided between adjacent active pillars in the active pillar column; the top surfaces of the target second isolation structure and the target first isolation structure are lower than the top surfaces of the active pillars; the first direction intersects with the second direction and are both parallel to the bottom surface of the target substrate; and the gate structure surrounds the active pillars.

According to some embodiments, the target second isolation structure includes an insulating column and a target liner layer covering a side surface of the insulating column.

According to some embodiments, a top surface of the target liner layer and a top surface of the target first isolation structure are both lower than a top surface of the insulating pillar, and a top surface of the insulating pillar is lower than a top surface of the active pillar.

According to some embodiments, the top surface of the gate structure is not higher than the top surface of the insulating pillar; the gate structures on the active pillars adjacent to each other along the first direction are in contact with each other, and the gate structures on the active pillars adjacent to each other along the second direction are isolated by the insulating pillar.

According to some embodiments, the gate structure includes a gate dielectric layer, a work function layer and a gate conductive layer, the gate dielectric layer covers the side wall of the active pillar, the thickness of the gate dielectric layer is less than the thickness of the target pad layer; the top surface of the gate dielectric layer is not higher than the top surface of the insulating pillar; the work function layer covers the side of the gate dielectric layer and is located between the gate dielectric layer and the insulating pillar, the top surface of the work function layer is not higher than the top surface of the gate dielectric layer; the gate conductive layer is located on the side of the work function layer away from the gate dielectric layer, and the top surface of the gate conductive layer is not higher than the top surface of the gate dielectric layer.

According to some embodiments, the semiconductor device also includes a bit line structure, which extends along a second direction and is located in a target substrate on one side along a third direction of a target second isolation structure adjacent to the second direction, and the bottom surface of the target first isolation structure is lower than the bottom surface of the bit line structure; the third direction is a direction perpendicular to the bottom surface of the target substrate.

According to some embodiments, the semiconductor device further includes: a capping layer, the top surface of the capping layer being flush with the top surface of the active pillar and being located on a side of the gate structure facing away from the bottom surface of the target substrate.

According to some embodiments, the material of the active pillar is selected from single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, silicon germanium and combinations thereof; the material of the target liner layer includes silicon oxide; the material of the insulating pillar is selected from silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide and combinations thereof.

According to some embodiments, a third aspect of the present disclosure provides a memory including the above-mentioned semiconductor device.

According to some embodiments, a fourth aspect of the present disclosure provides an electronic device, comprising the above-mentioned memory.

The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without creative work.

FIG1 is a schematic top view of a storage structure provided in some embodiments of the present disclosure;

FIG2-FIG3 are schematic cross-sectional structures of intermediate products obtained in different steps in some embodiments of the present disclosure along the aa' direction shown in FIG1 and perpendicular to the bottom surface of the target substrate;

FIG4 is a schematic flow chart of a method for preparing a semiconductor device provided in some other embodiments of the present disclosure;

FIG5a, FIG6a, and FIG7a are schematic diagrams of the three-dimensional structures of intermediate products obtained in different steps in some other embodiments of the present disclosure;

FIG5b is a schematic diagram of a cross-sectional structure perpendicular to the bottom surface of the target substrate obtained along the aa’ direction, bb’ direction, cc’ direction and dd’ direction shown in FIG5a;

FIG6b is a schematic diagram of a cross-sectional structure perpendicular to the bottom surface of the target substrate obtained along the aa’ direction, bb’ direction, cc’ direction and dd’ direction shown in FIG6a;

FIG7b is a schematic diagram of a cross-sectional structure perpendicular to the bottom surface of the target substrate obtained along the aa' direction, bb' direction, cc' direction and dd' direction shown in FIG7a;

Figures 8 to 16 are schematic diagrams of the cross-sectional structures of intermediate products obtained in different steps of the method for preparing a semiconductor device in some other embodiments of the present disclosure, which are perpendicular to the bottom surface of the target substrate along the aa’ direction, bb’ direction, cc’ direction and dd’ direction shown in Figure 1.

Detailed ways

In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used in the specification of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or parts, these elements, components, regions, layers, doping types and/or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be P-type. It may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like, may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

When used herein, the singular forms "a", "an" and "/the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and/or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and/or components may be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups is not excluded. At the same time, when used herein, the term "and/or" includes any and all combinations of the relevant listed items.

Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and/or tolerances are anticipated. Accordingly, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

Please refer to Figures 1 to 16. It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present disclosure. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

Please note that the mutual insulation between the two described in the embodiments of the present disclosure includes but is not limited to at least one of the presence of insulating material, insulating atmosphere or gap between the two.

Please refer to Figures 1 to 3. The dynamic random access memory (DRAM) includes an array area 400 composed of a plurality of storage cells and a peripheral area 500 located outside the array area 400. The transistors in the peripheral area 500 are integrated with the array area 400 by etching through holes and forming a metal silicide layer. Specifically, each storage cell includes a capacitor and a transistor. The gate of the transistor is connected to the word line structure 200, the drain of the transistor is connected to the bit line structure 300, and the source of the transistor is connected to the capacitor structure (not shown). The opening and closing of the transistor is controlled by the voltage signal on the word line structure 200, and then the data information stored in the capacitor structure is read through the bit line structure 300, or the data information is written into the capacitor structure through the bit line structure 300 for storage.

Please continue to refer to FIG. 2-FIG. 3. In some embodiments, before making the gate dielectric layer 51 of the word line structure, the insulating structure 53 between the word line structures is set to be flush with the top surface of the active pillar 20 of the VGAA transistor, and then the insulating material is grown on the sidewall and bottom of the gap 54 at the same time, and the insulating material is used to protect the source structure (not shown) to prevent the source structure from being damaged during the subsequent preparation of the gate dielectric layer 51. However, it is easy to generate fine cracks or voids inside the insulating material layer grown inside the gap 54, resulting in the growth of conductive materials in the fine cracks or voids during the subsequent preparation of the gate conductive layer 52, forming a gate-source leakage path 70, and establishing a current channel from the gate structure 50 to the source structure, resulting in leakage.

The present disclosure aims to provide a semiconductor device and a method for manufacturing the same, a memory and an electronic device, which can at least effectively avoid the leakage problem between the gate structure and the source structure of a VGAA transistor and improve the performance and reliability of the VGAA transistor.

Referring to FIG. 4 , in one embodiment of the present disclosure, a method for preparing a semiconductor device is provided, comprising the following steps:

Step S20: providing a target substrate having a bottom surface, forming a plurality of active pillars arranged in an array on the bottom surface of the target substrate, wherein the plurality of active pillars are arranged along a first direction to form an active pillar row, and the plurality of active pillars are arranged along a second direction to form an active pillar column, an initial first isolation structure is provided between adjacent active pillars in the active pillar row, and an initial second isolation structure is provided between adjacent active pillars in the active pillar column; the top surface of the initial first isolation structure and the top surface of the initial second isolation structure are both lower than the top surface of the active pillar, so as to obtain an exposed side wall of the active pillar; the first direction intersects with the second direction and is parallel to the bottom surface of the target substrate;

Step S40: forming a protection layer on the exposed sidewalls of the active pillars;

Step S60: removing a portion of the top of the initial second isolation structure and the top of the initial first isolation structure to obtain a target gap between the active pillar and the top of the initial second isolation structure;

Step S80: forming a gate structure in the target gap.

As an example, please continue to refer to Figure 4. Since a plurality of active pillars are formed in the target substrate and are arranged at intervals by the initial first isolation structure along the first direction, it is convenient to subsequently prepare a word line structure extending along the first direction through the active pillars; initial second isolation structures are formed on opposite sides of the active pillars along the second direction, so that the initial second isolation structure is subsequently used to insulate adjacent word line structures along the second direction from each other; since a protective layer is formed on the exposed side walls of the active pillars before the gate dielectric layer of the gate structure is prepared, there is no air gap in the dense protective layer, thereby avoiding damage to the surface of the active pillar covered by the protective layer during the subsequent formation of the gate dielectric layer on the surface of the active pillar exposed in the target gap; and avoiding the formation of conductive material in the air gap during the formation of the gate conductive layer, thereby avoiding the conductive material in the air gap inducing leakage current between the gate structure and the source structure during the operation of the VGAA transistor, which can effectively avoid the leakage problem between the gate structure and the source structure of the VGAA transistor, and improve the performance and reliability of the prepared semiconductor device.

As an example, referring to step S20 in FIG. 4 and FIGS. 5 a to 9 , providing a target substrate in step S20 may include the following steps:

Step S20: providing an initial substrate 100, on the bottom surface of which a plurality of active walls 21 arranged along a first direction (eg, ox direction) are formed, a first trench isolation structure 11 is provided between adjacent active walls 21, and the active walls 21 extend along a second direction (eg, oy direction);

Step S22: forming a plurality of second trenches 12 extending along a first direction (eg, ox direction) and arranged at intervals along a second direction (eg, oy direction) on the bottom surface of the initial substrate 100, wherein the bottom surface of the second trenches 12 is higher than the bottom surface of the first trench isolation structure 11;

Step S24: forming a liner material layer 311 on the bottom surface of the second trench 12 and the sidewalls opposite to the second direction (eg, oy direction);

Step S26: forming an insulating material layer 321 in the second trench 12 , the top surface of which is flush with the top surface of the active pillar 20 , and the liner material layer 311 and the insulating material layer 321 constitute a second trench isolation structure 13 ;

Step S28: The first trench isolation structure 11 and the second trench isolation structure 13 are etched back to obtain an initial first isolation structure 10' and an initial second isolation structure 30' whose top surfaces are lower than the top surface of the active pillar 20, so as to provide a target substrate 100'.

As an example, please continue to refer to Figures 5a-5b. The initial substrate 100 provided in step S20 can be composed of any combination of semiconductor materials, insulating materials, conductor materials or their material types. The initial substrate 100 can be a single-layer structure or a multi-layer structure. For example, the initial substrate 100 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III/V semiconductor substrates or II/VI semiconductor substrates. Or, for example, the initial substrate 100 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on insulator, etc. An ion implantation process may be used to implant P-type ions into the initial substrate 100 to form a first type doped well region (not shown). The P-type ions may include but are not limited to at least one of boron (B) ions, gallium (Ga) ions, boron fluoride ions, and indium (In) ions.

As an example, please continue to refer to FIG. 5a-FIG. 5b. In the embodiment where the initial substrate 100 includes a P-type substrate, the active wall 21 may be formed by implanting N-type ions in step S20; correspondingly, in the embodiment where the silicon substrate includes an N-type substrate, the active wall 21 may be formed by implanting P-type ions. Accordingly, the active wall 21 may be a P-type active The wall 21 may be an N-type active wall 21. The P-type active wall 21 may form an N-type metal oxide semiconductor (Negative channel Metal Oxide Semiconductor, referred to as NMOS) device, and the N-type active wall 21 may form a P-type metal oxide semiconductor (Positive channel Metal Oxide Semiconductor, referred to as PMOS) device. The N-type impurity ions may include but are not limited to at least one of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions. The n-type or p-type impurity concentration may be less than or equal to 10 ¹⁸ cm ^-3 , such as in the range between about 10 ¹⁷ cm ^-3 and about 10 ¹⁸ cm ^-3 .

As an example, please continue to refer to Figures 5a-5b. In step S20, an etching process can be used to form a first groove 111 arranged in a first direction (e.g., ox direction) and extending in a second direction (e.g., oy direction) in the initial substrate 100, so as to obtain a plurality of active walls 21 arranged in a first direction (e.g., ox direction), and the active wall 21 extends in the second direction (e.g., oy direction). The depth and width of the first groove 111 are adjusted according to the technical indicator requirements and are not specifically limited. The etching process may include but is not limited to a dry etching process and/or a wet etching process, and the dry etching process may include but is not limited to any one of a reactive ion etching process (RIE), an inductively coupled plasma etching process (ICP), or a high concentration plasma etching process (HDP). The material of the active wall 21 is selected from single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, germanium silicon, etc. and combinations thereof.

As an example, please refer to FIG. 6a-FIG. 6b. After the first trench 111 is obtained in step S20, a deposition process can be used to fill the first trench 111 with an isolation material to form a plurality of active walls 21 spaced apart along a first direction (e.g., ox direction) in the initial substrate 100. The active walls 21 extend along a second direction (e.g., oy direction). After the isolation material is deposited and filled with the isolation material in the first trench 111, a planarization process can be used to remove the isolation material on the top surface of the active wall 21 to obtain a first trench isolation structure 11 whose top surface is flush with the top surface of the active wall 21. The deposition process may include but is not limited to at least one of a chemical vapor deposition process (CVD), a physical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition (HDP), a plasma enhanced deposition process, and a spin-on dielectric layer (SOD). The planarization process may include but is not limited to at least one of a chemical mechanical polishing process, a dry etching process, and a flat push process.

As an example, please refer to FIG. 7a-7b. In step S22, a plurality of second trenches 12 extending along a first direction (e.g., ox direction) and arranged at intervals along a second direction (e.g., oy direction) may be formed on the initial substrate 100 by dry etching process. The bottom surface of the second trench 12 is higher than the bottom surface of the first trench isolation structure 11, and a plurality of active pillars 20 arranged in an array at intervals along the ox direction and the oy direction are obtained. Since it is necessary to prepare a bit line structure extending along the oy direction in the initial substrate 100 on one side of the second trench 12 adjacent to the second direction (e.g., oy direction) along the third direction (e.g., oz direction) (not shown in FIG. 7a-7b), the bit line structures adjacent to the ox direction are insulated from each other via the first trench isolation structure 11, and the word line structures adjacent to each other along the oy direction (not shown in FIG. 7a-7b) prepared subsequently are insulated from each other via the isolation material in the second trench 12. The third direction is a direction perpendicular to the bottom surface of the target substrate 100', and the first direction, the second direction, and the third direction may be set to be perpendicular to each other. The depth of the second trench 12 is less than the depth of the first trench 111. If the second trench 12 is too deep, there will be insufficient space for the subsequent preparation of the bit line structure; if the second trench 12 is too shallow, the height of the active pillar 20 will be relatively reduced, resulting in insufficient space for the subsequent preparation of the word line structure and the VGAA transistor. The material of the active pillar 20 is selected from single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, germanium silicon and a combination thereof. The dry etching process may include but is not limited to one or more of reactive ion etching (RIE), inductively coupled plasma etching (ICP) and high concentration plasma etching (HDP).

As an example, please refer to FIG8. In step S24, at least one of an in-situ steam generation process (ISSG), an atomic layer deposition process, a plasma vapor deposition process, and a rapid thermal oxidation process (RTO) can be used to form a liner material layer 311 on the bottom surface of the second trench 12 and the sidewalls opposite along the second direction (e.g., the oy direction). In step S26, a deposition process can be used to form an insulating material layer 321 whose top surface is flush with the top surface of the active pillar 20 in the second trench 12, and the liner material layer 311 and the insulating material layer 321 constitute the second trench isolation structure 13. The material of the liner material layer 311 may include silicon oxide. The material of the insulating material layer 321 may be selected from silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, and the like, and combinations thereof. The deposition process may include, but is not limited to, at least one of CVD, PVD, ALD, HDP, and SOD.

As an example, please continue to refer to FIG. 8 , after forming the liner material layer 311 on the bottom surface of the second trench 12 and the sidewalls opposite to the second direction (eg, the oy direction), and before forming the insulating material layer 321, the following steps are further included:

Step S25: Ions are injected into the initial substrate 100 on one side along the third direction through the bottom of the second trench 12, and an annealing process is performed, so that the conductive regions formed in the initial substrate 100 on one side of the adjacent second trench 12 along the third direction are electrically connected, and a bit line structure 300 extending along the second direction is formed; the bottom surface of the initial first isolation structure 10' is lower than the bottom surface of any conductive region; the third direction is a direction perpendicular to the bottom surface of the target substrate 100' (for example, the oz direction).

As an example, please continue to refer to FIG. 8. In step S24, the formation of a liner material layer 311 on the bottom surface of the second trench 12 and the sidewalls opposite along the second direction (e.g., the oy direction) can protect the active pillar 20 and prevent the active pillar 20 from being damaged or contaminated by doped ions in the subsequent process. In step S25, doped ions with a high dopant concentration between about 10 ¹⁸ cm ^-3 and 10 ¹⁹ cm ^-3 are implanted into the initial substrate 100 below the second trench 12 along the third direction (e.g., the oz direction) through an ion implantation process; the doped ions can be P-type ions, such as B ions, through an ion implantation process. Of course, in other embodiments, for example, N-type ions are used, and N-type ions have a higher current. Specifically, for example, As and P ions can be used. After performing at least one, for example, one low-energy high-dose ion implantation, an annealing process can be performed to diffuse the doped ions in the initial substrate 100 to form a bit line structure 300 extending along the second direction. During the annealing process, impurities accumulate at the interface between silicide and silicon due to segregation, thereby reducing the Schottky contact resistance and improving the performance of semiconductor devices. By forming a continuous metal silicide in the substrate as a buried bit line structure, the resistance of the semiconductor device is reduced, the performance of the semiconductor device is improved, and a VGAA transistor is formed, thereby effectively reducing the size of the memory and improving the integration and performance of the memory.

As an example, please continue to refer to FIG8 , during the doping process, the liner material layer 311 can effectively protect the sidewall of the active pillar 20 from being mixed with doping ions; during the annealing process, the liner material layer 311 can effectively protect the active pillar 20 and prevent it from deforming, thereby improving the structural stability of the active pillar 20. The annealing process can be a wet annealing process or a dry annealing process, and the annealing process temperature can be 800° C.-1500° C., for example, the annealing temperature can be 800° C., 900° C., 1000° C., 1100° C., 1200° C., 1300° C., 1400° C. or 1500° C.; the annealing gas can include at least one of H ₂ , O ₂ , N ₂ , Ar and He, and the annealing time can be 1.5 hours to 2.5 hours, for example, the annealing time can be 1.5 hours, 2.0 hours or 2.5 hours, etc. When the annealing gas includes _H2 and _O2 , the annealing process is a wet annealing process. The annealing process can remove some defects caused by ion implantation and activate dopants. The material of the bit line structure 300 can include titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide, tungsten nitride, etc. or a combination thereof to meet the actual needs of various different application scenarios and reduce the cost and complexity of preparation.

As an example, please refer to FIG9. In step S28, a dry etching process and/or a wet etching process may be used to etch back the first trench isolation structure 11 and the second trench isolation structure 13 to obtain an initial first isolation structure 10' and an initial second isolation structure 30' whose top surfaces are lower than the top surface of the active pillar 20, so as to obtain a target substrate 100'. The top surfaces of the initial first isolation structure 10' and the initial second isolation structure 30' may be set flush. In step S28, the rate and time of dry etching the first trench isolation structure 11 and the second trench isolation structure 13 may be controlled to obtain an initial first isolation structure 10' and an initial second isolation structure 30' whose top surfaces are lower than the top surface of the active pillar 20; wherein the bottom surface of the initial second isolation structure 30' is higher than the bottom surface of the initial first isolation structure 10'. The dry etching process may include, but is not limited to, at least one of RIE, ICP, and HDP.

As an example, referring to step S40 in FIG. 4 and FIG. 10 , forming the protection layer 40 on the exposed sidewall of the active pillar 20 in step S40 may include the following steps:

Step S42, forming a protective material layer 41 on the exposed surface of the active pillar 20, the top surface of the initial first isolation structure 10' and the top surface of the initial second isolation structure 30' by using an atomic layer deposition process;

Step S44, remove the protective material layer 41 located on the top surface of the active pillar 20, the top surface of the initial first isolation structure 10' and the top surface of the initial second isolation structure 30', and retain the protective material layer 41 located on the side wall of the active pillar 20 to form a protective layer 40.

As an example, please continue to refer to FIG. 10 , in step S42, an atomic layer deposition process is used to form a protective material layer 41 on the exposed surface of the active pillar 20, the top surface of the initial first isolation structure 10 ′ and the top surface of the initial second isolation structure 30 ′. The sub-layer deposition process is a technology that forms a deposited film by alternately passing a gaseous precursor pulse into a reactor and chemically adsorbing and reacting on a deposition substrate. When the precursor reaches the surface of the deposition substrate, it will chemically adsorb on its surface and react on the surface. The surface reaction of atomic layer deposition is self-limiting. The desired structure is formed by continuously repeating the self-limiting reaction in atomic layer deposition. The precursor material may include a non-metallic precursor material and/or a metallic precursor material. Atomic layer deposition technology is based on surface self-limitation and self-saturated adsorption reactions, so it has surface controllability. The prepared structure has excellent three-dimensional conformality and large-area uniformity, and is more adaptable to complex high-aspect-ratio surface deposition processes. At the same time, the atomic layer deposition process can produce a smooth surface morphology that fits the filling layer tightly, thereby reducing the stress generated by the deposition process. In step S42 , according to the characteristics of the atomic layer deposition process itself, the atomic layer deposition process is used to form the protective material layer 41 , so that the protective material layer 41 evenly covers the exposed sidewalls of the active pillar 20 and avoids defects such as fine cracks and voids formed inside the protective material layer 41 .

As an example, referring to FIG. 11 , in step S44, a dry etching process may be used to remove the protective material layer 41 located on the top surface of the active pillar 20, the top surface of the initial first isolation structure 10′, and the top surface of the initial second isolation structure 30′, and the protective material layer 41 retained on the exposed sidewall of the active pillar 20 constitutes a protective layer 40. The material of the protective layer 40 may be selected from silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, etc., and combinations thereof.

As an example, referring to step S60 in FIG. 4 and FIG. 12 , the removal of the initial liner layer 31 and the top of the initial first isolation structure 10′ in step S60 may include the following steps:

Step S61, using a wet etching process to remove the initial pad layer 31 and the top of the initial first isolation structure 10’, the remaining initial pad layer 31 constitutes the target pad layer 31’, the remaining initial first isolation structure 10’ constitutes the target first isolation structure 10, and the target pad layer 31’ and the insulating column 32 constitute the target second isolation structure 30.

As an example, the wet etching chemistry may include a chemical solution including ammonia (NH ₃ ), hydrogen peroxide (H ₂ O ₂ ), and water.

As an example, referring to step S80 in FIG. 4 and FIGS. 13 to 15 , forming the gate structure 50 in the target gap in step S80 may include the following steps:

Step S82, forming a gate dielectric layer 51 on the exposed sidewalls of the active pillar 20 in the target gap, wherein the thickness of the gate dielectric layer 51 is less than the thickness of the target liner layer 31';

Step S84, forming a work function material layer 5211, the work function material layer 5211 fills the gap between the target second isolation structure 30 and the adjacent active pillar 20, and covers the exposed surface of the gate dielectric layer 51 and the top surface of the target first isolation structure 10;

Step S86, forming a conductive material layer 5221, wherein the top surface of the conductive material layer 5221 located on one side of the target second isolation structure 30 along the third direction is higher than the top surface of the active pillar 20; the third direction is a direction perpendicular to the bottom surface of the target substrate 100';

In step S88, the work function material layer 5211 and the conductive material layer 5221 are etched back. The remaining top surface of the work function material layer 5211 flush with the top surface of the gate dielectric layer 51 constitutes a work function layer 521. The remaining top surface of the conductive material layer 5221 flush with the top surface of the gate dielectric layer 51 constitutes a gate conductive layer 522. The gate dielectric layer 51, the work function layer 521 and the gate conductive layer 522 constitute a gate structure 50.

As an example, please continue to refer to Figures 13-14. In step S82, at least one of an in-situ steam generation process (ISSG), an atomic layer deposition process, a plasma vapor deposition process, and a rapid thermal oxidation process (RTO) can be used to form a gate dielectric layer 51 on the exposed sidewall of the active pillar 20 in the target gap, and the thickness of the gate dielectric layer 51 is less than the thickness of the target liner layer 31'. The material of the gate dielectric layer 51 may include silicon oxide. In step S84, a deposition process may be used to form a work function material layer 5211, and the work function material layer 5211 fills the gap between the target second isolation structure 30 and the adjacent active pillar 20. The material of the work function material layer 5211 can be selected from titanium nitride (TiN), thallium nitride (TaN), titanium aluminum nitride (TiAlN), tungsten carbide nitride (WCN), molybdenum carbide nitride (MOCN), titanium aluminum carbon nitride (TiAlCN), etc. and combinations thereof. In step S86, a deposition process may be used to form a conductive material layer 5221, wherein the top surface of the portion of the conductive material layer 5221 located on one side of the target first isolation structure 10 along the third direction (e.g., the oz direction) is higher than the top surface of the insulating pillar 32, and the top surface of the portion of the conductive material layer 5221 located on one side of the target second isolation structure 30 along the third direction (e.g., the oz direction) is higher than the top surface of the active pillar 20; the material of the conductive material layer 5221 is selected from titanium, Tungsten, nickel, gold, silver, tungsten silicide, aluminum, palladium, copper, etc. and combinations thereof. In step S88, a dry etching process may be used to etch back the work function material layer 5211 and the conductive material layer 5221, and the remaining work function material layer 5211 whose top surface is flush with the top surface of the gate dielectric layer 51 constitutes the work function layer 521, and the remaining conductive material layer 5221 whose top surface is flush with the top surface of the gate dielectric layer 51 constitutes the gate conductive layer 522, and the gate dielectric layer 51, the work function layer 521 and the gate conductive layer 522 constitute the gate structure 50; the gate structure 50 surrounds the bare portion of the active pillar 20. The side walls are exposed, and the top surface is not higher than the top surface of the insulating column 32, for example, the top surface of the gate structure 50 is flush with the top surface of the insulating column 32; wherein the gate structures 50 on the active columns 20 adjacent to each other along the first direction (for example, the ox direction) are in contact and connected to form a word line structure extending along the ox direction; the gate structures 50 on the active columns 20 adjacent to each other along the second direction (for example, the oy direction) are isolated by the insulating column 32, so that the word line structures adjacent to each other along the oy direction prepared subsequently are insulated from each other.

As an example, please continue to refer to Figures 14-15. The protective layer 40 can be removed during the process of etching back the work function material layer 5211 and the conductive material layer 5221 to relatively reduce the process steps. In other embodiments, the protective layer 40 can also be removed after obtaining the gate structure 50 to meet the actual needs of various different application scenarios. The device formed on the active column 20 can be a junctionless transistor, and the active column 20 can include a source structure, a vertical channel, a gate structure 50 and a drain structure arranged in sequence to form a junctionless transistor. The types of doped ions in the source structure, the vertical channel, the gate structure 50 and the drain structure can be the same. On the one hand, it can ensure the control ability of the transistor gate, improve the integration density and electrical performance of the semiconductor device, and effectively avoid the adverse effects caused by the growth of the bit line structure, thereby ensuring the performance and reliability of the process VGAA transistor.

As an example, referring to FIG. 16 , after obtaining the gate structure 50 and removing the protection layer 40 , the following steps may also be included:

Step S90 , forming a capping layer 60 whose top surface is flush with the top surface of the active pillar 20 ; the capping layer 60 fills the gaps between the active pillars 20 adjacent to each other along the first direction (eg, ox direction) and the second direction (eg, oy direction).

As an example, please continue to refer to FIG. 16. In step S90, a deposition process may be used to form a capping layer 60 whose top surface is flush with the top surface of the active pillar 20; the capping layer 60 fills the gaps between the active pillars 20 adjacent to each other in the first direction (e.g., ox direction) and the second direction (e.g., oy direction). The material of the capping layer 60 is selected from silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, etc. and combinations thereof.

As an example, please continue to refer to FIG. 16 , the step S90 of forming the capping layer 60 whose top surface is flush with the top surface of the active pillar 20 may include the following steps:

Step S92, forming a spacer material layer 61 whose top surface is higher than the top surface of the active pillar 20; the spacer material layer 61 fills the gaps between the active pillars 20 adjacent to each other along the first direction (eg, ox direction) and the second direction (eg, oy direction);

Step S94 , planarizing the spacer material layer 61 to obtain the cap layer 60 .

As an example, please continue to refer to FIG. 16. In step S92, a deposition process may be used to form a spacer material layer 61 whose top surface is higher than the top surface of the active pillar 20; the spacer material layer 61 fills the gaps between the active pillars 20 adjacent along the first direction (e.g., the ox direction) and the second direction (e.g., the oy direction); the material of the spacer material layer 61 is selected from silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, etc. and combinations thereof. In step S92, at least one of a chemical mechanical polishing process, a dry etching process, and a flat push process may be used to process the spacer material layer 61 to obtain a cap layer 60 with a flush top surface.

Although the various steps in the flowchart of Fig. 4 are shown in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence according to the indication of the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in sequence, and these steps can be performed in other sequences. Moreover, although at least a part of the steps in Fig. 4 can include multiple sub-steps or multiple stages, these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution of these sub-steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

As an example, please refer to FIG. 16. The present disclosure provides a semiconductor device, which includes a target substrate 100' and a gate structure 50. The bottom surface of the target substrate 100' has a plurality of active pillars 20 arranged in an array, the plurality of active pillars 20 are arranged along a first direction to form an active pillar row, the plurality of active pillars 20 are arranged along a second direction to form an active pillar column, the adjacent active pillars 20 in the active pillar row have a target first isolation structure 10, and the adjacent active pillars 20 in the active pillar column have a target first isolation structure 10. The target second isolation structure 30 is provided between the target substrate 100' and the target second isolation structure 30; the target second isolation structure 30 includes an insulating column 32 and a target liner layer 31' covering the side of the insulating column 32; the top surfaces of the target second isolation structure 30 and the target first isolation structure 10 are lower than the top surface of the active column 20; the first direction intersects with the second direction and is parallel to the bottom surface of the target substrate 100'; the gate structure 50 surrounds the active column 20. "Below" or "higher" in the present disclosure is based on the bottom surface of the target substrate 100' as a reference, that is, "lower" or "higher" is determined by comparing the distance from the bottom surface of the target substrate 100'.

The semiconductor device in the above-mentioned embodiment forms an exposed side wall of the active pillar 20 by making the top surfaces of the target first isolation structure 10 and the target second isolation structure 30 lower than the top surface of the active pillar 20, and then a protective layer 40 can be formed on the exposed side wall of the active pillar 20. There is no air gap in the dense protective layer 40, so as to avoid damaging the surface of the active pillar 20 covered by the protective layer 40 during the subsequent formation of the gate dielectric layer 51 on the surface of the active pillar 20 exposed in the target gap; and avoid forming a conductive material in the air gap during the formation of the gate conductive layer 522, so as to avoid the leakage current between the gate structure 50 and the source structure induced by the conductive material in the air gap during the operation of the VGAA transistor.

As an example, please continue to refer to FIG. 16 , the bottom surface of the target second isolation structure 30 is higher than the bottom surface of the target first isolation structure 10, so as to facilitate the subsequent formation of the bit line structure 300 extending along the second direction and spaced apart along the first direction. The top surface of the target liner layer 31 'and the top surface of the target first isolation structure 10 are both lower than the top surface of the insulating column 32, so as to facilitate the formation of the gate structure 50 on the exposed sidewall of the insulating column 32; the top surface of the insulating column 32 is lower than the top surface of the active column 20, so as to facilitate the subsequent formation of the cap layer 60.

As an example, please continue to refer to Figure 16, the top surface of the gate structure 50 is not higher than the top surface of the insulating column 32; the gate structures 50 on the active columns 20 adjacent to each other along the first direction are in contact and connected, and the gate structures 50 on the active columns 20 adjacent to each other along the second direction are isolated by the insulating columns 32 to form a word line structure 200 extending along the first direction and spaced apart along the second direction.

In the semiconductor device in the above embodiment, the device formed by the active pillar 20 can be a junctionless transistor, and a source, a vertical channel and a drain arranged in sequence can be formed on the active pillar 20, which can ensure the control capability of the transistor gate and improve the integration density and electrical performance of the semiconductor device; because the initial second isolation structure 30' adjacent along the second direction (for example, the oy direction) can be used to form a bit line structure 300 whose bottom surface is not lower than the bottom surface of the target first isolation structure 10 in the target substrate 100' directly below the active pillar 20 adjacent along the second direction (for example, the oy direction), the bit line structures 300 adjacent along the first direction (for example, the ox direction) are insulated from each other, and the growth of the bit line structure 300 is prevented from having adverse effects on the VGAA transistor, thereby ensuring the performance and reliability of the semiconductor device.

As an example, please continue to refer to Figure 16, the semiconductor device further includes a capping layer 60, the top surface of the capping layer 60 is flush with the top surface of the active pillar 20, and is located on the side of the gate structure 50 away from the bottom surface of the target substrate 100'. The material of the capping layer 60 is selected from silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, etc. and combinations thereof.

As an example, please continue to refer to Figure 16. The gate structure 50 includes a gate dielectric layer 51, a work function layer 521 and a gate conductive layer 522. The gate dielectric layer 51 covers the side wall of the active pillar 20, and the thickness of the gate dielectric layer 51 is less than the thickness of the target pad layer 31'; the top surface of the gate dielectric layer 51 is not higher than the top surface of the insulating pillar 32; the work function layer 521 covers the side of the gate dielectric layer 51 and is located between the gate dielectric layer 51 and the insulating pillar 32, and the top surface of the work function layer 521 is not higher than the top surface of the gate dielectric layer 51; the gate conductive layer 522 is located on the side of the work function layer 521 away from the gate dielectric layer 51, and the top surface of the gate conductive layer 522 is not higher than the top surface of the gate dielectric layer 51.

As an example, please continue to refer to FIG. 16, the semiconductor device further includes a bit line structure 300, which extends along the second direction and is located in the target substrate 100' on one side of the target second isolation structure 30 adjacent to the second direction along the third direction, and the bottom surface of the target first isolation structure 10 is lower than the bottom surface of the bit line structure 300; the third direction is a direction perpendicular to the bottom surface of the target substrate 100'. The first direction, the second direction and the third direction can be set to be perpendicular to each other.

As an example, the material of the active pillar can be selected from single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, silicon germanium, etc. and combinations thereof. The material of the protective layer can be selected from silicon nitride, silicon oxynitride, silicon carbide nitride, aluminum oxide, etc. and combinations thereof. The material of the target pad layer can include silicon oxide. The material of the insulating pillar can be selected from silicon nitride, silicon oxynitride, silicon carbide nitride, aluminum oxide, etc. and combinations thereof. The material of the cap layer can be selected from silicon nitride, silicon oxynitride, silicon carbide nitride, aluminum oxide, etc. and combinations thereof.

As an example, please continue to refer to FIG. 16 . The present disclosure provides a memory including the above-mentioned semiconductor device. The device formed by the active pillar 20 can be a junctionless transistor. A source, a vertical channel and a drain arranged in sequence can be formed on the active pillar 20, which can ensure the control capability of the transistor gate and improve the integration density and electrical performance of the memory. Since a bit line structure 300 having a bottom surface not lower than the bottom surface of the target first isolation structure 10 can be formed in the target substrate 100' directly below the active pillar 20 adjacent along the second direction (for example, the oy direction) with the help of the initial second isolation structure 30' adjacent along the second direction (for example, the oy direction), the bit line structures 300 adjacent along the first direction (for example, the ox direction) are insulated from each other, and the growth of the bit line structure 300 is prevented from having adverse effects on the VGAA transistor, thereby ensuring the performance and reliability of the memory.

As an example, the present disclosure provides an electronic device, including the above-mentioned memory. The electronic device is, for example, but not limited to, a suitable type of electronic product such as a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, etc. Consumer electronic products include mobile phones, tablet computers, laptop computers, desktop monitors, all-in-one computers, etc. Home electronic products include smart door locks, televisions, refrigerators, wearable devices, etc. Vehicle-mounted electronic products include vehicle-mounted navigation systems, vehicle-mounted DVDs, etc. Financial terminal products include ATM machines, self-service terminals, etc.

The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims (22)

1. A method for preparing a semiconductor device, comprising:

   A target substrate having a bottom surface is provided, and a plurality of active pillars arranged in an array are formed on the bottom surface of the target substrate, wherein the plurality of active pillars are arranged along a first direction to form an active pillar row, and the plurality of active pillars are arranged along a second direction to form an active pillar column, an initial first isolation structure is provided between adjacent active pillars in the active pillar row, and an initial second isolation structure is provided between adjacent active pillars in the active pillar column; the top surface of the initial first isolation structure and the top surface of the initial second isolation structure are both lower than the top surface of the active pillar, so as to obtain an exposed side wall of the active pillar; the first direction intersects with the second direction and is parallel to the bottom surface of the target substrate;

   forming a protective layer on the exposed sidewalls of the active pillar;

   removing a portion of a top of the initial second isolation structure and a top of the initial first isolation structure to obtain a target gap between the active pillar and a top of the initial second isolation structure;

   A gate structure is formed in the target gap.
2. The method for preparing a semiconductor device according to claim 1, wherein the initial second isolation structure comprises an insulating column and an initial liner layer covering the outer side and bottom surface of the insulating column; and removing a portion of the top of the initial second isolation structure comprises:

   The top of the initial liner layer is removed to expose the top of the insulating pillar.
3. The method for preparing a semiconductor device according to claim 1, wherein providing a target substrate having a bottom surface comprises:

   Providing an initial substrate, wherein a plurality of active walls arranged along the first direction are formed on the bottom surface of the initial substrate, a first trench isolation structure is provided between adjacent active walls, and the active walls extend along the second direction;

   forming a plurality of second trenches extending along the first direction and arranged at intervals along the second direction on the bottom surface of the initial substrate, wherein the bottom surface of the second trench is higher than the bottom surface of the first trench isolation structure;

   forming a liner material layer on the bottom surface of the second trench and the sidewalls opposite to the second direction;

   forming an insulating material layer in the second trench, the top surface of which is flush with the top surface of the active pillar, wherein the liner material layer and the insulating material layer constitute a second trench isolation structure;

   The first trench isolation structure and the second trench isolation structure are etched back to obtain the initial first isolation structure and the initial second isolation structure whose top surfaces are lower than the top surface of the active pillar, so as to provide the target substrate.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the etching back the first trench isolation structure and the second trench isolation structure comprises:

   By controlling the etching rate and time of the first trench isolation structure and the second trench isolation structure, the initial first isolation structure and the initial second isolation structure whose top surfaces are lower than the top surface of the active pillar are obtained.
5. The method for preparing a semiconductor device according to claim 4, wherein the step of forming a protective layer on the exposed sidewalls of the active pillar comprises:

   Forming a protective material layer on the exposed surface of the active pillar, the top surface of the initial first isolation structure, and the top surface of the initial second isolation structure by an atomic layer deposition process;

   The protective material layer located on the top surface of the active pillar, the top surface of the initial first isolation structure and the top surface of the initial second isolation structure is removed, and the protective material layer located on the side wall of the active pillar is retained to form the protective layer.
6. The method for preparing a semiconductor device according to claim 2, wherein the removing of the initial liner layer and the top of the initial first isolation structure comprises:

   The initial pad layer and the top of the initial first isolation structure are removed by a wet etching process, the remaining initial pad layer constitutes a target pad layer, the remaining initial first isolation structure constitutes a target first isolation structure, and the target pad layer and the insulating column constitute a target second isolation structure.
7. The method for manufacturing a semiconductor device according to claim 6, wherein forming a gate structure in the target gap comprises:

   A gate dielectric layer is formed on the exposed sidewalls of the active pillars in the target gap, wherein the thickness of the gate dielectric layer is less than the target gap. The target liner layer thickness;

   forming a work function material layer, wherein the work function material layer fills the gap between the target second isolation structure and the adjacent active pillar and covers the exposed surface of the gate dielectric layer and the top surface of the target first isolation structure;

   forming a conductive material layer, wherein a top surface of a portion of the conductive material layer located on one side of the target second isolation structure along a third direction is higher than a top surface of the active pillar; the third direction is a direction perpendicular to a bottom surface of the target substrate;

   The work function material layer and the conductive material layer are etched back, and the remaining work function material layer whose top surface is flush with the top surface of the gate dielectric layer constitutes a work function layer, and the remaining conductive material layer whose top surface is flush with the top surface of the gate dielectric layer constitutes a gate conductive layer. The gate dielectric layer, the work function layer and the gate conductive layer constitute the gate structure.
8. The method for preparing a semiconductor device according to claim 7, wherein the protective layer is removed during the process of etching back the work function material layer and the conductive material layer, or

   The protection layer is removed after the gate structure is obtained.
9. The method for preparing a semiconductor device according to claim 8, wherein after obtaining the gate structure and removing the protective layer, it further comprises:

   A capping layer is formed whose top surface is flush with the top surface of the active pillar; the capping layer fills up the gaps between the active pillars adjacent to each other along the first direction and the second direction.
10. The method for preparing a semiconductor device according to claim 9, wherein the forming of a capping layer having a top surface flush with a top surface of the active pillar comprises:

    forming a spacer material layer whose top surface is higher than the top surface of the active pillar; the spacer material layer fills the gaps between the active pillars adjacent to each other along the first direction and the second direction;

    The spacer material layer is planarized to obtain the cap layer.
11. The method for preparing a semiconductor device according to claim 10, wherein the planarizing process of the spacer material layer comprises:

    The spacer material layer is processed by at least one of a chemical mechanical polishing process, a dry etching process and a push-on process.
12. The method for preparing a semiconductor device according to any one of claims 3 to 5, wherein after forming a liner material layer on the bottom surface of the second trench and the sidewalls opposite to the second direction and before forming the insulating material layer, the method further comprises:

    Ions are injected into the initial substrate on one side along the third direction through the bottom of the second trench, and an annealing process is performed, so that the conductive regions formed in the initial substrate on one side along the third direction of the adjacent second trenches are electrically connected, and a bit line structure extending along the second direction is formed; the bottom surface of the initial first isolation structure is lower than the bottom surface of any of the conductive regions; the third direction is a direction perpendicular to the bottom surface of the target substrate.
13. A semiconductor device, comprising:

    A target substrate, wherein a plurality of active pillars arranged in an array are provided on the bottom surface of the target substrate, wherein the plurality of active pillars are arranged along a first direction to form an active pillar row, and the plurality of active pillars are arranged along a second direction to form an active pillar column, a target first isolation structure is provided between adjacent active pillars in the active pillar row, and a target second isolation structure is provided between adjacent active pillars in the active pillar column; the top surfaces of the target second isolation structure and the target first isolation structure are lower than the top surfaces of the active pillars; the first direction intersects with the second direction and are both parallel to the bottom surface of the target substrate;

    The gate structure surrounds the active pillar.
14. The semiconductor device according to claim 13, wherein the target second isolation structure comprises an insulating column and a target liner layer covering a side surface of the insulating column.
15. The semiconductor device according to claim 14, wherein a top surface of the target liner layer and a top surface of the target first isolation structure are both lower than a top surface of the insulating column, and a top surface of the insulating column is lower than a top surface of the active column.
16. The semiconductor device according to claim 14, wherein the top surface of the gate structure is not higher than the top surface of the insulating column; the gate structures on the active columns adjacent to each other along the first direction are in contact with each other, and the gate structures on the active columns adjacent to each other along the second direction are isolated by the insulating column.
17. The semiconductor device according to claim 14, wherein the gate structure comprises:

    a gate dielectric layer covering the sidewalls of the active pillar, wherein the thickness of the gate dielectric layer is less than the thickness of the target liner layer; and the top surface of the gate dielectric layer is not higher than the top surface of the insulating pillar;

    a work function layer, covering the side surface of the gate dielectric layer and being located between the gate dielectric layer and the insulating pillar, wherein the top surface of the work function layer is not higher than the top surface of the gate dielectric layer;

    The gate conductive layer is located on a side of the work function layer away from the gate dielectric layer, and the top surface of the gate conductive layer is not higher than the top surface of the gate dielectric layer.
18. The semiconductor device according to claim 15, further comprising:

    The bit line structure extends along the second direction and is located in the target substrate on one side of the target second isolation structure adjacent to the second direction along the third direction, and the bottom surface of the target first isolation structure is lower than the bottom surface of the bit line structure; the third direction is a direction perpendicular to the bottom surface of the target substrate.
19. The semiconductor device according to any one of claims 13 to 18, further comprising:

    The capping layer has a top surface flush with the top surface of the active pillar and is located on a side of the gate structure that is away from the bottom surface of the target substrate.
20. The semiconductor device according to claim 14, further comprising at least one of the following features:

    The material of the active pillar is selected from single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, germanium silicon and a combination thereof;

    The material of the target liner layer includes silicon oxide;

    The material of the insulating column is selected from silicon nitride, silicon oxynitride, silicon carbide nitride, aluminum oxide and a combination thereof.
21. A memory, comprising:

    A semiconductor device as claimed in any one of claims 13 to 20.
22. An electronic device, comprising:

    The memory of claim 21.