CN102468152B - Manufacturing method of gate medium layer and transistor - Google Patents
Manufacturing method of gate medium layer and transistor Download PDFInfo
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- CN102468152B CN102468152B CN2010105326165A CN201010532616A CN102468152B CN 102468152 B CN102468152 B CN 102468152B CN 2010105326165 A CN2010105326165 A CN 2010105326165A CN 201010532616 A CN201010532616 A CN 201010532616A CN 102468152 B CN102468152 B CN 102468152B
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Abstract
The invention provides a manufacturing method of a gate medium layer and a transistor. The manufacturing method of the gate medium layer comprises the following steps: providing a semiconductor substrate; cleaning the semiconductor substrate; forming an interface oxidation layer on the cleaned semiconductor substrate; forming a high K medium layer on the interface oxidation layer. By using the method of the invention, an adhesive force between the interface oxidation layer and the semiconductor substrate can be improved. Uniformity and compactness of the interface oxidation layer can be improved too. Thermal budgets of the semiconductor substrate and the finally formed transistor can be reduced and performance of a device can be improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly gate dielectric layer and transistorized manufacture method.
Background technology
Along with the field of integrated circuit feature size downsizing to deep-submicron, transistorized grid size dwindles, and correspondingly the thickness as the silicon dioxide layer of gate dielectric layer also needs to reduce, and to improve transistorized grid capacitance, prevents that short-channel effect from appearring in device.But, when gate dielectric layer thickness dwindles gradually, the thickness of gate dielectric layer is decreased to below 3 nanometers, produces a lot of problems thereupon, for example: (1) leakage current increases; (2), there is the impurity concentration gradient in Impurity Diffusion between gate dielectric layer and Semiconductor substrate, described impurity can be diffused in Semiconductor substrate or be fixed in gate dielectric layer from grid, finally affects the performance of device.
Therefore, those skilled in the art adopt new gate dielectric layer to replace existing gate dielectric layer to replace existing silicon dioxide.For the electric capacity that keeps gate dielectric layer is constant, those skilled in the art adopt high-k (high K) dielectric layer as new gate dielectric layer.Described high K dielectric layer has thermal stability and mechanical strength preferably, can obtain less leakage current.
Prior art is utilized the high K dielectric layer to make transistorized method and be please refer to Fig. 1 to Fig. 2.At first, with reference to figure 1, provide Semiconductor substrate 100, in described Semiconductor substrate 100, be formed with at least two isolation structures 101, the zone between adjacent isolation structure 101 is active area, in the Semiconductor substrate 100 of described active area, is formed with dopant well 103.Then, carry out oxidation technology, form interface oxide layer 107 on described Semiconductor substrate 100, for the high K dielectric layer that improves follow-up formation and the adhesive force between Semiconductor substrate 100.
Then, still with reference to figure 1, form high K dielectric layer 104 above described interface oxide layer 107.
Then, please refer to Fig. 2, utilize described interface oxide layer 107 and high K dielectric layer 104 as gate dielectric layer, described gate dielectric layer is carried out to etching, form metal gates 105 on gate dielectric layer after etching, form side wall 112, the interior formation light doping section 110 of Semiconductor substrate 100 and source/drain region 114 in described metal gates 105 both sides in described metal gates 105 both sides.
Can also find more information about existing preparation method of transistor in the Chinese patent application that is CN101661883A at publication number.
Find in practice, there is leakage current in the transistor that existing method is made, the unstable properties of device.
Summary of the invention
The problem that the present invention solves is to provide a kind of manufacture method and transistorized manufacture method of gate dielectric layer, has reduced transistorized leakage current, has improved the stability of device.
For addressing the above problem, the invention provides a kind of manufacture method of gate dielectric layer, comprising:
Semiconductor substrate is provided;
Described Semiconductor substrate is cleaned;
Form interface oxide layer on Semiconductor substrate after cleaning;
Form the high K dielectric layer on described interface oxide layer.
Alternatively, described cleaning utilizes hydrofluoric acid to carry out.
Alternatively, the mass concentration of described hydrofluoric acid is 10%～0.01%, and the time of described cleaning is for being no more than 60 minutes.
Alternatively, the time interval of the step of described cleaning step and described formation interface oxide layer is for being no more than 30 minutes.
Alternatively, described interface oxide layer utilizes ozone process to make, and the parameter of described ozone process is:
Semiconductor substrate after described cleaning is positioned in bag ultra-pure water ozoniferous, soaks 1～2000 second, the temperature of described ultra-pure water is less than or equal to 200 degrees centigrade.
Alternatively, the mass concentration of described ozone in water is 1～500ppm.
Alternatively, the thickness range of described interface oxide layer is 4～20 dusts, and the thickness range of described high K dielectric layer is 10～40 dusts.
Accordingly, the present invention also provides a kind of transistorized manufacture method, comprising:
Semiconductor substrate is provided;
Described Semiconductor substrate is cleaned;
Form interface oxide layer on Semiconductor substrate after cleaning;
Form the high K dielectric layer on described interface oxide layer;
The described high K dielectric layer of etching and interface oxide layer;
Form metal gates on described high K dielectric layer and interface oxide layer;
Formation source/drain region in described Semiconductor substrate.
Alternatively, described cleaning utilizes hydrofluoric acid to carry out.
Alternatively, the mass concentration of described hydrofluoric acid is 10%～0.01%, and the time of described cleaning is for being no more than 60 minutes.
Alternatively, the time interval of the step of described cleaning step and described formation interface oxide layer is for being no more than 30 minutes.
Alternatively, described interface oxide layer utilizes ozone process to make, and the parameter of described ozone process is:
Semiconductor substrate after described cleaning is positioned in bag ultra-pure water ozoniferous, soaks 1～2000 second, the temperature of described ultra-pure water is less than or equal to 200 degrees centigrade.
Compared with prior art, the present invention has the following advantages:
The present invention is before forming interface oxide layer, described Semiconductor substrate is cleaned, the natural oxidizing layer (native oxide) of removal semiconductor substrate surface, organic pollution, particulate pollutant etc., form interface oxide layer on Semiconductor substrate after cleaning, thereby improved the adhesive force between interface oxide layer and Semiconductor substrate, improve uniformity and the compactness of interface oxide layer, reduce the leakage current of the final device formed, improved the stability of device;
Further, the technique that the present invention forms interface oxide layer is ozone process, described ozone process bag is for being positioned over the Semiconductor substrate after described cleaning in bag ultra-pure water ozoniferous, soak 1～2000 second, in the ozone process process, the temperature of described ultra-pure water is less than or equal to 200 degrees centigrade, with prior art, utilizes thermal oxidation technology to make oxide layer and compares, reduce the heat budget to Semiconductor substrate, prevented the excessive unstable properties that causes the device of final formation of heat budget.
The accompanying drawing explanation
Fig. 1～Fig. 2 is that prior art utilizes the high K dielectric layer to make transistorized cross-sectional view.
Fig. 3 is high K dielectric layer manufacturing method thereof schematic flow sheet of the present invention.
Fig. 4～Fig. 6 is the gate dielectric layer manufacture method cross-sectional view of one embodiment of the invention.
Fig. 7 is preparation method of transistor schematic flow sheet of the present invention.
Fig. 8～Figure 11 is the preparation method of transistor cross-sectional view of one embodiment of the invention.
Embodiment
Prior art utilizes the transistor of high K dielectric layer making at leakage current, the unstable properties of device.Study discovery through the inventor, one of reason that causes existing high K dielectric layer to have leakage current is that the adhesive force between interface oxide layer and Semiconductor substrate is bad, for example, because prior art is utilized thermal oxidation process (furnace oxidation or RTO method for oxidation) usually, directly Semiconductor substrate is heated, prior art is the natural oxidizing layer to semiconductor substrate surface, Organic Pollution, particles etc. are removed, the interface oxide layer unevenness that makes thermal oxidation process form at semiconductor substrate surface, affect uniformity (described uniformity is greater than 3%) and the compactness of interface oxide layer, and improved the insulation effect of interface oxide layer, increased the leakage current of device.
And, because prior art is utilized thermal oxidation process making transistor, the temperature of described thermal oxidation process is at least at 800 degrees centigrade, and this has strengthened Semiconductor substrate and the final transistorized heat budget formed, affect the work function of metal gates, make the unstable properties of device.
In order to address the above problem, the inventor, through creative work, proposes a kind of gate dielectric layer and transistorized manufacture method.Please refer to Fig. 3, the manufacture method of described gate dielectric layer comprises:
Semiconductor substrate is provided;
Described Semiconductor substrate is cleaned;
Form interface oxide layer on Semiconductor substrate after cleaning;
Form the high K dielectric layer on described interface oxide layer.
Below in conjunction with specific embodiments technical scheme of the present invention is described in detail., in conjunction with Fig. 4～Fig. 6, be please the gate dielectric layer manufacture method cross-sectional view of one embodiment of the invention.
Please refer to Fig. 4, Semiconductor substrate 200 is provided, described Semiconductor substrate 200, be formed with at least two isolation structures 201 in described Semiconductor substrate 200, and the zone between adjacent isolation structures 201 is active area.
The material of described Semiconductor substrate 200 can be silicon, germanium silicon etc.
Described Semiconductor substrate 200 is carried out to Implantation, at described active area, form dopant well 203.The method that forms dopant well 203 is same as the prior art, and the known technology as those skilled in the art, be not described in detail at this.
Then, described Semiconductor substrate 200 is carried out to cleaning step.Described cleaning step is for removing natural oxidizing layer, organic pollution and the particle of semiconductor substrate surface.As an embodiment, described natural oxidizing layer utilizes hydrofluoric acid to remove, and is about to described Semiconductor substrate and is positioned in hydrofluoric acid solution, soaks and is no more than 60 minutes.As an embodiment, the concentration of described hydrofluoric acid solution is 10%～0.01%.
Through described cleaning step, the natural oxidizing layer of semiconductor substrate surface, organic pollution, particle etc. are removed, more be conducive to the follow-up ozone process carried out and form interface oxide layer at semiconductor substrate surface, and improve uniformity and the compactness of described interface oxide layer.
Because the Semiconductor substrate after cleaning is placed in air, may form new natural oxidizing layer, influential to the ozone process of follow-up formation interface oxide layer for fear of this natural oxidizing layer, the time interval of the step of described cleaning step and interface oxide layer is unsuitable long, the described time interval should be no more than 30 minutes, and the described time interval is more short better.
Then, please refer to Fig. 5, form interface oxide layer 207 on the Semiconductor substrate 200 after described cleaning.As an embodiment, the thickness range of described interface oxide layer is 4～20 dusts.
Inventor's discovery, the manufacture method of described interface oxide layer 207 can be thermal oxidation process, chemical gaseous phase depositing process or ozone process method.
Particularly, described thermal oxidation process is positioned over hot environment by described Semiconductor substrate 200, and at the oxygen of the Semiconductor substrate 200 logical certain flow in surface, the pasc reaction of described oxygen and Semiconductor substrate under hot environment, form interface oxide layer 207.The temperature of common described hot environment is at least 800 degrees centigrade, and this can increase described Semiconductor substrate 200 and the final transistorized heat budget formed.
Described chemical gaseous phase depositing process more than 400 degrees centigrade at described Semiconductor substrate 200 surface deposition interface oxide layers 207.The uniformity of the interface oxide layer 207 that the heavy method of chemical gaseous phase forms is bad, and may increase described Semiconductor substrate 200 and the final transistorized heat budget formed.
Therefore, as preferred embodiment, the present invention utilizes the ozone process method to make described interface oxide layer.As an embodiment, the parameter of described ozone process is:
As preferred embodiment, described ozone mass concentration is 1～500ppm.The temperature of described ozone process is 20～150 degrees centigrade, and this temperature range has reduced the transistorized heat budget formed greatly.
In order to verify the uniformity of the interface oxide layer that ozone process forms, the inventor tests, the temperature of ozone process is 30 degrees centigrade, the soak time of ozone process is 600 seconds, ozone concentration is 50ppm, and the average thickness of the interface oxide layer of acquisition is 10 dusts, and the uniformity of described interface oxide layer is 1.1%, the uniformity of the interface oxide layer formed with prior art is 3% to compare, and has greatly improved the uniformity of interface oxide layer.
Then, please refer to Fig. 6, form high K dielectric layer 204 on described interface oxide layer 207.The thickness range of described high K dielectric layer 204 is 10～40 dusts.The material of described high K dielectric layer can be hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium or aluminium oxide etc.
The present invention also provides a kind of transistorized manufacture method, please refer to Fig. 7, and described method comprises:
Step S1, provide Semiconductor substrate;
Step S2, cleaned described Semiconductor substrate;
Step S3, form interface oxide layer on the Semiconductor substrate after cleaning;
Step S4 forms the high K dielectric layer on described interface oxide layer;
Step S5, the described high K dielectric layer of etching and interface oxide layer;
Step S6, formation source/drain region in described Semiconductor substrate;
Step S7 forms metal gates on described high K dielectric layer and interface oxide layer.
Below in conjunction with specific embodiments technical scheme of the present invention is elaborated.Please in conjunction with the preparation method of transistor cross-sectional view of the present invention shown in Fig. 8～Figure 11.
At first, with reference to figure 8, Semiconductor substrate 200 is provided, described Semiconductor substrate 200, be formed with at least two isolation structures 201 in described Semiconductor substrate 200, zone between adjacent isolation structures 201 is active area, is formed with interface oxide layer 207 and high K dielectric layer 204 on described Semiconductor substrate 200.The manufacture method of described interface oxide layer 207 and high K dielectric layer 204 please refer to the gate dielectric layer manufacture method of an embodiment, at this, does not do and repeats.
Then, please refer to Fig. 9, as preferred embodiment, on described high K dielectric layer 207, form polysilicon layer, then the described polysilicon layer of etching, form polysilicon gate 212.Described polysilicon gate 212, as dummy grid (dummy gate), finally will be removed.Then, the described interface oxide layer 207 of etching and high K dielectric layer 204, make the width of described interface oxide layer 207 and high K dielectric layer 204 identical with the width of described polysilicon gate 212.
Then, the interface oxide layer 207 after described polysilicon gate 212, etching and high K dielectric layer 204 both sides form side wall 212.Described side wall 212 is the ONO structure that silica-silicon nitride-silicon oxynitride forms.The method that forms described side wall 212 is same as the prior art, and the known technology as those skilled in the art, be not described in detail here.
Then, please refer to Figure 10, form interlayer dielectric layer 213 on described Semiconductor substrate 200, described interlayer dielectric layer 213 flushes with described polysilicon gate 214 (with reference to figure 9) and side wall 212.Described interlayer dielectric layer 213 can for silica, silicon nitride, carborundum or silicon oxynitride,
Then, still with reference to Figure 10, carry out etching technics, remove described polysilicon gate 213, at the interior formation opening of described interlayer dielectric layer 213, described opening exposes the high K dielectric layer 204 of below.
Then, please refer to Figure 11, form barrier layer 209 in described opening, form above described barrier layer 209.Metal gates 205, described metal gates 205 flushes with described interlayer dielectric layer 213.The method that forms described barrier layer 209 and metal gates 205 is same as the prior art, and the known technology as those skilled in the art, be not described in detail at this.
To sum up, the method that the present invention proposes is cleaned Semiconductor substrate, on the Semiconductor substrate after described cleaning, forms interface oxide layer, has improved the adhesive force of interface oxide layer and Semiconductor substrate, has improved uniformity and the compactness of described interface oxide layer; Described interface oxide layer utilizes ozone process to form, and the temperature of described ozone process is less than 200 degrees centigrade, avoids causing Semiconductor substrate and the final transistorized heat budget formed, and has improved the performance of device.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (12)
1. the manufacture method of a gate dielectric layer, is characterized in that, comprising:
Semiconductor substrate is provided;
Described Semiconductor substrate is cleaned;
Semiconductor substrate after cleaning is positioned in bag ultra-pure water ozoniferous, formation is positioned at the interface oxide layer of semiconductor substrate surface, the temperature of described ultra-pure water, for being more than or equal to 30 degrees centigrade, is less than or equal to 200 degrees centigrade, and the mass concentration of described ozone is 50-500ppm;
Form the high K dielectric layer on described interface oxide layer.
2. the manufacture method of gate dielectric layer as claimed in claim 1, is characterized in that, described cleaning utilizes hydrofluoric acid to carry out.
3. the manufacture method of gate dielectric layer as claimed in claim 2, is characterized in that, the mass concentration of described hydrofluoric acid is 10%～0.01%, and the time of described cleaning is for being no more than 60 minutes.
4. the manufacture method of gate dielectric layer as claimed in claim 1, is characterized in that, the time interval of the step of described cleaning step and described formation interface oxide layer is for being no more than 30 minutes.
5. the manufacture method of gate dielectric layer as claimed in claim 1, is characterized in that, the Semiconductor substrate after described cleaning is positioned in bag ultra-pure water ozoniferous and soaks 1～2000 second.
6. the manufacture method of gate dielectric layer as claimed in claim 1, is characterized in that, the temperature of described ozone process is 30～100 degrees centigrade.
7. the manufacture method of gate dielectric layer as claimed in claim 1, is characterized in that, the thickness range of described interface oxide layer is 4～20 dusts, and the thickness range of described high K dielectric layer is 10～40 dusts.
8. a transistorized manufacture method, is characterized in that, comprising:
Semiconductor substrate is provided;
Described Semiconductor substrate is cleaned;
Semiconductor substrate after cleaning is positioned in bag ultra-pure water ozoniferous, formation is positioned at the interface oxide layer of semiconductor substrate surface, the temperature of described ultra-pure water, for being more than or equal to 30 degrees centigrade, is less than or equal to 200 degrees centigrade, and the mass concentration of described ozone is 50-500ppm;
Form the high K dielectric layer on described interface oxide layer;
The described high K dielectric layer of etching and interface oxide layer;
Form metal gates on described high K dielectric layer and interface oxide layer;
Formation source/drain region in described Semiconductor substrate.
9. transistorized manufacture method as claimed in claim 8, is characterized in that, described cleaning utilizes hydrofluoric acid to carry out.
10. transistorized manufacture method as claimed in claim 9, is characterized in that, the mass concentration of described hydrofluoric acid is 10%～0.01%, and the time of described cleaning is no more than 60 minutes.
11. transistorized manufacture method as claimed in claim 9, is characterized in that, the time interval of the step of described cleaning step and described formation interface oxide layer is for being no more than 30 minutes.
12. transistorized manufacture method as claimed in claim 8, is characterized in that, the Semiconductor substrate after described cleaning is positioned in bag ultra-pure water ozoniferous and soaks 1～2000 second.
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| CN2010105326165A CN102468152B (en) | 2010-11-01 | 2010-11-01 | Manufacturing method of gate medium layer and transistor |
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| CN103579113B (en) * | 2012-08-03 | 2017-02-08 | 中国科学院微电子研究所 | Complementary field effect transistor with double-work function metal gates and manufacturing method thereof |
| CN105869988B (en) * | 2015-01-20 | 2019-09-24 | 无锡华润上华科技有限公司 | A kind of manufacturing method of semiconductor devices |
| CN108288646A (en) * | 2017-12-14 | 2018-07-17 | 中国科学院微电子研究所 | Fin FET and preparation method thereof |
Citations (3)
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| CN1378241A (en) * | 2001-03-29 | 2002-11-06 | 华邦电子股份有限公司 | Method for improving sheet resistance measuring value stibility under low energy ion implanting |
| CN1964001A (en) * | 2005-11-08 | 2007-05-16 | 财团法人工业技术研究院 | A method to generate super thin oxide layer with ozone water |
| CN101425457A (en) * | 2007-10-30 | 2009-05-06 | 台湾积体电路制造股份有限公司 | High dielectric constant grid dielectric material forming method and a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5837662A (en) * | 1997-12-12 | 1998-11-17 | Memc Electronic Materials, Inc. | Post-lapping cleaning process for silicon wafers |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1378241A (en) * | 2001-03-29 | 2002-11-06 | 华邦电子股份有限公司 | Method for improving sheet resistance measuring value stibility under low energy ion implanting |
| CN1964001A (en) * | 2005-11-08 | 2007-05-16 | 财团法人工业技术研究院 | A method to generate super thin oxide layer with ozone water |
| CN101425457A (en) * | 2007-10-30 | 2009-05-06 | 台湾积体电路制造股份有限公司 | High dielectric constant grid dielectric material forming method and a semiconductor device |
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| Title |
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| US 5,837,662 A,1998.11.17, |
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